Google Git
Sign in
foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-032/e88affe28790cd629b3931541fdb30ee64046d45^!/.
commit
e88affe28790cd629b3931541fdb30ee64046d45
[log]
author
manarabdelaty <manarabdelatty@aucegypt.edu>
Mon Dec 28 18:49:03 2020 +0200
committer
manarabdelaty <manarabdelatty@aucegypt.edu>
Mon Dec 28 18:49:03 2020 +0200
tree
0385b0a7a0dafc21334c79347d56adab77b19b46
parent
914647f379343272c8cfe863582050c761d16511 [diff]
Added N5 simulations

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index d396704..91ad1ee 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile

@@ -36,7 +36,7 @@
 
 %.vvp: %_tb.v %.hex test.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -DFAST -I $(BEHAVIOURAL_MODELS) \
+	iverilog -DFUNCTIONAL -DSIM -DFAST -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I .. -I $(RTL_PATH) \
 	$< -o $@
 else

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 068f2a2..4162781 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v

@@ -18,12 +18,11 @@
 `timescale 1 ns / 1 ps
 
 `define   TEST_FILE   "../sw_n5/test.hex" 
-`define   SIM_TIME    600_000
+`define   SIM_TIME    3000_000
 `define   SIM_LEVEL   0
 
 `define SOC_SETUP_TIME 800*2001
 
-`include "caravel.v"
 `include "spiflash.v"
 
 `include "sst26wf080b.v"
@@ -76,6 +75,8 @@
 `include "user_project/NfiVe32.v"
 `include "user_project/soc_core.v"
 
+`include "caravel.v"
+
 `endif
 
 module io_ports_tb;
@@ -142,7 +143,6 @@
 		RSTB <= 1'b1;	    // Release reset
 		#(`SOC_SETUP_TIME);
 		#(`SIM_TIME);
-	    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
 	    $finish;
 	end
 
@@ -217,7 +217,7 @@
 
 endmodule
 
-module terminal #(parameter bit_time = 160) (input rx);
+module terminal #(parameter bit_time = 400) (input rx);
 
     integer i;
     reg [7:0] char;

diff --git a/verilog/rtl/user_project/IPs/DFFRAMBB.v b/verilog/rtl/user_project/IPs/DFFRAMBB.v
index 5599bc8..2825426 100644
--- a/verilog/rtl/user_project/IPs/DFFRAMBB.v
+++ b/verilog/rtl/user_project/IPs/DFFRAMBB.v

@@ -67,14 +67,46 @@
 endmodule
 
 module DEC2x4 (
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
     input           EN,
     input   [1:0]   A,
     output  [3:0]   SEL
 );
-    sky130_fd_sc_hd__nor3b_4    AND0 ( .Y(SEL[0]), .A(A[0]),   .B(A[1]), .C_N(EN) );
-    sky130_fd_sc_hd__and3b_4    AND1 ( .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) );
-    sky130_fd_sc_hd__and3b_4    AND2 ( .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) );
-    sky130_fd_sc_hd__and3_4     AND3 ( .X(SEL[3]), .A(A[1]),   .B(A[0]), .C(EN) );
+    sky130_fd_sc_hd__nor3b_4    AND0 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .Y(SEL[0]), .A(A[0]),   .B(A[1]), .C_N(EN) );
+    sky130_fd_sc_hd__and3b_4    AND1 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) );
+    sky130_fd_sc_hd__and3b_4    AND2 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) );
+    sky130_fd_sc_hd__and3_4     AND3 ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(SEL[3]), .A(A[1]),   .B(A[0]), .C(EN) );
     
 endmodule
 
@@ -123,11 +155,22 @@
 endmodule
 
 module MUX4x1_32(
+`ifdef USE_POWER_PINS
+    input VPWR,
+    input VGND,
+`endif
     input   [31:0]      A0, A1, A2, A3,
     input   [1:0]       S,
     output  [31:0]      X
 );
-    sky130_fd_sc_hd__mux4_1 MUX[31:0] (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) );
+    sky130_fd_sc_hd__mux4_1 MUX[31:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) );
 endmodule
 
 module PASS (input [31:0] A, output [31:0] X);

diff --git a/verilog/rtl/user_project/IPs/RAM_3Kx32.v b/verilog/rtl/user_project/IPs/RAM_3Kx32.v
index 57f8fa5..f7dbf25 100644
--- a/verilog/rtl/user_project/IPs/RAM_3Kx32.v
+++ b/verilog/rtl/user_project/IPs/RAM_3Kx32.v

@@ -2,6 +2,10 @@
 `default_nettype none
 
 module RAM_3Kx32 (
+`ifdef USE_POWER_PINS
+    VPWR,
+    VGND,
+`endif
     CLK,
     WE,
     EN,
@@ -9,6 +13,12 @@
     Do,
     A
 );
+
+`ifdef USE_POWER_PINS
+    input VPWR;
+    input VGND;
+`endif
+
     input           CLK;
     input   [3:0]   WE;
     input           EN;
@@ -41,9 +51,29 @@
         
     endgenerate 
     
-    MUX4x1_32 MUX ( .A0(_Do_[0]), .A1(_Do_[1]), .A2(_Do_[2]), .A3(32'b0), .S(A[11:10]), .X(Do_pre) );
-    DEC2x4 DEC ( .EN(EN), .A(A[11:10]), .SEL(_EN_) );
+    MUX4x1_32 MUX ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .A0(_Do_[0]), .A1(_Do_[1]), .A2(_Do_[2]), .A3(32'b0), .S(A[11:10]), .X(Do_pre) 
+    );
+    DEC2x4 DEC ( 
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+    `endif
+        .EN(EN), .A(A[11:10]), .SEL(_EN_)
+    );
 
-    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
+    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (
+    `ifdef USE_POWER_PINS
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPWR),
+        .VNB(VGND),
+    `endif
+        .X(Do), .A(Do_pre)
+    );
     
-endmodule
\ No newline at end of file
+endmodule

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_GPIO.v b/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_GPIO.v
deleted file mode 100644
index 8441800..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_GPIO.v
+++ /dev/null

@@ -1,165 +0,0 @@
-`timescale 1ns/1ns
-    module AHBlite_GPIO (
-    // AHB Interface
-    // clock and reset 
-    input  wire        HCLK,    
-    //input  wire        HCLKG,   // Gated clock
-    input  wire        HRESETn, // Reset
-
-    // input ports
-    input   wire        HSEL,    // Select
-    input   wire [23:2] HADDR,   // Address
-    input   wire        HREADY, // 
-    input   wire        HWRITE,  // Write control
-    input   wire [1:0]  HTRANS,    // AHB transfer type
-    input   wire [2:0]  HSIZE,    // AHB hsize
-    input   wire [31:0] HWDATA,  // Write data
-
-    // output ports
-    output wire [31:0] HRDATA,  // Read data
-    output wire        HREADYOUT,  // Device ready
-    output wire [1:0]   HRESP,
-
-    output wire [15:0] IRQ,
-	
-    // IP Interface
-	// WGPIODIN register/fields
-	input [15:0] WGPIODIN,
-	// WGPIODOUT register/fields
-	output [15:0] WGPIODOUT,
-	// WGPIOPU register/fields
-	output [15:0] WGPIOPU,
-	// WGPIOPD register/fields
-	output [15:0] WGPIOPD,
-	// WGPIODIR register/fields
-	output [15:0] WGPIODIR
-);
-    reg         IOSEL;
-    reg [23:0]  IOADDR;
-    reg         IOWRITE;    // I/O transfer direction
-    reg [2:0]   IOSIZE;     // I/O transfer size
-    reg         IOTRANS;
-
-    // registered HSEL, update only if selected to reduce toggling
-    always @(posedge HCLK or negedge HRESETn) begin
-        if (~HRESETn)
-            IOSEL <= 1'b0;
-        else
-            IOSEL <= HSEL & HREADY;
-    end
-    
-    // registered address, update only if selected to reduce toggling
-    always @(posedge HCLK or negedge HRESETn) begin
-        if (~HRESETn)
-            IOADDR <= 24'd0;
-        else
-            IOADDR <= {HADDR[23:2], 2'b0};
-    end
-
-    // Data phase write control
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-      if (~HRESETn)
-        IOWRITE <= 1'b0;
-      else
-        IOWRITE <= HWRITE;
-    end
-  
-    // registered hsize, update only if selected to reduce toggling
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-      if (~HRESETn)
-        IOSIZE <= {3{1'b0}};
-      else
-        IOSIZE <= HSIZE[2:0];
-    end
-  
-    // registered HTRANS, update only if selected to reduce toggling
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-      if (~HRESETn)
-        IOTRANS <= 1'b0;
-      else
-        IOTRANS <= HTRANS[1];
-    end
-    
-    wire rd_enable;
-    assign  rd_enable = IOSEL & (~IOWRITE) & IOTRANS; 
-    wire wr_enable = IOTRANS & IOWRITE & IOSEL;
-    
-
-    reg [15:0] WGPIODOUT;
-    reg [15:0] WGPIOPU;
-    reg [15:0] WGPIOPD;
-    reg [15:0] WGPIODIR;
-    reg [15:0] WGPIOIM;
-    wire[15:0] WGPIODIN;
-
-	// Register: WGPIODOUT
-    wire WGPIODOUT_select = wr_enable & (IOADDR[23:2] == 22'h1);
-    
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-        if (~HRESETn)
-            WGPIODOUT <= 16'h0;
-        else if (WGPIODOUT_select)
-            WGPIODOUT <= HWDATA;
-    end
-    
-	// Register: WGPIOPU
-    wire WGPIOPU_select = wr_enable & (IOADDR[23:2] == 22'h2);
-    
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-        if (~HRESETn)
-            WGPIOPU <= 16'h0;
-        else if (WGPIOPU_select)
-            WGPIOPU <= HWDATA;
-    end
-    
-	// Register: WGPIOPD
-    wire WGPIOPD_select = wr_enable & (IOADDR[23:2] == 22'h3);
-    
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-        if (~HRESETn)
-            WGPIOPD <= 16'h0;
-        else if (WGPIOPD_select)
-            WGPIOPD <= HWDATA;
-    end
-    
-	// Register: WGPIODIR
-    wire WGPIODIR_select = wr_enable & (IOADDR[23:2] == 22'h4);
-    
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-        if (~HRESETn)
-            WGPIODIR <= 16'h0;
-        else if (WGPIODIR_select)
-            WGPIODIR <= HWDATA;
-    end
-    
-    // Register: IM
-    wire WGPIOIM_select = wr_enable & (IOADDR[23:2] == 22'h5);
-    
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-        if (~HRESETn)
-            WGPIOIM <= 16'h0;
-        else if (WGPIOIM_select)
-            WGPIOIM <= HWDATA;
-    end
-    
-    assign IRQ = (~WGPIODIR) & WGPIOIM;
-
-    assign HRDATA = 
-      	(IOADDR[23:2] == 22'h0) ? {16'd0,WGPIODIN} : 
-      	(IOADDR[23:2] == 22'h1) ? {16'd0,WGPIODOUT} : 
-      	(IOADDR[23:2] == 22'h2) ? {16'd0,WGPIOPU} : 
-      	(IOADDR[23:2] == 22'h3) ? {16'd0,WGPIOPD} : 
-      	(IOADDR[23:2] == 22'h4) ? {16'd0,WGPIODIR} :
-        (IOADDR[23:2] == 22'h5) ? {16'd0,WGPIOIM} : 
-	32'hDEADBEEF;
-	assign HREADYOUT = 1'b1;     // Always ready
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_bus0.v b/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_bus0.v
deleted file mode 100644
index b655a1a..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_bus0.v
+++ /dev/null

@@ -1,77 +0,0 @@
-
-    `timescale 1ns/1ns
-    module AHBlite_BUS0(
-        input wire HCLK,
-        input wire HRESETn,
-      
-        // Master Interface
-        input wire [31:0] HADDR,
-        input wire [31:0] HWDATA, 
-        output wire [31:0] HRDATA,
-        output wire        HREADY,
-        // Slave # 0
-        output wire         HSEL_S0,
-        input wire          HREADY_S0,
-        input wire  [31:0]  HRDATA_S0,
-        // Slave # 1
-        output wire         HSEL_S1,
-        input wire          HREADY_S1,
-        input wire  [31:0]  HRDATA_S1,
-        // Slave # 2
-        output wire         HSEL_S2,
-        input wire          HREADY_S2,
-        input wire  [31:0]  HRDATA_S2,
-        // Slave # 3
-        output wire         HSEL_S3,
-        input wire          HREADY_S3,
-        input wire  [31:0]  HRDATA_S3,
-
-        // Slave # 4
-        output wire         HSEL_S4,
-        input wire          HREADY_S4,
-        input wire  [31:0]  HRDATA_S4,
-
-
-        // SubSystem # 0
-        output wire         HSEL_SS0,
-        input wire          HREADY_SS0,
-        input wire  [31:0]  HRDATA_SS0
-    );
-        wire [7:0]  PAGE = HADDR[31:24];
-        reg [7:0] APAGE;
-
-        always@ (posedge HCLK or negedge HRESETn) begin
-        if(!HRESETn)
-            APAGE <= 8'h0;
-        else if(HREADY)
-            APAGE <= PAGE;
-        end
-
-    	assign HSEL_S0 = (PAGE == 8'h00);
-		assign HSEL_S1 = (PAGE == 8'h20);
-		assign HSEL_S2 = (PAGE == 8'h48);
-		assign HSEL_S3 = (PAGE == 8'h49);
-        assign HSEL_S4 = (PAGE == 8'h4A);
-		assign HSEL_SS0 = (PAGE == 8'h40);
-	
-
-        assign HREADY =
-			(APAGE == 8'h00) ? HREADY_S0 :
-			(APAGE == 8'h20) ? HREADY_S1 :
-			(APAGE == 8'h48) ? HREADY_S2 :
-			(APAGE == 8'h49) ? HREADY_S3 :
-            (APAGE == 8'h4A) ? HREADY_S4 :
-			(APAGE == 8'h40) ? HREADY_SS0 :
-			1'b1;
-
-
-        assign HRDATA =
-			(APAGE == 8'h00) ? HRDATA_S0 :
-			(APAGE == 8'h20) ? HRDATA_S1 :
-			(APAGE == 8'h48) ? HRDATA_S2 :
-			(APAGE == 8'h49) ? HRDATA_S3 :
-            (APAGE == 8'h4A) ? HRDATA_S4 :
-			(APAGE == 8'h40) ? HRDATA_SS0 :
-			32'hDEADBEEF;
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_db_reg.v b/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_db_reg.v
deleted file mode 100644
index b46d639..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_db_reg.v
+++ /dev/null

@@ -1,101 +0,0 @@
-`timescale 1ns/1ns
-    module AHBlite_db_reg (
-    // AHB Interface
-    // clock and reset 
-    input  wire        HCLK,    
-    //input  wire        HCLKG,   // Gated clock
-    input  wire        HRESETn, // Reset
-
-    // input ports
-    input   wire        HSEL,    // Select
-    input   wire [23:2] HADDR,   // Address
-    input   wire        HREADY, // 
-    input   wire        HWRITE,  // Write control
-    input   wire [1:0]  HTRANS,    // AHB transfer type
-    input   wire [2:0]  HSIZE,    // AHB hsize
-    input   wire [31:0] HWDATA,  // Write data
-
-    // output ports
-    output wire [31:0] HRDATA,  // Read data
-    output wire        HREADYOUT,  // Device ready
-    output wire [1:0]   HRESP,
-		// IP Interface
-	// db_reg register/fields
-	output [3:0] db_reg
-
-
-);
-    reg         IOSEL;
-    reg [23:0]  IOADDR;
-    reg         IOWRITE;    // I/O transfer direction
-    reg [2:0]   IOSIZE;     // I/O transfer size
-    reg         IOTRANS;
-
-    // registered HSEL, update only if selected to reduce toggling
-    always @(posedge HCLK or negedge HRESETn) begin
-        if (~HRESETn)
-            IOSEL <= 1'b0;
-        else
-            IOSEL <= HSEL & HREADY;
-    end
-    
-    // registered address, update only if selected to reduce toggling
-    always @(posedge HCLK or negedge HRESETn) begin
-        if (~HRESETn)
-            IOADDR <= 24'd0;
-        else
-            IOADDR <= HADDR[23:0];
-    end
-
-    // Data phase write control
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-      if (~HRESETn)
-        IOWRITE <= 1'b0;
-      else
-        IOWRITE <= HWRITE;
-    end
-  
-    // registered hsize, update only if selected to reduce toggling
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-      if (~HRESETn)
-        IOSIZE <= {3{1'b0}};
-      else
-        IOSIZE <= HSIZE[2:0];
-    end
-  
-    // registered HTRANS, update only if selected to reduce toggling
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-      if (~HRESETn)
-        IOTRANS <= 1'b0;
-      else
-        IOTRANS <= HTRANS[1];
-    end
-    
-    wire rd_enable;
-    assign  rd_enable = IOSEL & (~IOWRITE) & IOTRANS; 
-    wire wr_enable = IOTRANS & IOWRITE & IOSEL;
-    
-
-    reg [3:0] db_reg;
-
-
-	// Register: db_reg
-    wire db_reg_select = wr_enable & (IOADDR[23:2] == 20'h0);
-    
-    always @(posedge HCLK or negedge HRESETn)
-    begin
-        if (~HRESETn)
-            db_reg <= 4'h0;
-        else if (db_reg_select)
-            db_reg <= HWDATA;
-    end
-    
-    assign HRDATA = 
-      	(IOADDR[23:2] == 22'h0) ? {28'd0,db_reg} : 
-	32'hDEADBEEF;
-	assign HREADYOUT = 1'b1;     // Always ready
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_sys_0.v b/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_sys_0.v
deleted file mode 100644
index 9b931cb..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/AHBlite_sys_0.v
+++ /dev/null

@@ -1,309 +0,0 @@
-
-`timescale 1ns/1ns
-
-//`define DBG
-module AHBlite_sys_0(
-		input HCLK,
-		input HRESETn,
-     
-		input [31: 0] HADDR,
-		input [31: 0] HWDATA,
-		input HWRITE,
-		input [1: 0] HTRANS,
-		input [2:0] HSIZE,
-
-		output HREADY,
-		output [31: 0] HRDATA,
-
-		input wire [3: 0] fdi_S0,
-		output wire [3: 0] fdo_S0,
-		output wire [0: 0] fdoe_S0,
-		output wire [0: 0] fsclk_S0,
-		output wire [0: 0] fcen_S0,
-		input wire [31: 0] SRAMRDATA_S1,
-		output wire [3: 0] SRAMWEN_S1,
-		output wire [31: 0] SRAMWDATA_S1,
-		output wire [0: 0] SRAMCS0_S1,
-		//output wire [0: 0] SRAMCS1_S1,
-		//output wire [0: 0] SRAMCS2_S1,
-		//output wire [0: 0] SRAMCS3_S1,
-		output wire [11: 0] SRAMADDR_S1,
-		input wire [15: 0] GPIOIN_S2,
-		output wire [15: 0] GPIOOUT_S2,
-		output wire [15: 0] GPIOPU_S2,
-		output wire [15: 0] GPIOPD_S2,
-		output wire [15: 0] GPIOOEN_S2,
-		output wire [3:0] db_reg,
-		input wire [0: 0] RsRx_SS0_S0,
-		output wire [0: 0] RsTx_SS0_S0,
-		output wire [0: 0] uart_irq_SS0_S0,
-		input wire [0: 0] RsRx_SS0_S1,
-		output wire [0: 0] RsTx_SS0_S1,
-		output wire [0: 0] uart_irq_SS0_S1,
-		input wire [0: 0] MSI_SS0_S2,
-		output wire [0: 0] MSO_SS0_S2,
-		output wire [0: 0] SSn_SS0_S2,
-		output wire [0: 0] SCLK_SS0_S2,
-		input wire [0: 0] MSI_SS0_S3,
-		output wire [0: 0] MSO_SS0_S3,
-		output wire [0: 0] SSn_SS0_S3,
-		output wire [0: 0] SCLK_SS0_S3,
-		input wire [0: 0] scl_i_SS0_S4,
-		output wire [0: 0] scl_o_SS0_S4,
-		output wire [0: 0] scl_oen_o_SS0_S4,
-		input wire [0: 0] sda_i_SS0_S4,
-		output wire [0: 0] sda_o_SS0_S4,
-		output wire [0: 0] sda_oen_o_SS0_S4,
-		input wire [0: 0] scl_i_SS0_S5,
-		output wire [0: 0] scl_o_SS0_S5,
-		output wire [0: 0] scl_oen_o_SS0_S5,
-		input wire [0: 0] sda_i_SS0_S5,
-		output wire [0: 0] sda_o_SS0_S5,
-		output wire [0: 0] sda_oen_o_SS0_S5,
-		output wire [0: 0] pwm_SS0_S6,
-		output wire [0: 0] pwm_SS0_S7,
-
-		output wire [31:0] IRQ
-	);
-        
-		//assign IRQ[15:0] = 0;
-
-        //Inputs
-        wire HSEL_S0, HSEL_S1, HSEL_S2, HSEL_S3, HSEL_S4, HSEL_SS0;
-
-        //Outputs
-        wire    [31:0]   HRDATA_S0, HRDATA_S1, HRDATA_S2, HRDATA_S3, HRDATA_S4, HRDATA_SS0, HRDATA;
-        wire             HREADY_S0, HREADY_S1, HREADY_S2, HREADY_S3, HREADY_S4, HREADY_SS0, HREADY;
-        wire  [1:0]   HRESP;
-       // wire          IRQ;
-        
-		wire [15: 0] WGPIODIN_S2;
-		wire [15: 0] WGPIODOUT_S2;
-		wire [15: 0] WGPIOPU_S2;
-		wire [15: 0] WGPIOPD_S2;
-		wire [15: 0] WGPIODIR_S2;
-
-	//Digital module # 0
-	QSPI_XIP_CTRL S0 ( 
-		.HCLK(HCLK),
-		.HRESETn(HRESETn),
-		.HSEL(HSEL_S0),
-		.HADDR(HADDR),
-		.HREADY(HREADY),
-		.HWRITE(HWRITE),
-		.HTRANS(HTRANS),
-		//.HSIZE(HSIZE),
-		.HRDATA(HRDATA_S0),
-		.HREADYOUT(HREADY_S0),
-		.din(fdi_S0),
-		.dout(fdo_S0),
-		.douten(fdoe_S0),
-		.sck(fsclk_S0),
-		.ce_n(fcen_S0)
-	);
-
-		
-	//Digital module # 1
-	AHBSRAM S1 ( 
-		.HCLK(HCLK),
-		.HRESETn(HRESETn),
-		.HSEL(HSEL_S1),
-		.HADDR(HADDR),
-		.HREADY(HREADY),
-		.HWRITE(HWRITE),
-		.HTRANS(HTRANS),
-		.HSIZE(HSIZE),
-		.HWDATA(HWDATA),
-		.HRDATA(HRDATA_S1),
-		.HREADYOUT(HREADY_S1),
-		.SRAMRDATA(SRAMRDATA_S1),
-		.SRAMWEN(SRAMWEN_S1),
-		.SRAMWDATA(SRAMWDATA_S1),
-		.SRAMCS0(SRAMCS0_S1),
-		//.SRAMCS1(SRAMCS1_S1),
-		//.SRAMCS2(SRAMCS2_S1),
-		//.SRAMCS3(SRAMCS3_S1),
-		.SRAMADDR(SRAMADDR_S1)
-	);
-		
-	//Digital module # 2
-	GPIO S2 ( 
-		.WGPIODIN(WGPIODIN_S2),
-		.WGPIODOUT(WGPIODOUT_S2),
-		.WGPIOPU(WGPIOPU_S2),
-		.WGPIOPD(WGPIOPD_S2),
-		.WGPIODIR(WGPIODIR_S2),
-		.GPIOIN(GPIOIN_S2),
-		.GPIOOUT(GPIOOUT_S2),
-		.GPIOPU(GPIOPU_S2),
-		.GPIOPD(GPIOPD_S2),
-		.GPIOOEN(GPIOOEN_S2)
-	);
-		
-	//AHB Slave # 2
-	AHBlite_GPIO S_2 (
-		.HCLK(HCLK),
-		.HRESETn(HRESETn),
-		.HSEL(HSEL_S2),
-		.HADDR(HADDR[23:2]),
-		.HREADY(HREADY),
-		.HWRITE(HWRITE),
-		.HTRANS(HTRANS),
-		.HSIZE(HSIZE),
-		.HWDATA(HWDATA),
-
-		.WGPIODIN(WGPIODIN_S2),
-		.WGPIODOUT(WGPIODOUT_S2),
-		.WGPIOPU(WGPIOPU_S2),
-		.WGPIOPD(WGPIOPD_S2),
-		.WGPIODIR(WGPIODIR_S2),
-		.HRDATA(HRDATA_S2),
-		.HREADYOUT(HREADY_S2),
-		.HRESP(HRESP), 
-
-		.IRQ(IRQ[15:0])
-	);
-			
-	//AHB Slave # 3
-/*	
-	AHBlite_db_reg S_3 (
-		.HCLK(HCLK),
-		.HRESETn(HRESETn),
-		.HSEL(HSEL_S3),
-		.HADDR(HADDR[23:2]),
-		.HREADY(HREADY),
-		.HWRITE(HWRITE),
-		.HTRANS(HTRANS),
-		.HSIZE(HSIZE),
-		.HWDATA(HWDATA),
-		.db_reg(db_reg),
-
-		.HRDATA(HRDATA_S3),
-		.HREADYOUT(HREADY_S3),
-		.HRESP(HRESP)
-	);
-*/
-
-	AHB_SPM S_3 (
-		.HCLK(HCLK),
-		.HRESETn(HRESETn),
-		.HSEL(HSEL_S3),
-		.HADDR(HADDR),
-		.HREADY(HREADY),
-		.HWRITE(HWRITE),
-		.HTRANS(HTRANS),
-		.HSIZE(HSIZE),
-		.HWDATA(HWDATA),
-		//.db_reg(db_reg),
-
-		.HRDATA(HRDATA_S3),
-		.HREADYOUT(HREADY_S3),
-		.HRESP(HRESP)
-	);		
-
-
-	// SLAVE 4
-	assign HREADY_S4 = 1;
-
-
-	//AHB Bus
-	AHBlite_BUS0 AHB(
-		.HCLK(HCLK),
-		.HRESETn(HRESETn),
-		
-		// Master Interface
-		.HADDR(HADDR),
-		.HWDATA(HWDATA), 
-		.HREADY(HREADY),
-		.HRDATA(HRDATA),
-		
-		// Slave # 0
-		.HSEL_S0(HSEL_S0),
-		.HREADY_S0(HREADY_S0),
-		.HRDATA_S0(HRDATA_S0),
-		
-		// Slave # 1
-		.HSEL_S1(HSEL_S1),
-		.HREADY_S1(HREADY_S1),
-		.HRDATA_S1(HRDATA_S1),
-		
-		// Slave # 2
-		.HSEL_S2(HSEL_S2),
-		.HREADY_S2(HREADY_S2),
-		.HRDATA_S2(HRDATA_S2),
-		
-		// Slave # 3
-		.HSEL_S3(HSEL_S3),
-		.HREADY_S3(HREADY_S3),
-		.HRDATA_S3(HRDATA_S3),
-		
-		// Slave # 4
-		.HSEL_S4(HSEL_S4),
-		.HREADY_S4(HREADY_S4),
-		.HRDATA_S4(HRDATA_S4),
-
-		// Subsystem # 0
-		.HSEL_SS0(HSEL_SS0),
-		.HREADY_SS0(HREADY_SS0),
-		.HRDATA_SS0(HRDATA_SS0)
-	);
-
-    //SubSystem Instantiation #0 
-    apb_sys_0 apb_sys_inst_0(
-        // Global signals 
-        .HCLK(HCLK),
-        .HRESETn(HRESETn),
-    
-        // AHB Slave inputs 
-        .HADDR(HADDR),
-        .HTRANS(HTRANS),
-        .HWRITE(HWRITE),
-        .HWDATA(HWDATA),
-        .HSEL(HSEL_SS0),
-        .HREADY(HREADY),
-    
-        // AHB Slave outputs 
-        .HRDATA(HRDATA_SS0),
-        .HREADYOUT(HREADY_SS0),
-		.RsRx_S0(RsRx_SS0_S0),
-		.RsTx_S0(RsTx_SS0_S0),
-
-		.RsRx_S1(RsRx_SS0_S1),
-		.RsTx_S1(RsTx_SS0_S1),
-
-		.MSI_S2(MSI_SS0_S2),
-		.MSO_S2(MSO_SS0_S2),
-		.SSn_S2(SSn_SS0_S2),
-		.SCLK_S2(SCLK_SS0_S2),
-
-		.MSI_S3(MSI_SS0_S3),
-		.MSO_S3(MSO_SS0_S3),
-		.SSn_S3(SSn_SS0_S3),
-		.SCLK_S3(SCLK_SS0_S3),
-
-		.scl_i_S4(scl_i_SS0_S4),
-		.scl_o_S4(scl_o_SS0_S4),
-		.scl_oen_o_S4(scl_oen_o_SS0_S4),
-		.sda_i_S4(sda_i_SS0_S4),
-		.sda_o_S4(sda_o_SS0_S4),
-		.sda_oen_o_S4(sda_oen_o_SS0_S4),
-
-		.scl_i_S5(scl_i_SS0_S5),
-		.scl_o_S5(scl_o_SS0_S5),
-		.scl_oen_o_S5(scl_oen_o_SS0_S5),
-		.sda_i_S5(sda_i_SS0_S5),
-		.sda_o_S5(sda_o_SS0_S5),
-		.sda_oen_o_S5(sda_oen_o_SS0_S5),
-
-		.pwm_S6(pwm_SS0_S6),
-		.pwm_S7(pwm_SS0_S7),
-
-		.IRQ(IRQ[31:16])
-    );
-`ifdef DBG
-    always @(posedge HCLK)
-	if(HTRANS[1] & HREADY)
-        $display("Mem request (%d) A:%X", HWRITE, HADDR);
-`endif
-    endmodule
-        
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/AHB_2_APB.v b/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/AHB_2_APB.v
deleted file mode 100644
index 813c8be..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/AHB_2_APB.v
+++ /dev/null

@@ -1,214 +0,0 @@
-
-`timescale 1ns/1ns
-module ahb_2_apb(
-// Global signals --------------------------------------------------------------
-  input wire          HCLK,
-  input wire          HRESETn,
-  
-// AHB Slave inputs ------------------------------------------------------------  
-  input wire  [31:0]  HADDR,
-  input wire  [1:0]   HTRANS,
-  input wire          HWRITE,
-  input wire  [31:0]  HWDATA,
-  input wire          HSEL,
-  input wire          HREADY,
-  
-// APB Master inputs -----------------------------------------------------------
-  input wire  [31:0]  PRDATA,
-  input wire          PREADY,
-  
-// AHB Slave outputs -----------------------------------------------------------
-  output wire [31:0]  HRDATA,
-  output reg          HREADYOUT,
-  
-// APB Master outputs ----------------------------------------------------------
-  output wire [31:0]  PWDATA,
-  output reg          PENABLE,
-  output reg  [31:0]  PADDR,
-  output reg          PWRITE,
-  
-  output wire         PCLK,
-  output wire         PRESETn
-);
-  
-//Constants
-
-  `define ST_IDLE 2'b00
-  `define ST_SETUP 2'b01
-  `define ST_ACCESS 2'b11
-
-
-  wire          Transfer;
-  wire          ACRegEn;
-  reg   [31:0]  last_HADDR;
-  reg           last_HWRITE;
-  
-  wire  [31:0]  HADDR_Mux;
-  
-  reg   [1:0]   CurrentState;
-  reg   [1:0]   NextState;
-  
-  reg           HREADY_next;  
-  wire          PWRITE_next;
-  wire          PENABLE_next;
-  wire          APBEn;
-  
-  
-  assign PCLK = HCLK;
-  assign PRESETn = HRESETn;
-  
-  assign Transfer = HSEL & HREADY & HTRANS[1];
-  
-  assign ACRegEn = HSEL & HREADY;
-  
-  //Set register values of AHB signals
-  
-  always @ (posedge HCLK, negedge HRESETn)
-  begin
-    if(!HRESETn)
-      begin
-        last_HADDR <= {32{1'b0}};
-        last_HWRITE <= 1'b0;
-      end
-    
-    else
-      begin
-        if(ACRegEn)
-          begin
-            last_HADDR <= HADDR;
-            last_HWRITE <= HWRITE;
-          end
-      end
-  end
-  
-  
-// Next State Logic
-
-  always @ (CurrentState,PREADY, Transfer)
-  begin
-    case (CurrentState)
-      `ST_IDLE: 
-        begin
-          if(Transfer)
-            NextState = `ST_SETUP;
-          else
-            NextState = `ST_IDLE;
-        end
-      
-      `ST_SETUP:
-        begin
-          NextState = `ST_ACCESS;
-        end
-      
-      `ST_ACCESS:
-        begin
-          if(!PREADY)
-            NextState = `ST_ACCESS;
-          else
-            begin
-              if(Transfer)
-                NextState = `ST_SETUP;
-              else
-                NextState = `ST_IDLE;
-            end
-        end
-      default:
-        NextState = `ST_IDLE;
-    endcase
-  end
-  
-// State Machine
-
-  always @ (posedge HCLK, negedge HRESETn)
-  begin
-    if(!HRESETn)
-      CurrentState <= `ST_IDLE;
-    else
-      CurrentState <= NextState;
-  end
-  
-  
-//HREADYOUT
-
-  always @ (NextState, PREADY)
-  begin
-    case (NextState)
-      `ST_IDLE:
-        HREADY_next = 1'b1;
-      `ST_SETUP:
-        HREADY_next = 1'b0;
-      `ST_ACCESS: 
-        HREADY_next = PREADY;
-      default:
-        HREADY_next = 1'b1;
-    endcase
-  end
-
-  always @(posedge HCLK, negedge HRESETn)
-  begin
-    if(!HRESETn)
-      HREADYOUT <= 1'b1;
-    else
-      HREADYOUT <= HREADY_next;
-  end
-
-  
-// HADDRMux
-  assign HADDR_Mux = ((NextState == `ST_SETUP) ? HADDR :
-                      last_HADDR);
-
-//APBen
-  assign APBEn = ((NextState == `ST_SETUP) ? 1'b1 : 1'b0);
-
-//PADDR
-
-  always @ (posedge HCLK, negedge HRESETn)
-  begin
-    if (!HRESETn)
-      PADDR <= {31{1'b0}};
-    else
-      begin
-        if (APBEn)
-          PADDR <= HADDR_Mux;
-      end
-  end
-
-//PWDATA
-
-  assign PWDATA = HWDATA;
-
-
-//PENABLE
-
-  assign PENABLE_next = ((NextState == `ST_ACCESS) ? 1'b1 : 1'b0);
-  
-  always @ (posedge HCLK, negedge HRESETn)
-  begin
-    if(!HRESETn)
-      PENABLE <= 1'b0;
-    else
-      PENABLE <= PENABLE_next;
-  end
-  
-//PWRITE
-
-  assign PWRITE_next = ((NextState == `ST_SETUP) ? HWRITE : last_HWRITE);
-
-  always @ (posedge HCLK, negedge HRESETn)
-  begin
-    if(!HRESETn)
-      PWRITE <= 1'b0;
-    else
-      begin
-        if (APBEn)
-          PWRITE <= PWRITE_next;
-      end
-  end
-
-
-//HRDATA
-  assign HRDATA = PRDATA;
-
-
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_PWM32.v b/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_PWM32.v
deleted file mode 100644
index bc7aa6f..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_PWM32.v
+++ /dev/null

@@ -1,112 +0,0 @@
-/*
-        APB Wrapper for PWM32 macro 
-        Automatically generated from a JSON description by Mohamed Shalan
-        Generated at 2020-11-26 12:31:7 
-*/
-
-`timescale 1ns/1ns
-   
-module APB_PWM32 (
-	// APB Interface
-	// clock and reset 
-	input  wire        PCLK,    
-	//input  wire        PCLKG,   // Gated clock
-	input  wire        PRESETn, // Reset
-
-	// input ports
-	input  wire        PSEL,    // Select
-	input  wire [19:2] PADDR,   // Address
-	input  wire        PENABLE, // Transfer control
-	input  wire        PWRITE,  // Write control
-	input  wire [31:0] PWDATA,  // Write data
-
-	// output ports
-	output wire [31:0] PRDATA,  // Read data
-	output wire        PREADY,
-	// Device ready
-
-	// IP Interface
-	// PRE register/fields
-	output [31:0] PRE,
-
-
-	// TMRCMP1 register/fields
-	output [31:0] TMRCMP1,
-
-
-	// TMRCMP2 register/fields
-	output [31:0] TMRCMP2,
-
-
-	// TMREN register/fields
-	output [0:0] TMREN
-
-);
-	wire rd_enable;
-	wire wr_enable;
-	assign  rd_enable = PSEL & (~PWRITE); 
-	assign  wr_enable = PSEL & PWRITE & (PENABLE); 
-	assign  PREADY = 1'b1;
-    
-
-    reg [31:0] PRE;
-
-    reg [31:0] TMRCMP1;
-
-    reg [31:0] TMRCMP2;
-
-    reg [0:0] TMREN;
-
-
-	// Register: PRE
-	wire PRE_select = wr_enable & (PADDR[19:2] == 18'h4);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            PRE <= 32'h0;
-        else if (PRE_select)
-            PRE <= PWDATA;
-    end
-    
-	// Register: TMRCMP1
-	wire TMRCMP1_select = wr_enable & (PADDR[19:2] == 18'h1);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            TMRCMP1 <= 32'h0;
-        else if (TMRCMP1_select)
-            TMRCMP1 <= PWDATA;
-    end
-    
-	// Register: TMRCMP2
-	wire TMRCMP2_select = wr_enable & (PADDR[19:2] == 18'h2);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            TMRCMP2 <= 32'h0;
-        else if (TMRCMP2_select)
-            TMRCMP2 <= PWDATA;
-    end
-    
-	// Register: TMREN
-	wire TMREN_select = wr_enable & (PADDR[19:2] == 18'h8);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            TMREN <= 1'h0;
-        else if (TMREN_select)
-            TMREN <= PWDATA;
-    end
-    
-	assign PRDATA = 
-		(PADDR[19:2] == 18'h4) ? PRE : 
-		(PADDR[19:2] == 18'h1) ? TMRCMP1 : 
-		(PADDR[19:2] == 18'h2) ? TMRCMP2 : 
-		(PADDR[19:2] == 18'h8) ? {31'd0,TMREN} : 
-		32'hDEADBEEF;
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_TIMER32.v b/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_TIMER32.v
deleted file mode 100644
index cfdfe7a..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_TIMER32.v
+++ /dev/null

@@ -1,142 +0,0 @@
-/*
-        APB Wrapper for TIMER32 macro 
-        Automatically generated from a JSON description by Mohamed Shalan
-        Generated at 2020-11-26 12:31:7 
-*/
-
-`timescale 1ns/1ns
-   
-module APB_TIMER32 (
-	// APB Interface
-	// clock and reset 
-	input  wire        PCLK,    
-	//input  wire        PCLKG,   // Gated clock
-	input  wire        PRESETn, // Reset
-
-	// input ports
-	input  wire        PSEL,    // Select
-	input  wire [19:2] PADDR,   // Address
-	input  wire        PENABLE, // Transfer control
-	input  wire        PWRITE,  // Write control
-	input  wire [31:0] PWDATA,  // Write data
-
-	// output ports
-	output wire [31:0] PRDATA,  // Read data
-	output wire        PREADY,
-	// Device ready
-
-	// IP Interface
-	output		IRQ,
-
-	// TMR register/fields
-	input [31:0] TMR,
-
-
-	// PRE register/fields
-	output [31:0] PRE,
-
-
-	// TMRCMP register/fields
-	output [31:0] TMRCMP,
-
-
-	// TMROV register/fields
-	input [0:0] TMROV,
-
-
-	// TMROVCLR register/fields
-	output [0:0] TMROVCLR,
-
-
-	// TMREN register/fields
-	output [0:0] TMREN
-
-);
-	wire rd_enable;
-	wire wr_enable;
-	assign  rd_enable = PSEL & (~PWRITE); 
-	assign  wr_enable = PSEL & PWRITE & (PENABLE); 
-	assign  PREADY = 1'b1;
-    
-
-    reg [31:0] PRE;
-
-    reg [31:0] TMRCMP;
-
-    reg [0:0] TMROVCLR;
-
-    reg [0:0] TMREN;
-
-    wire[31:0] TMR;
-    wire[0:0] TMROV;
-
-	// Register: PRE
-	wire PRE_select = wr_enable & (PADDR[19:2] == 18'h1);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            PRE <= 32'h0;
-        else if (PRE_select)
-            PRE <= PWDATA;
-    end
-    
-	// Register: TMRCMP
-	wire TMRCMP_select = wr_enable & (PADDR[19:2] == 18'h2);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            TMRCMP <= 32'h0;
-        else if (TMRCMP_select)
-            TMRCMP <= PWDATA;
-    end
-    
-	// Register: TMROVCLR
-	wire TMROVCLR_select = wr_enable & (PADDR[19:2] == 18'h4);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            TMROVCLR <= 1'h0;
-        else if (TMROVCLR_select)
-            TMROVCLR <= PWDATA;
-    end
-    
-	// Register: TMREN
-	wire TMREN_select = wr_enable & (PADDR[19:2] == 18'h5);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            TMREN <= 1'h0;
-        else if (TMREN_select)
-            TMREN <= PWDATA;
-    end
-    
-
-	// IRQ Enable Register @ offset 0x100
-	reg[0:0] IRQEN;
-	wire IRQEN_select = wr_enable & (PADDR[19:2] == 18'h40);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            IRQEN <= 1'h0;
-        else if (IRQEN_select)
-            IRQEN <= PWDATA;
-    end
-    
-	assign IRQ = ( TMROV & IRQEN[0] ) ;
-
-	assign PRDATA = 
-		(PADDR[19:2] == 18'h0) ? TMR : 
-		(PADDR[19:2] == 18'h1) ? PRE : 
-		(PADDR[19:2] == 18'h2) ? TMRCMP : 
-		(PADDR[19:2] == 18'h3) ? {31'd0,TMROV} : 
-		(PADDR[19:2] == 18'h4) ? {31'd0,TMROVCLR} : 
-		(PADDR[19:2] == 18'h5) ? {31'd0,TMREN} : 
-		(PADDR[19:2] == 18'h40) ? {31'd0,IRQEN} : 
-		32'hDEADBEEF;
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_WDT32.v b/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_WDT32.v
deleted file mode 100644
index 06348d8..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_WDT32.v
+++ /dev/null

@@ -1,124 +0,0 @@
-/*
-        APB Wrapper for WDT32 macro 
-        Automatically generated from a JSON description by Mohamed Shalan
-        Generated at 2020-11-26 12:31:7 
-*/
-
-`timescale 1ns/1ns
-   
-module APB_WDT32 (
-	// APB Interface
-	// clock and reset 
-	input  wire        PCLK,    
-	//input  wire        PCLKG,   // Gated clock
-	input  wire        PRESETn, // Reset
-
-	// input ports
-	input  wire        PSEL,    // Select
-	input  wire [19:2] PADDR,   // Address
-	input  wire        PENABLE, // Transfer control
-	input  wire        PWRITE,  // Write control
-	input  wire [31:0] PWDATA,  // Write data
-
-	// output ports
-	output wire [31:0] PRDATA,  // Read data
-	output wire        PREADY,
-	// Device ready
-
-	// IP Interface
-	output		IRQ,
-
-	// WDTMR register/fields
-	input [31:0] WDTMR,
-
-
-	// WDLOAD register/fields
-	output [31:0] WDLOAD,
-
-
-	// WDOV register/fields
-	input [0:0] WDOV,
-
-
-	// WDOVCLR register/fields
-	output [0:0] WDOVCLR,
-
-
-	// WDEN register/fields
-	output [0:0] WDEN
-
-);
-	wire rd_enable;
-	wire wr_enable;
-	assign  rd_enable = PSEL & (~PWRITE); 
-	assign  wr_enable = PSEL & PWRITE & (PENABLE); 
-	assign  PREADY = 1'b1;
-    
-
-    reg [31:0] WDLOAD;
-
-    reg [0:0] WDOVCLR;
-
-    reg [0:0] WDEN;
-
-    wire[31:0] WDTMR;
-    wire[0:0] WDOV;
-
-	// Register: WDLOAD
-	wire WDLOAD_select = wr_enable & (PADDR[19:2] == 18'h1);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            WDLOAD <= 32'h0;
-        else if (WDLOAD_select)
-            WDLOAD <= PWDATA;
-    end
-    
-	// Register: WDOVCLR
-	wire WDOVCLR_select = wr_enable & (PADDR[19:2] == 18'h4);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            WDOVCLR <= 1'h0;
-        else if (WDOVCLR_select)
-            WDOVCLR <= PWDATA;
-    end
-    
-	// Register: WDEN
-	wire WDEN_select = wr_enable & (PADDR[19:2] == 18'h5);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            WDEN <= 1'h0;
-        else if (WDEN_select)
-            WDEN <= PWDATA;
-    end
-    
-
-	// IRQ Enable Register @ offset 0x100
-	reg[0:0] IRQEN;
-	wire IRQEN_select = wr_enable & (PADDR[19:2] == 18'h40);
-
-    always @(posedge PCLK or negedge PRESETn)
-    begin
-        if (~PRESETn)
-            IRQEN <= 1'h0;
-        else if (IRQEN_select)
-            IRQEN <= PWDATA;
-    end
-    
-	assign IRQ = ( WDOV & IRQEN[0] ) ;
-
-	assign PRDATA = 
-		(PADDR[19:2] == 18'h0) ? WDTMR : 
-		(PADDR[19:2] == 18'h1) ? WDLOAD : 
-		(PADDR[19:2] == 18'h3) ? {31'd0,WDOV} : 
-		(PADDR[19:2] == 18'h4) ? {31'd0,WDOVCLR} : 
-		(PADDR[19:2] == 18'h5) ? {31'd0,WDEN} : 
-		(PADDR[19:2] == 18'h40) ? {31'd0,IRQEN} : 
-		32'hDEADBEEF;
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_bus0.v b/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_bus0.v
deleted file mode 100644
index 403e27c..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_bus0.v
+++ /dev/null

@@ -1,236 +0,0 @@
-
-`timescale 1ns/1ns
-
-module APB_BUS0 #(
-    // Parameters to enable/disable ports
-    
-    parameter PORT0_ENABLE  = 1,
-    parameter PORT1_ENABLE  = 1,
-    parameter PORT2_ENABLE  = 1,
-    parameter PORT3_ENABLE  = 1,
-    parameter PORT4_ENABLE  = 1,
-    parameter PORT5_ENABLE  = 1,
-    parameter PORT6_ENABLE  = 1,
-    parameter PORT7_ENABLE  = 1,
-    parameter PORT8_ENABLE  = 1,
-    parameter PORT9_ENABLE  = 1,
-    parameter PORT10_ENABLE  = 1,
-    parameter PORT11_ENABLE  = 1,
-    parameter PORT12_ENABLE  = 1,
-    parameter PORT13_ENABLE  = 1,
-    parameter PORT14_ENABLE  = 1,
-    parameter PORT15_ENABLE  = 1
-    )
-
-
-    (
-    // --------------------------------------------------------------------------
-    // Port Definitions
-    // --------------------------------------------------------------------------
-    //MODULE INPUTS
-      input  wire  [3:0]  DEC_BITS,
-      input  wire         PSEL,
-          
-    // Slave # 0
-    output wire         PSEL_S0,
-    input wire          PREADY_S0,
-    input wire  [31:0]  PRDATA_S0,
-    input wire          PSLVERR_S0,
-    // Slave # 1
-    output wire         PSEL_S1,
-    input wire          PREADY_S1,
-    input wire  [31:0]  PRDATA_S1,
-    input wire          PSLVERR_S1,
-    // Slave # 2
-    output wire         PSEL_S2,
-    input wire          PREADY_S2,
-    input wire  [31:0]  PRDATA_S2,
-    input wire          PSLVERR_S2,
-    // Slave # 3
-    output wire         PSEL_S3,
-    input wire          PREADY_S3,
-    input wire  [31:0]  PRDATA_S3,
-    input wire          PSLVERR_S3,
-    // Slave # 4
-    output wire         PSEL_S4,
-    input wire          PREADY_S4,
-    input wire  [31:0]  PRDATA_S4,
-    input wire          PSLVERR_S4,
-    // Slave # 5
-    output wire         PSEL_S5,
-    input wire          PREADY_S5,
-    input wire  [31:0]  PRDATA_S5,
-    input wire          PSLVERR_S5,
-    // Slave # 6
-    output wire         PSEL_S6,
-    input wire          PREADY_S6,
-    input wire  [31:0]  PRDATA_S6,
-    input wire          PSLVERR_S6,
-    // Slave # 7
-    output wire         PSEL_S7,
-    input wire          PREADY_S7,
-    input wire  [31:0]  PRDATA_S7,
-    input wire          PSLVERR_S7,
-    // Slave # 8
-    output wire         PSEL_S8,
-    input wire          PREADY_S8,
-    input wire  [31:0]  PRDATA_S8,
-    input wire          PSLVERR_S8,
-    // Slave # 9
-    output wire         PSEL_S9,
-    input wire          PREADY_S9,
-    input wire  [31:0]  PRDATA_S9,
-    input wire          PSLVERR_S9,
-    // Slave # 10
-    output wire         PSEL_S10,
-    input wire          PREADY_S10,
-    input wire  [31:0]  PRDATA_S10,
-    input wire          PSLVERR_S10,
-    // Slave # 11
-    output wire         PSEL_S11,
-    input wire          PREADY_S11,
-    input wire  [31:0]  PRDATA_S11,
-    input wire          PSLVERR_S11,
-    // Slave # 12
-    output wire         PSEL_S12,
-    input wire          PREADY_S12,
-    input wire  [31:0]  PRDATA_S12,
-    input wire          PSLVERR_S12,
-    // Slave # 13
-    output wire         PSEL_S13,
-    input wire          PREADY_S13,
-    input wire  [31:0]  PRDATA_S13,
-    input wire          PSLVERR_S13,
-    // Slave # 14
-    output wire         PSEL_S14,
-    input wire          PREADY_S14,
-    input wire  [31:0]  PRDATA_S14,
-    input wire          PSLVERR_S14,
-    // Slave # 15
-    output wire         PSEL_S15,
-    input wire          PREADY_S15,
-    input wire  [31:0]  PRDATA_S15,
-    input wire          PSLVERR_S15,
-    //MODULE OUTPUTS
-    output wire         PREADY,
-    output wire [31:0]  PRDATA,
-    output wire         PSLVERR
-);
- 
-    wire [15:0] en  = { 
-                        (PORT15_ENABLE  == 1),
-                        (PORT14_ENABLE  == 1),
-                        (PORT13_ENABLE  == 1),
-                        (PORT12_ENABLE  == 1),
-                        (PORT11_ENABLE  == 1),
-                        (PORT10_ENABLE  == 1),
-                        (PORT9_ENABLE  == 1),
-                        (PORT8_ENABLE  == 1),
-                        (PORT7_ENABLE  == 1),
-                        (PORT6_ENABLE  == 1),
-                        (PORT5_ENABLE  == 1),
-                        (PORT4_ENABLE  == 1),
-                        (PORT3_ENABLE  == 1),
-                        (PORT2_ENABLE  == 1),
-                        (PORT1_ENABLE  == 1),
-                        (PORT0_ENABLE  == 1)
-                        };
-
-    wire [15:0] dec  = { 
-                        (DEC_BITS  == 4'd15),
-                        (DEC_BITS  == 4'd14),
-                        (DEC_BITS  == 4'd13),
-                        (DEC_BITS  == 4'd12),
-                        (DEC_BITS  == 4'd11),
-                        (DEC_BITS  == 4'd10),
-                        (DEC_BITS  == 4'd9),
-                        (DEC_BITS  == 4'd8),
-                        (DEC_BITS  == 4'd7),
-                        (DEC_BITS  == 4'd6),
-                        (DEC_BITS  == 4'd5),
-                        (DEC_BITS  == 4'd4),
-                        (DEC_BITS  == 4'd3),
-                        (DEC_BITS  == 4'd2),
-                        (DEC_BITS  == 4'd1),
-                        (DEC_BITS  == 4'd0)
-                        };
-
-
-    // Setting PSEL 
-    assign PSEL_S0 = PSEL & dec[0] & en[0];
-    assign PSEL_S1 = PSEL & dec[1] & en[1];
-    assign PSEL_S2 = PSEL & dec[2] & en[2];
-    assign PSEL_S3 = PSEL & dec[3] & en[3];
-    assign PSEL_S4 = PSEL & dec[4] & en[4];
-    assign PSEL_S5 = PSEL & dec[5] & en[5];
-    assign PSEL_S6 = PSEL & dec[6] & en[6];
-    assign PSEL_S7 = PSEL & dec[7] & en[7];
-    assign PSEL_S8 = PSEL & dec[8] & en[8];
-    assign PSEL_S9 = PSEL & dec[9] & en[9];
-    assign PSEL_S10 = PSEL & dec[10] & en[10];
-    assign PSEL_S11 = PSEL & dec[11] & en[11];
-    assign PSEL_S12 = PSEL & dec[12] & en[12];
-    assign PSEL_S13 = PSEL & dec[13] & en[13];
-    assign PSEL_S14 = PSEL & dec[14] & en[14];
-    assign PSEL_S15 = PSEL & dec[15] & en[15];
-
-    // Setting PREADY
-
-    assign PREADY = ~PSEL |
-        ( dec[0] & ( PREADY_S0 | en[0] ) ) |
-        ( dec[1] & ( PREADY_S1 | en[1] ) ) |
-        ( dec[2] & ( PREADY_S2 | en[2] ) ) |
-        ( dec[3] & ( PREADY_S3 | en[3] ) ) |
-        ( dec[4] & ( PREADY_S4 | en[4] ) ) |
-        ( dec[5] & ( PREADY_S5 | en[5] ) ) |
-        ( dec[6] & ( PREADY_S6 | en[6] ) ) |
-        ( dec[7] & ( PREADY_S7 | en[7] ) ) |
-        ( dec[8] & ( PREADY_S8 | en[8] ) ) |
-        ( dec[9] & ( PREADY_S9 | en[9] ) ) |
-        ( dec[10] & ( PREADY_S10 | en[10] ) ) |
-        ( dec[11] & ( PREADY_S11 | en[11] ) ) |
-        ( dec[12] & ( PREADY_S12 | en[12] ) ) |
-        ( dec[13] & ( PREADY_S13 | en[13] ) ) |
-        ( dec[14] & ( PREADY_S14 | en[14] ) ) |
-        ( dec[15] & ( PREADY_S15 | en[15] ) );
-
-    // Setting PSLVERR
-
-    assign PSLVERR = ( PSEL_S0 & PSLVERR_S0 ) |
-        ( PSEL_S1 & PSLVERR_S1 ) |
-        ( PSEL_S2 & PSLVERR_S2 ) |
-        ( PSEL_S3 & PSLVERR_S3 ) |
-        ( PSEL_S4 & PSLVERR_S4 ) |
-        ( PSEL_S5 & PSLVERR_S5 ) |
-        ( PSEL_S6 & PSLVERR_S6 ) |
-        ( PSEL_S7 & PSLVERR_S7 ) |
-        ( PSEL_S8 & PSLVERR_S8 ) |
-        ( PSEL_S9 & PSLVERR_S9 ) |
-        ( PSEL_S10 & PSLVERR_S10 ) |
-        ( PSEL_S11 & PSLVERR_S11 ) |
-        ( PSEL_S12 & PSLVERR_S12 ) |
-        ( PSEL_S13 & PSLVERR_S13 ) |
-        ( PSEL_S14 & PSLVERR_S14 ) |
-        ( PSEL_S15 & PSLVERR_S15 );
-
-    // Setting PRDATA
-
-    assign PRDATA = ( {32{PSEL_S0}} & PRDATA_S0 ) |
-        ( {32{PSEL_S1}} & PRDATA_S1 ) |
-        ( {32{PSEL_S2}} & PRDATA_S2 ) |
-        ( {32{PSEL_S3}} & PRDATA_S3 ) |
-        ( {32{PSEL_S4}} & PRDATA_S4 ) |
-        ( {32{PSEL_S5}} & PRDATA_S5 ) |
-        ( {32{PSEL_S6}} & PRDATA_S6 ) |
-        ( {32{PSEL_S7}} & PRDATA_S7 ) |
-        ( {32{PSEL_S8}} & PRDATA_S8 ) |
-        ( {32{PSEL_S9}} & PRDATA_S9 ) |
-        ( {32{PSEL_S10}} & PRDATA_S10 ) |
-        ( {32{PSEL_S11}} & PRDATA_S11 ) |
-        ( {32{PSEL_S12}} & PRDATA_S12 ) |
-        ( {32{PSEL_S13}} & PRDATA_S13 ) |
-        ( {32{PSEL_S14}} & PRDATA_S14 ) |
-        ( {32{PSEL_S15}} & PRDATA_S15 );
-    
-endmodule
-    
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_sys_0.v b/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_sys_0.v
deleted file mode 100644
index 4fd19ac..0000000
--- a/verilog/rtl/user_project/rtl/AHB_sys_0/APB_sys_0/APB_sys_0.v
+++ /dev/null

@@ -1,756 +0,0 @@
-
-`timescale 1ns/1ns
-module apb_sys_0(
-    // Global signals 
-    input wire          HCLK,
-    input wire          HRESETn,
-
-    // AHB Slave inputs 
-    input wire  [31:0]  HADDR,
-    input wire  [1:0]   HTRANS,
-    input wire          HWRITE,
-    input wire  [31:0]  HWDATA,
-    input wire          HSEL,
-    input wire          HREADY,
-
-    // AHB Slave outputs 
-    output wire [31:0]  HRDATA,
-    output wire         HREADYOUT,
-	input wire [0: 0] RsRx_S0,
-	output wire [0: 0] RsTx_S0,
-
-	input wire [0: 0] RsRx_S1,
-	output wire [0: 0] RsTx_S1,
-
-	input wire [0: 0] MSI_S2,
-	output wire [0: 0] MSO_S2,
-	output wire [0: 0] SSn_S2,
-	output wire [0: 0] SCLK_S2,
-
-	input wire [0: 0] MSI_S3,
-	output wire [0: 0] MSO_S3,
-	output wire [0: 0] SSn_S3,
-	output wire [0: 0] SCLK_S3,
-
-	input wire [0: 0] scl_i_S4,
-	output wire [0: 0] scl_o_S4,
-	output wire [0: 0] scl_oen_o_S4,
-	input wire [0: 0] sda_i_S4,
-	output wire [0: 0] sda_o_S4,
-	output wire [0: 0] sda_oen_o_S4,
-
-	input wire [0: 0] scl_i_S5,
-	output wire [0: 0] scl_o_S5,
-	output wire [0: 0] scl_oen_o_S5,
-	input wire [0: 0] sda_i_S5,
-	output wire [0: 0] sda_o_S5,
-	output wire [0: 0] sda_oen_o_S5,
-
-	output wire [0: 0] pwm_S6,
-	output wire [0: 0] pwm_S7,
-
-    output [31:16] IRQ
-);
-    
-    // APB Master Signals
-    wire PCLK;
-    wire PRESETn;
-    wire [31:0] PADDR;
-    wire PWRITE;
-    wire [31:0] PWDATA;
-    wire PENABLE;
-    
-    // APB Slave Signals
-    wire PREADY;
-    wire [31:0] PRDATA ;
-    wire 		PSLVERR;
-
-    //ADDED PSEL Signal
-    //wire PSEL = HSEL; 
-    wire PSEL_next = HSEL;
-    reg PSEL_next_next;
-    reg PSEL;
-    always @ (posedge HCLK, negedge HRESETn)
-    begin
-        if(!HRESETn)
-        PSEL <= 1'b0;
-        else begin
-            PSEL_next_next <= PSEL_next;
-            PSEL <= PSEL_next | PSEL_next_next;
-        end
-    end
-    //Instantiating the bridge
-
-    ahb_2_apb AHB2APB_BR (
-        .HCLK(HCLK),
-        .HRESETn(HRESETn),
-        .HADDR(HADDR[31:0]),
-        .HSEL(HSEL),
-        .HREADY(HREADY),
-        .HTRANS(HTRANS[1:0]),
-        .HWDATA(HWDATA[31:0]),
-        .HWRITE(HWRITE),
-        .HRDATA(HRDATA),
-        .HREADYOUT(HREADYOUT),
-        .PCLK(PCLK),
-        .PRESETn(PRESETn),
-        .PADDR(PADDR[31:0]),
-        .PWRITE(PWRITE),
-        .PWDATA(PWDATA[31:0]),
-        .PENABLE(PENABLE),
-        .PREADY(PREADY),
-        .PRDATA(PRDATA[31:0])
-    );
-        
-        
-    //Bus Signals
-        
-    //Slave #0
-    wire PSEL_S0;
-    wire [31:0] PRDATA_S0;
-    wire PREADY_S0;
-    wire PSLVERR_S0;
-    
-    //Slave #1
-    wire PSEL_S1;
-    wire [31:0] PRDATA_S1;
-    wire PREADY_S1;
-    wire PSLVERR_S1;
-    
-    //Slave #2
-    wire PSEL_S2;
-    wire [31:0] PRDATA_S2;
-    wire PREADY_S2;
-    wire PSLVERR_S2;
-    
-    //Slave #3
-    wire PSEL_S3;
-    wire [31:0] PRDATA_S3;
-    wire PREADY_S3;
-    wire PSLVERR_S3;
-    
-    //Slave #4
-    wire PSEL_S4;
-    wire [31:0] PRDATA_S4;
-    wire PREADY_S4;
-    wire PSLVERR_S4;
-    
-    //Slave #5
-    wire PSEL_S5;
-    wire [31:0] PRDATA_S5;
-    wire PREADY_S5;
-    wire PSLVERR_S5;
-    
-    //Slave #6
-    wire PSEL_S6;
-    wire [31:0] PRDATA_S6;
-    wire PREADY_S6;
-    wire PSLVERR_S6;
-    
-    //Slave #7
-    wire PSEL_S7;
-    wire [31:0] PRDATA_S7;
-    wire PREADY_S7;
-    wire PSLVERR_S7;
-    
-    //Slave #8
-    wire PSEL_S8;
-    wire [31:0] PRDATA_S8;
-    wire PREADY_S8;
-    wire PSLVERR_S8;
-    
-    //Slave #9
-    wire PSEL_S9;
-    wire [31:0] PRDATA_S9;
-    wire PREADY_S9;
-    wire PSLVERR_S9;
-    
-    //Slave #10
-    wire PSEL_S10;
-    wire [31:0] PRDATA_S10;
-    wire PREADY_S10;
-    wire PSLVERR_S10;
-    
-    //Slave #11
-    wire PSEL_S11;
-    wire [31:0] PRDATA_S11;
-    wire PREADY_S11;
-    wire PSLVERR_S11;
-    
-    //Slave #12
-    wire PSEL_S12;
-    wire [31:0] PRDATA_S12;
-    wire PREADY_S12;
-    wire PSLVERR_S12;
-    
-    //Slave #13
-    wire PSEL_S13;
-    wire [31:0] PRDATA_S13;
-    wire PREADY_S13;
-    wire PSLVERR_S13;
-    
-    //Unused Ports Signals
-    wire PSEL_S14;
-    wire PSEL_S15;
-
-    wire [31: 0] PRE_S6;
-    wire [31: 0] TMRCMP1_S6;
-    wire [31: 0] TMRCMP2_S6;
-    wire [0: 0] TMREN_S6;
-    wire [31: 0] PRE_S7;
-    wire [31: 0] TMRCMP1_S7;
-    wire [31: 0] TMRCMP2_S7;
-    wire [0: 0] TMREN_S7;
-    wire [31: 0] TMR_S8;
-    wire [31: 0] PRE_S8;
-    wire [31: 0] TMRCMP_S8;
-    wire [0: 0] TMROV_S8;
-    wire [0: 0] TMROVCLR_S8;
-    wire [0: 0] TMREN_S8;
-    wire [31: 0] TMR_S9;
-    wire [31: 0] PRE_S9;
-    wire [31: 0] TMRCMP_S9;
-    wire [0: 0] TMROV_S9;
-    wire [0: 0] TMROVCLR_S9;
-    wire [0: 0] TMREN_S9;
-    wire [31: 0] TMR_S10;
-    wire [31: 0] PRE_S10;
-    wire [31: 0] TMRCMP_S10;
-    wire [0: 0] TMROV_S10;
-    wire [0: 0] TMROVCLR_S10;
-    wire [0: 0] TMREN_S10;
-    wire [31: 0] TMR_S11;
-    wire [31: 0] PRE_S11;
-    wire [31: 0] TMRCMP_S11;
-    wire [0: 0] TMROV_S11;
-    wire [0: 0] TMROVCLR_S11;
-    wire [0: 0] TMREN_S11;
-    wire [31: 0] WDTMR_S12;
-    wire [31: 0] WDLOAD_S12;
-    wire [0: 0] WDOV_S12;
-    wire [0: 0] WDOVCLR_S12;
-    wire [0: 0] WDEN_S12;
-    wire [31: 0] WDTMR_S13;
-    wire [31: 0] WDLOAD_S13;
-    wire [0: 0] WDOV_S13;
-    wire [0: 0] WDOVCLR_S13;
-    wire [0: 0] WDEN_S13;
-
-    assign IRQ[31:28] = 4'd0;
-
-        //Digital module # 0
-        APB_UART S0 (
-            .PCLK(PCLK),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S0),
-            .PADDR(PADDR),
-            .PREADY(PREADY_S0),
-            .PWRITE(PWRITE),
-            .PWDATA(PWDATA),
-            .PRDATA(PRDATA_S0),
-            .PENABLE(PENABLE),
-
-            .RsRx(RsRx_S0),   
-            .RsTx(RsTx_S0),   
-            .uart_irq(IRQ[16])
-        );
-
-        //Digital module # 1
-        APB_UART S1 (
-            .PCLK(PCLK),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S1),
-            .PADDR(PADDR),
-            .PREADY(PREADY_S1),
-            .PWRITE(PWRITE),
-            .PWDATA(PWDATA),
-            .PRDATA(PRDATA_S1),
-            .PENABLE(PENABLE),
-
-            .RsRx(RsRx_S1),   
-            .RsTx(RsTx_S1),   
-            .uart_irq(IRQ[17])
-        );
-
-        //Digital module # 2
-        APB_SPI S2 (
-            .PCLK(PCLK),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S2),
-            .PADDR(PADDR),
-            .PREADY(PREADY_S2),
-            .PWRITE(PWRITE),
-            .PWDATA(PWDATA),
-            .PRDATA(PRDATA_S2),
-            .PENABLE(PENABLE),
-
-            .MSI(MSI_S2),   
-            .MSO(MSO_S2),   
-            .SSn(SSn_S2),   
-            .SCLK(SCLK_S2),
-
-            .IRQ(IRQ[18])
-        );
-
-        //Digital module # 3
-        APB_SPI S3 (
-            .PCLK(PCLK),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S3),
-            .PADDR(PADDR),
-            .PREADY(PREADY_S3),
-            .PWRITE(PWRITE),
-            .PWDATA(PWDATA),
-            .PRDATA(PRDATA_S3),
-            .PENABLE(PENABLE),
-
-            .MSI(MSI_S3),   
-            .MSO(MSO_S3),   
-            .SSn(SSn_S3),   
-            .SCLK(SCLK_S3),
-
-            .IRQ(IRQ[19])
-        );
-
-        //Digital module # 4
-        APB_I2C S4 (
-            .PCLK(PCLK),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S4),
-            .PADDR(PADDR),
-            .PREADY(PREADY_S4),
-            .PWRITE(PWRITE),
-            .PWDATA(PWDATA),
-            .PRDATA(PRDATA_S4),
-            .PENABLE(PENABLE),
-
-            .scl_i(scl_i_S4),   
-            .scl_o(scl_o_S4),   
-            .scl_oen_o(scl_oen_o_S4),   
-            .sda_i(sda_i_S4),   
-            .sda_o(sda_o_S4),   
-            .sda_oen_o(sda_oen_o_S4),
-
-            .IRQ(IRQ[20])
-        );
-
-        //Digital module # 5
-        APB_I2C S5 (
-            .PCLK(PCLK),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S5),
-            .PADDR(PADDR),
-            .PREADY(PREADY_S5),
-            .PWRITE(PWRITE),
-            .PWDATA(PWDATA),
-            .PRDATA(PRDATA_S5),
-            .PENABLE(PENABLE),
-
-            .scl_i(scl_i_S5),   
-            .scl_o(scl_o_S5),   
-            .scl_oen_o(scl_oen_o_S5),   
-            .sda_i(sda_i_S5),   
-            .sda_o(sda_o_S5),   
-            .sda_oen_o(sda_oen_o_S5),
-
-            .IRQ(IRQ[21])
-        );
-
-        //Digital module # 6
-        PWM32 S6 (
-            .clk(PCLK),
-            .rst(~PRESETn),
-            .PRE(PRE_S6),
-            .TMRCMP1(TMRCMP1_S6),
-            .TMRCMP2(TMRCMP2_S6),
-            .TMREN(TMREN_S6),
-
-            .pwm(pwm_S6)
-        );
-
-        //APB Slave # 6
-        APB_PWM32 S_6 (
-            .PCLK(PCLK),
-            //.PCLKG(),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S6),
-            .PADDR(PADDR [19:2]),
-            .PREADY(PREADY_S6),
-            .PWRITE(PWRITE),
-            .PENABLE(PENABLE),
-            .PWDATA(PWDATA),
-
-            .PRE(PRE_S6),
-            .TMRCMP1(TMRCMP1_S6),
-            .TMRCMP2(TMRCMP2_S6),
-            .TMREN(TMREN_S6),
-            .PRDATA(PRDATA_S6)
-        );
-
-        //Digital module # 7
-        PWM32 S7 (
-            .clk(PCLK),
-            .rst(~PRESETn),
-            .PRE(PRE_S7),
-            .TMRCMP1(TMRCMP1_S7),
-            .TMRCMP2(TMRCMP2_S7),
-            .TMREN(TMREN_S7),
-
-            .pwm(pwm_S7)
-        );
-
-        //APB Slave # 7
-        APB_PWM32 S_7 (
-            .PCLK(PCLK),
-            //.PCLKG(),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S7),
-            .PADDR(PADDR [19:2]),
-            .PREADY(PREADY_S7),
-            .PWRITE(PWRITE),
-            .PENABLE(PENABLE),
-            .PWDATA(PWDATA),
-
-            .PRE(PRE_S7),
-            .TMRCMP1(TMRCMP1_S7),
-            .TMRCMP2(TMRCMP2_S7),
-            .TMREN(TMREN_S7),
-            .PRDATA(PRDATA_S7)
-        );
-
-        //Digital module # 8
-        TIMER32 S8 (
-            .clk(PCLK),
-            .rst(~PRESETn),
-            .TMR(TMR_S8),
-            .PRE(PRE_S8),
-            .TMRCMP(TMRCMP_S8),
-            .TMROV(TMROV_S8),
-            .TMROVCLR(TMROVCLR_S8),
-            .TMREN(TMREN_S8)
-
-        );
-
-        //APB Slave # 8
-        APB_TIMER32 S_8 (
-            .PCLK(PCLK),
-            //.PCLKG(),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S8),
-            .PADDR(PADDR [19:2]),
-            .PREADY(PREADY_S8),
-            .PWRITE(PWRITE),
-            .PENABLE(PENABLE),
-            .PWDATA(PWDATA),
-
-            .TMR(TMR_S8),
-            .PRE(PRE_S8),
-            .TMRCMP(TMRCMP_S8),
-            .TMROV(TMROV_S8),
-            .TMROVCLR(TMROVCLR_S8),
-            .TMREN(TMREN_S8),
-
-            .IRQ(IRQ[22]),
-            .PRDATA(PRDATA_S8)
-        );
-
-        //Digital module # 9
-        TIMER32 S9 (
-            .clk(PCLK),
-            .rst(~PRESETn),
-            .TMR(TMR_S9),
-            .PRE(PRE_S9),
-            .TMRCMP(TMRCMP_S9),
-            .TMROV(TMROV_S9),
-            .TMROVCLR(TMROVCLR_S9),
-            .TMREN(TMREN_S9)
-
-        );
-
-        //APB Slave # 9
-        APB_TIMER32 S_9 (
-            .PCLK(PCLK),
-            //.PCLKG(),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S9),
-            .PADDR(PADDR [19:2]),
-            .PREADY(PREADY_S9),
-            .PWRITE(PWRITE),
-            .PENABLE(PENABLE),
-            .PWDATA(PWDATA),
-
-            .TMR(TMR_S9),
-            .PRE(PRE_S9),
-            .TMRCMP(TMRCMP_S9),
-            .TMROV(TMROV_S9),
-            .TMROVCLR(TMROVCLR_S9),
-            .TMREN(TMREN_S9),
-
-            .IRQ(IRQ[23]),
-            .PRDATA(PRDATA_S9)
-        );
-
-        //Digital module # 10
-        TIMER32 S10 (
-            .clk(PCLK),
-            .rst(~PRESETn),
-            .TMR(TMR_S10),
-            .PRE(PRE_S10),
-            .TMRCMP(TMRCMP_S10),
-            .TMROV(TMROV_S10),
-            .TMROVCLR(TMROVCLR_S10),
-            .TMREN(TMREN_S10)
-        );
-
-        //APB Slave # 10
-        APB_TIMER32 S_10 (
-            .PCLK(PCLK),
-            //.PCLKG(),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S10),
-            .PADDR(PADDR [19:2]),
-            .PREADY(PREADY_S10),
-            .PWRITE(PWRITE),
-            .PENABLE(PENABLE),
-            .PWDATA(PWDATA),
-
-            .TMR(TMR_S10),
-            .PRE(PRE_S10),
-            .TMRCMP(TMRCMP_S10),
-            .TMROV(TMROV_S10),
-            .TMROVCLR(TMROVCLR_S10),
-            .TMREN(TMREN_S10),
-
-            .IRQ(IRQ[24]),
-            .PRDATA(PRDATA_S10)
-        );
-
-        //Digital module # 11
-        TIMER32 S11 (
-            .clk(PCLK),
-            .rst(~PRESETn),
-            .TMR(TMR_S11),
-            .PRE(PRE_S11),
-            .TMRCMP(TMRCMP_S11),
-            .TMROV(TMROV_S11),
-            .TMROVCLR(TMROVCLR_S11),
-            .TMREN(TMREN_S11)
-
-        );
-
-        //APB Slave # 11
-        APB_TIMER32 S_11 (
-            .PCLK(PCLK),
-            //.PCLKG(),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S11),
-            .PADDR(PADDR [19:2]),
-            .PREADY(PREADY_S11),
-            .PWRITE(PWRITE),
-            .PENABLE(PENABLE),
-            .PWDATA(PWDATA),
-
-            .TMR(TMR_S11),
-            .PRE(PRE_S11),
-            .TMRCMP(TMRCMP_S11),
-            .TMROV(TMROV_S11),
-            .TMROVCLR(TMROVCLR_S11),
-            .TMREN(TMREN_S11),
-            .IRQ(IRQ[25]),
-            .PRDATA(PRDATA_S11)
-        );
-
-        //Digital module # 12
-        WDT32 S12 (
-            .clk(PCLK),
-            .rst(~PRESETn),
-            .WDTMR(WDTMR_S12),
-            .WDLOAD(WDLOAD_S12),
-            .WDOV(WDOV_S12),
-            .WDOVCLR(WDOVCLR_S12),
-            .WDEN(WDEN_S12)
-
-        );
-
-        //APB Slave # 12
-        APB_WDT32 S_12 (
-            .PCLK(PCLK),
-            //.PCLKG(),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S12),
-            .PADDR(PADDR [19:2]),
-            .PREADY(PREADY_S12),
-            .PWRITE(PWRITE),
-            .PENABLE(PENABLE),
-            .PWDATA(PWDATA),
-
-            .WDTMR(WDTMR_S12),
-            .WDLOAD(WDLOAD_S12),
-            .WDOV(WDOV_S12),
-            .WDOVCLR(WDOVCLR_S12),
-            .WDEN(WDEN_S12),
-            .IRQ(IRQ[26]),
-            .PRDATA(PRDATA_S12)
-        );
-
-        //Digital module # 13
-        WDT32 S13 (
-            .clk(PCLK),
-            .rst(~PRESETn),
-            .WDTMR(WDTMR_S13),
-            .WDLOAD(WDLOAD_S13),
-            .WDOV(WDOV_S13),
-            .WDOVCLR(WDOVCLR_S13),
-            .WDEN(WDEN_S13)
-
-        );
-
-        //APB Slave # 13
-        APB_WDT32 S_13 (
-            .PCLK(PCLK),
-            //.PCLKG(),
-            .PRESETn(PRESETn),
-            .PSEL(PSEL_S13),
-            .PADDR(PADDR [19:2]),
-            .PREADY(PREADY_S13),
-            .PWRITE(PWRITE),
-            .PENABLE(PENABLE),
-            .PWDATA(PWDATA),
-
-            .WDTMR(WDTMR_S13),
-            .WDLOAD(WDLOAD_S13),
-            .WDOV(WDOV_S13),
-            .WDOVCLR(WDOVCLR_S13),
-            .WDEN(WDEN_S13),
-
-            .IRQ(IRQ[27]),
-            .PRDATA(PRDATA_S13)
-        );
-
-
-        //APB Bus
-        APB_BUS0 #(
-            .PORT0_ENABLE   (1),
-            .PORT1_ENABLE   (1),
-            .PORT2_ENABLE   (1),
-            .PORT3_ENABLE   (1),
-            .PORT4_ENABLE   (1),
-            .PORT5_ENABLE   (1),
-            .PORT6_ENABLE   (1),
-            .PORT7_ENABLE   (1),
-            .PORT8_ENABLE   (1),
-            .PORT9_ENABLE   (1),
-            .PORT10_ENABLE   (1),
-            .PORT11_ENABLE   (1),
-            .PORT12_ENABLE   (1),
-            .PORT13_ENABLE   (1),
-            .PORT14_ENABLE   (0),
-            .PORT15_ENABLE   (0)
-        )
-        apbBus(
-            // Inputs
-            .DEC_BITS   (PADDR[23:20]),
-            .PSEL       (PSEL),
-
-            .PSEL_S0         (PSEL_S0),
-            .PREADY_S0       (PREADY_S0),
-            .PRDATA_S0       (PRDATA_S0),
-            // .PSLVERR0     (timer0_pslverr),
-            .PSLVERR_S0      (1'b0),
-
-            .PSEL_S1         (PSEL_S1),
-            .PREADY_S1       (PREADY_S1),
-            .PRDATA_S1       (PRDATA_S1),
-            // .PSLVERR1     (timer1_pslverr),
-            .PSLVERR_S1      (1'b0),
-
-            .PSEL_S2         (PSEL_S2),
-            .PREADY_S2       (PREADY_S2),
-            .PRDATA_S2       (PRDATA_S2),
-            // .PSLVERR2     (timer2_pslverr),
-            .PSLVERR_S2      (1'b0),
-
-            .PSEL_S3         (PSEL_S3),
-            .PREADY_S3       (PREADY_S3),
-            .PRDATA_S3       (PRDATA_S3),
-            // .PSLVERR3     (timer3_pslverr),
-            .PSLVERR_S3      (1'b0),
-
-            .PSEL_S4         (PSEL_S4),
-            .PREADY_S4       (PREADY_S4),
-            .PRDATA_S4       (PRDATA_S4),
-            // .PSLVERR4     (timer4_pslverr),
-            .PSLVERR_S4      (1'b0),
-
-            .PSEL_S5         (PSEL_S5),
-            .PREADY_S5       (PREADY_S5),
-            .PRDATA_S5       (PRDATA_S5),
-            // .PSLVERR5     (timer5_pslverr),
-            .PSLVERR_S5      (1'b0),
-
-            .PSEL_S6         (PSEL_S6),
-            .PREADY_S6       (PREADY_S6),
-            .PRDATA_S6       (PRDATA_S6),
-            // .PSLVERR6     (timer6_pslverr),
-            .PSLVERR_S6      (1'b0),
-
-            .PSEL_S7         (PSEL_S7),
-            .PREADY_S7       (PREADY_S7),
-            .PRDATA_S7       (PRDATA_S7),
-            // .PSLVERR7     (timer7_pslverr),
-            .PSLVERR_S7      (1'b0),
-
-            .PSEL_S8         (PSEL_S8),
-            .PREADY_S8       (PREADY_S8),
-            .PRDATA_S8       (PRDATA_S8),
-            // .PSLVERR8     (timer8_pslverr),
-            .PSLVERR_S8      (1'b0),
-
-            .PSEL_S9         (PSEL_S9),
-            .PREADY_S9       (PREADY_S9),
-            .PRDATA_S9       (PRDATA_S9),
-            // .PSLVERR9     (timer9_pslverr),
-            .PSLVERR_S9      (1'b0),
-
-            .PSEL_S10         (PSEL_S10),
-            .PREADY_S10       (PREADY_S10),
-            .PRDATA_S10       (PRDATA_S10),
-            // .PSLVERR10     (timer10_pslverr),
-            .PSLVERR_S10      (1'b0),
-
-            .PSEL_S11         (PSEL_S11),
-            .PREADY_S11       (PREADY_S11),
-            .PRDATA_S11       (PRDATA_S11),
-            // .PSLVERR11     (timer11_pslverr),
-            .PSLVERR_S11      (1'b0),
-
-            .PSEL_S12         (PSEL_S12),
-            .PREADY_S12       (PREADY_S12),
-            .PRDATA_S12       (PRDATA_S12),
-            // .PSLVERR12     (timer12_pslverr),
-            .PSLVERR_S12      (1'b0),
-
-            .PSEL_S13         (PSEL_S13),
-            .PREADY_S13       (PREADY_S13),
-            .PRDATA_S13       (PRDATA_S13),
-            // .PSLVERR13     (timer13_pslverr),
-            .PSLVERR_S13      (1'b0),
-
-            .PSEL_S14         (PSEL_S14),
-            .PREADY_S14       (1'b1),
-            .PRDATA_S14       (32'h00000000),
-            .PSLVERR_S14      (1'b0),
-
-            .PSEL_S15         (PSEL_S15),
-            .PREADY_S15       (1'b1),
-            .PRDATA_S15       (32'h00000000),
-            .PSLVERR_S15      (1'b0),
-
-            // Output
-            .PREADY            (PREADY),
-            .PRDATA            (PRDATA),
-            .PSLVERR           (PSLVERR)
-        );
-       
-endmodule
-    
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/DFFRFile.v b/verilog/rtl/user_project/rtl/DFFRFile.v
deleted file mode 100644
index 9fb40b2..0000000
--- a/verilog/rtl/user_project/rtl/DFFRFile.v
+++ /dev/null

@@ -1,140 +0,0 @@
-/* 
-	DFFRFile
-	32x32 Register File with 2RW1W ports and clock gating for SKY130A 
-	~ 3550 Cells
-	< 2ns (no input or output delays)
-*/
-/*
-    	Author: Mohamed Shalan (mshalan@aucegypt.edu)
-*/
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-module DFFRFile (
-	input [4:0] 	R1, R2, RW,
-	input [31:0] 	DW,
-	output [31:0]	D1, D2,
-	input CLK,
-	input WE
-);
-
-	wire [31:0] sel1, sel2, selw;
-
-	DEC5x32 DEC0 ( .A(R1), .SEL(sel1) );
-	DEC5x32 DEC1 ( .A(R2), .SEL(sel2) );
-	DEC5x32 DEC2 ( .A(RW), .SEL(selw) );
-	
-	RFWORD0 RFW0 ( .CLK(CLK), .WE(), .SEL1(sel1[0]), .SEL2(sel2[0]), .SELW(), .D1(D1), .D2(D2), .DW() );	
-
-	generate
-		genvar e;
-		for(e=1; e<32; e=e+1)
-			RFWORD RFW ( .CLK(CLK), .WE(WE), .SEL1(sel1[e]), .SEL2(sel2[e]), .SELW(selw[e]), .D1(D1), .D2(D2), .DW(DW) );	
-	endgenerate
-
-endmodule
-module RFWORD (
-    input CLK,
-    input WE,
-    input SEL1, SEL2, SELW,
-    output [31:0] D1, D2,
-    input [31:0] DW
-);
-
-    wire [31:0]  q_wire;
-    wire   we_wire;
-    wire [3:0]   SEL1_B, SEL2_B;
-    wire [3:0]  GCLK;
-
-    sky130_fd_sc_hd__inv_2 INV1[3:0] (.Y(SEL1_B), .A(SEL1));
-	sky130_fd_sc_hd__inv_2 INV2[3:0] (.Y(SEL2_B), .A(SEL2));
-
-    sky130_fd_sc_hd__and2_1 CGAND ( .A(SELW), .B(WE), .X(we_wire) );
-    sky130_fd_sc_hd__dlclkp_1 CG[3:0] ( .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) );
-
-    generate 
-        genvar i;
-        for(i=0; i<32; i=i+1) begin : BIT
-            sky130_fd_sc_hd__dfxtp_1 FF ( .D(DW[i]), .Q(q_wire[i]), .CLK(GCLK[i/8]) );
-            sky130_fd_sc_hd__ebufn_2 OBUF1 ( .A(q_wire[i]), .Z(D1[i]), .TE_B(SEL1_B[i/8]) );
-			sky130_fd_sc_hd__ebufn_2 OBUF2 ( .A(q_wire[i]), .Z(D2[i]), .TE_B(SEL2_B[i/8]) );
-        end
-		
-    endgenerate 
-endmodule
-
-module RFWORD0 (
-    input CLK,
-    input WE,
-    input SEL1, SEL2, SELW,
-    output [31:0] D1, D2,
-    input [31:0] DW
-);
-
-    wire [31:0]  q_wire;
-    wire   we_wire;
-    wire [3:0]   SEL1_B, SEL2_B;
-    wire [3:0]  GCLK;
-	wire [1:0]	lo;
-
-    sky130_fd_sc_hd__inv_2 INV1[3:0] (.Y(SEL1_B), .A(SEL1));
-	sky130_fd_sc_hd__inv_2 INV2[3:0] (.Y(SEL2_B), .A(SEL2));
-
-	sky130_fd_sc_hd__conb_1 TIE [1:0] (.LO(lo), .HI());
-
-    //sky130_fd_sc_hd__and2_1 CGAND ( .A(SELW), .B(WE), .X(we_wire) );
-    //sky130_fd_sc_hd__dlclkp_1 CG[3:0] ( .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) );
-
-    generate 
-        genvar i;
-        for(i=0; i<32; i=i+1) begin : BIT
-            //sky130_fd_sc_hd__dfxtp_1 FF ( .D(DW[i]), .Q(q_wire[i]), .CLK(GCLK[i/8]) );
-            sky130_fd_sc_hd__ebufn_2 OBUF1 ( .A(lo[0]), .Z(D1[i]), .TE_B(SEL1_B[i/8]) );
-			sky130_fd_sc_hd__ebufn_2 OBUF2 ( .A(lo[1]), .Z(D2[i]), .TE_B(SEL2_B[i/8]) );
-        end
-		
-    endgenerate 
-endmodule
-
-/*
-module DEC2x4 (
-    input           EN,
-    input   [1:0]   A,
-    output  [3:0]   SEL
-);
-    sky130_fd_sc_hd__nor3b_4    AND0 ( .Y(SEL[0]), .A(A[0]),   .B(A[1]), .C_N(EN) );
-    sky130_fd_sc_hd__and3b_4    AND1 ( .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) );
-    sky130_fd_sc_hd__and3b_4    AND2 ( .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) );
-    sky130_fd_sc_hd__and3_4     AND3 ( .X(SEL[3]), .A(A[1]),   .B(A[0]), .C(EN) );
-    
-endmodule
-
-module DEC3x8 (
-    input           EN,
-    input [2:0]     A,
-    output [7:0]    SEL
-);
-    sky130_fd_sc_hd__nor4b_2   AND0 ( .Y(SEL[0])  , .A(A[0]), .B(A[1])  , .C(A[2]), .D_N(EN) ); // 000
-    sky130_fd_sc_hd__and4bb_2   AND1 ( .X(SEL[1])  , .A_N(A[2]), .B_N(A[1]), .C(A[0])  , .D(EN) ); // 001
-    sky130_fd_sc_hd__and4bb_2   AND2 ( .X(SEL[2])  , .A_N(A[2]), .B_N(A[0]), .C(A[1])  , .D(EN) ); // 010
-    sky130_fd_sc_hd__and4b_2    AND3 ( .X(SEL[3])  , .A_N(A[2]), .B(A[1]), .C(A[0])  , .D(EN) );   // 011
-    sky130_fd_sc_hd__and4bb_2   AND4 ( .X(SEL[4])  , .A_N(A[0]), .B_N(A[1]), .C(A[2])  , .D(EN) ); // 100
-    sky130_fd_sc_hd__and4b_2    AND5 ( .X(SEL[5])  , .A_N(A[1]), .B(A[0]), .C(A[2])  , .D(EN) );   // 101
-    sky130_fd_sc_hd__and4b_2    AND6 ( .X(SEL[6])  , .A_N(A[0]), .B(A[1]), .C(A[2])  , .D(EN) );   // 110
-    sky130_fd_sc_hd__and4_2     AND7 ( .X(SEL[7])  , .A(A[0]), .B(A[1]), .C(A[2])  , .D(EN) ); // 111
-endmodule
-*/
-
-module DEC5x32 (
-    input   [4:0]   A,
-    output  [31:0]   SEL
-);
-	wire [3:0] EN;
-	DEC3x8 D0 ( .A(A[2:0]), .SEL(SEL[7:0]), .EN(EN[0]) );
-	DEC3x8 D1 ( .A(A[2:0]), .SEL(SEL[15:8]), .EN(EN[1]) );
-	DEC3x8 D2 ( .A(A[2:0]), .SEL(SEL[23:16]), .EN(EN[2]) );
-	DEC3x8 D3 ( .A(A[2:0]), .SEL(SEL[31:24]), .EN(EN[3]) );
-
-	DEC2x4 D ( .A(A[4:3]), .SEL(EN), .EN(1'b1) );
-endmodule

diff --git a/verilog/rtl/user_project/rtl/IPs/AHBSRAM.v b/verilog/rtl/user_project/rtl/IPs/AHBSRAM.v
deleted file mode 100644
index ed0c1c1..0000000
--- a/verilog/rtl/user_project/rtl/IPs/AHBSRAM.v
+++ /dev/null

@@ -1,334 +0,0 @@
-/*
-module AHBSRAM#( parameter AW = 14)( // Address width 
-     input           HCLK,      // system bus clock 
-     input           HRESETn,   // system bus reset 
-     input           HSEL,      // AHB peripheral select 
-     input           HREADY,    // AHB ready input 
-     input     [1:0] HTRANS,    // AHB transfer type 
-     input     [2:0] HSIZE,     // AHB hsize 
-     input           HWRITE,    // AHB hwrite 
-     input  [AW-1:0] HADDR,     // AHB address bus 
-     input    [31:0] HWDATA,    // AHB write data bus 
-     output          HREADYOUT, // AHB ready output to S->M mux 
-     output          HRESP,     // AHB response 
-     output   [31:0] HRDATA,    // AHB read data bus 
-      
-     input    [31:0] SRAMRDATA, // SRAM Read Data 
-     output [AW-3:0] SRAMADDR,  // SRAM address 
-     output    [3:0] SRAMWEN,   // SRAM write enable (active high) 
-     output   [31:0] SRAMWDATA, // SRAM write data 
-     output          SRAMCS     // SRAM Chip Select  (active high) 
-   ); 
-   reg  [(AW-3):0] buf_addr; // Write address buffer   
-   reg  [ 3:0]     buf_we;   // Write enable buffer (data phase)  
-   reg             buf_hit;  // High when AHB read address  
-                             // matches buffered address 
-   reg  [31:0]     buf_data; // AHB write bus buffered  
-   reg             buf_pend; // Buffer write data valid  
-   reg                       buf_data_en;//Data buffer write enable (data phase) 
-   wire  ahb_access   = HTRANS[1] & HSEL & HREADY; 
-   wire  ahb_write    = ahb_access &  HWRITE; 
-   wire  ahb_read     = ahb_access & (~HWRITE); 
-    
-   // Stored write data in pending state if new transfer is read 
-   //   buf_data_en indicate new write (data phase) 
-   //   ahb_read    indicate new read  (address phase) 
-   //   buf_pend    is registered version of buf_pend_nxt 
-   wire        buf_pend_nxt = (buf_pend | buf_data_en) & ahb_read; 
-   
-   // RAM write happens when  
-   // - write pending (buf_pend), or 
-   // - new AHB write seen (buf_data_en) at data phase, 
-   // - and not reading (address phase) 
-   wire        ram_write    = (buf_pend | buf_data_en)  & (~ahb_read); // ahb_write 
-   // RAM WE is the buffered WE 
-   assign      SRAMWEN  = {4{ram_write}} & buf_we[3:0]; 
-   // RAM address is the buffered address for RAM write otherwise HADDR 
-   assign      SRAMADDR = ahb_read ? HADDR[AW-1:2] : buf_addr; 
-   // RAM chip select during read or write 
-   assign      SRAMCS   = ahb_read | ram_write; 
-   // Byte lane decoder and next state logic 
-   wire       tx_byte    = (~HSIZE[1]) & (~HSIZE[0]); 
-   wire       tx_half    = (~HSIZE[1]) &  HSIZE[0]; 
-   wire       tx_word    =   HSIZE[1]; 
-   wire       byte_at_00 = tx_byte & (~HADDR[1]) & (~HADDR[0]); 
-   wire       byte_at_01 = tx_byte & (~HADDR[1]) &   HADDR[0]; 
-   wire       byte_at_10 = tx_byte &   HADDR[1]  & (~HADDR[0]); 
-   wire       byte_at_11 = tx_byte &   HADDR[1]  &   HADDR[0]; 
-   wire       half_at_00 = tx_half & (~HADDR[1]); 
-   wire       half_at_10 = tx_half &   HADDR[1]; 
-   wire       word_at_00 = tx_word; 
-   wire       byte_sel_0 = word_at_00 | half_at_00 | byte_at_00; 
-   wire       byte_sel_1 = word_at_00 | half_at_00 | byte_at_01; 
-   wire       byte_sel_2 = word_at_00 | half_at_10 | byte_at_10; 
-   wire       byte_sel_3 = word_at_00 | half_at_10 | byte_at_11; 
-  // Address phase byte lane strobe 
-   wire [3:0] buf_we_nxt ={byte_sel_3 & ahb_write, byte_sel_2 & ahb_write, 
-                           byte_sel_1 & ahb_write,byte_sel_0 & ahb_write};  
-   // buf_data_en is data phase write control 
-   always @(posedge HCLK or negedge HRESETn) 
-     if (~HRESETn) 
-       buf_data_en <= 1'b0; 
-     else   
-       buf_data_en <= ahb_write; 
- 
-   always @(posedge HCLK) 
-     if(buf_we[3] & buf_data_en) 
-       buf_data[31:24] <= HWDATA[31:24]; 
- 
-   always @(posedge HCLK) 
-     if(buf_we[2] & buf_data_en) 
-       buf_data[23:16] <= HWDATA[23:16]; 
-  
-   always @(posedge HCLK) 
-     if(buf_we[1] & buf_data_en) 
-       buf_data[15: 8] <= HWDATA[15: 8]; 
-       
-   always @(posedge HCLK) 
-     if(buf_we[0] & buf_data_en) 
-       buf_data[ 7: 0] <= HWDATA[ 7: 0]; 
- 
-   // buf_we keep the valid status of each byte (data phase) 
-   always @(posedge HCLK or negedge HRESETn) 
-     if (~HRESETn) 
-       buf_we <= 4'b0000; 
-     else if(ahb_write) 
-       buf_we <= buf_we_nxt; 
- 
-   always @(posedge HCLK or negedge HRESETn) 
-     begin 
-     if (~HRESETn) 
-       buf_addr <= {(AW-2){1'b0}}; 
-     else if (ahb_write) 
-         buf_addr <= HADDR[(AW-1):2]; 
-     end 
-   // Buf_hit detection logic 
-   wire  buf_hit_nxt = (HADDR[AW-1:2] == buf_addr[AW-3:0]); 
-   // ---------------------------------------------------------- 
-   // Read data merge : This is for the case when there is a AHB  
-   // write followed by AHB read to the same address. In this case 
-   // the data is merged from the buffer as the RAM write to that 
-   // address hasn't happened yet 
-   // ---------------------------------------------------------- 
-   wire [ 3:0] merge1  = {4{buf_hit}} & buf_we; // data phase, buf_we indicates data is valid 
-   assign HRDATA={merge1[3] ? buf_data[31:24] : SRAMRDATA[31:24], 
-                  merge1[2] ? buf_data[23:16] : SRAMRDATA[23:16], 
-                  merge1[1] ? buf_data[15: 8] : SRAMRDATA[15: 8], 
-                  merge1[0] ? buf_data[ 7: 0] : SRAMRDATA[ 7: 0]}; 
- 
-   // Synchronous state update 
-   always @(posedge HCLK or negedge HRESETn) 
-     if (~HRESETn) 
-       buf_hit <= 1'b0; 
-     else if(ahb_read) 
-       buf_hit <= buf_hit_nxt; 
- 
-   always @(posedge HCLK or negedge HRESETn) 
-     if (~HRESETn) 
-       buf_pend <= 1'b0; 
-     else 
-       buf_pend <= buf_pend_nxt; 
- 
-   // if there is an AHB write and valid data in the buffer, RAM write data 
-   // comes from the buffer. otherwise comes from the HWDATA 
-   assign SRAMWDATA = (buf_pend) ? buf_data : HWDATA[31:0]; 
-   assign HREADYOUT = 1'b1; 
-   assign HRESP     = 1'b0; 
-endmodule 
-*/
-module AHBSRAM #(
-// --------------------------------------------------------------------------
-// Parameter Declarations
-// --------------------------------------------------------------------------
-  parameter AW       = 14) // Address width
- (
-// --------------------------------------------------------------------------
-// Port Definitions
-// --------------------------------------------------------------------------
-  input  wire          HCLK,      // system bus clock
-  input  wire          HRESETn,   // system bus reset
-  input  wire          HSEL,      // AHB peripheral select
-  input  wire          HREADY,    // AHB ready input
-  input  wire    [1:0] HTRANS,    // AHB transfer type
-  input  wire    [2:0] HSIZE,     // AHB hsize
-  input  wire          HWRITE,    // AHB hwrite
-  input  wire [31:0] HADDR,     // AHB address bus
-  input  wire   [31:0] HWDATA,    // AHB write data bus
-  output wire          HREADYOUT, // AHB ready output to S->M mux
-  output wire   [1:0]       HRESP,     // AHB response
-  output wire   [31:0] HRDATA,    // AHB read data bus
-
-  input  wire   [31:0] SRAMRDATA, // SRAM Read Data
-  output wire    [3:0] SRAMWEN,   // SRAM write enable (active high)
-  output wire   [31:0] SRAMWDATA, // SRAM write data
-  output wire          SRAMCS0,
-  //output wire          SRAMCS1,
-  //output wire          SRAMCS2,
-  //output wire          SRAMCS3,
-  output wire [AW:0]   SRAMADDR  // SRAM address
-);   // SRAM Chip Select  (active high)
-
-   // ----------------------------------------------------------
-   // Internal state
-   // ----------------------------------------------------------
-   reg  [(AW-3 - 0):0]           buf_addr;        // Write address buffer
-   reg  [ 3:0]               buf_we;          // Write enable buffer (data phase)
-   reg                       buf_hit;         // High when AHB read address
-                                              // matches buffered address
-   reg  [31:0]               buf_data;        // AHB write bus buffered
-   reg                       buf_pend;        // Buffer write data valid
-   reg                       buf_data_en;     // Data buffer write enable (data phase)
-
-   // ----------------------------------------------------------
-   // Read/write control logic
-   // ----------------------------------------------------------
-
-   wire        ahb_access   = HTRANS[1] & HSEL & HREADY;
-   wire        ahb_write    = ahb_access &  HWRITE;
-   wire        ahb_read     = ahb_access & (~HWRITE);
-
-
-   // Stored write data in pending state if new transfer is read
-   //   buf_data_en indicate new write (data phase)
-   //   ahb_read    indicate new read  (address phase)
-   //   buf_pend    is registered version of buf_pend_nxt
-   wire        buf_pend_nxt = (buf_pend | buf_data_en) & ahb_read;
-
-   // RAM write happens when
-   // - write pending (buf_pend), or
-   // - new AHB write seen (buf_data_en) at data phase,
-   // - and not reading (address phase)
-   wire        ram_write    = (buf_pend | buf_data_en)  & (~ahb_read); // ahb_write
-
-   // RAM WE is the buffered WE
-   assign      SRAMWEN  = {4{ram_write}} & buf_we[3:0];
-
-   // RAM address is the buffered address for RAM write otherwise HADDR
-   assign      SRAMADDR = ahb_read ? HADDR[AW-1:2] : buf_addr;
-
-   // RAM chip select during read or write
-   wire SRAMCS_src; 
-   assign      SRAMCS_src   = ahb_read | ram_write;
-   assign SRAMCS0 = SRAMCS_src; // & (~HADDR[AW + 3]) & (~HADDR[AW + 2]);
-   //assign SRAMCS1 = SRAMCS_src & (~HADDR[AW + 3]) & (HADDR[AW + 2]);
-   //assign SRAMCS2 = SRAMCS_src & (HADDR[AW + 3]) & (~HADDR[AW + 2]);
-   //assign SRAMCS3 = SRAMCS_src & (HADDR[AW + 3]) & (HADDR[AW + 2]);
-   // ----------------------------------------------------------
-   // Byte lane decoder and next state logic
-   // ----------------------------------------------------------
-
-   wire       tx_byte    = (~HSIZE[1]) & (~HSIZE[0]);
-   wire       tx_half    = (~HSIZE[1]) &  HSIZE[0];
-   wire       tx_word    =   HSIZE[1];
-
-   wire       byte_at_00 = tx_byte & (~HADDR[1]) & (~HADDR[0]);
-   wire       byte_at_01 = tx_byte & (~HADDR[1]) &   HADDR[0];
-   wire       byte_at_10 = tx_byte &   HADDR[1]  & (~HADDR[0]);
-   wire       byte_at_11 = tx_byte &   HADDR[1]  &   HADDR[0];
-
-   wire       half_at_00 = tx_half & (~HADDR[1]);
-   wire       half_at_10 = tx_half &   HADDR[1];
-
-   wire       word_at_00 = tx_word;
-
-   wire       byte_sel_0 = word_at_00 | half_at_00 | byte_at_00;
-   wire       byte_sel_1 = word_at_00 | half_at_00 | byte_at_01;
-   wire       byte_sel_2 = word_at_00 | half_at_10 | byte_at_10;
-   wire       byte_sel_3 = word_at_00 | half_at_10 | byte_at_11;
-
-   // Address phase byte lane strobe
-   wire [3:0] buf_we_nxt = { byte_sel_3 & ahb_write,
-                             byte_sel_2 & ahb_write,
-                             byte_sel_1 & ahb_write,
-                             byte_sel_0 & ahb_write };
-
-   // ----------------------------------------------------------
-   // Write buffer
-   // ----------------------------------------------------------
-
-   // buf_data_en is data phase write control
-   always @(posedge HCLK or negedge HRESETn)
-     if (~HRESETn)
-       buf_data_en <= 1'b0;
-     else
-       buf_data_en <= ahb_write;
-
-   always @(posedge HCLK)
-     if(buf_we[3] & buf_data_en)
-       buf_data[31:24] <= HWDATA[31:24];
-
-   always @(posedge HCLK)
-     if(buf_we[2] & buf_data_en)
-       buf_data[23:16] <= HWDATA[23:16];
-
-   always @(posedge HCLK)
-     if(buf_we[1] & buf_data_en)
-       buf_data[15: 8] <= HWDATA[15: 8];
-
-   always @(posedge HCLK)
-     if(buf_we[0] & buf_data_en)
-       buf_data[ 7: 0] <= HWDATA[ 7: 0];
-
-   // buf_we keep the valid status of each byte (data phase)
-   always @(posedge HCLK or negedge HRESETn)
-     if (~HRESETn)
-       buf_we <= 4'b0000;
-     else if(ahb_write)
-       buf_we <= buf_we_nxt;
-
-   always @(posedge HCLK or negedge HRESETn)
-     begin
-     if (~HRESETn)
-       buf_addr <= {(AW-2){1'b0}};
-     else if (ahb_write)
-         buf_addr <= HADDR[(AW-1):2];
-     end
-   // ----------------------------------------------------------
-   // Buf_hit detection logic
-   // ----------------------------------------------------------
-
-   wire  buf_hit_nxt = (HADDR[AW-1:2] == buf_addr[AW-3 - 0:0]);
-
-   // ----------------------------------------------------------
-   // Read data merge : This is for the case when there is a AHB
-   // write followed by AHB read to the same address. In this case
-   // the data is merged from the buffer as the RAM write to that
-   // address hasn't happened yet
-   // ----------------------------------------------------------
-
-   wire [ 3:0] merge1  = {4{buf_hit}} & buf_we; // data phase, buf_we indicates data is valid
-
-   assign HRDATA =
-              { merge1[3] ? buf_data[31:24] : SRAMRDATA[31:24],
-                merge1[2] ? buf_data[23:16] : SRAMRDATA[23:16],
-                merge1[1] ? buf_data[15: 8] : SRAMRDATA[15: 8],
-                merge1[0] ? buf_data[ 7: 0] : SRAMRDATA[ 7: 0] };
-
-   // ----------------------------------------------------------
-   // Synchronous state update
-   // ----------------------------------------------------------
-
-   always @(posedge HCLK or negedge HRESETn)
-     if (~HRESETn)
-       buf_hit <= 1'b0;
-     else if(ahb_read)
-       buf_hit <= buf_hit_nxt;
-
-   always @(posedge HCLK or negedge HRESETn)
-     if (~HRESETn)
-       buf_pend <= 1'b0;
-     else
-       buf_pend <= buf_pend_nxt;
-
-   // if there is an AHB write and valid data in the buffer, RAM write data
-   // comes from the buffer. otherwise comes from the HWDATA
-   assign SRAMWDATA = (buf_pend) ? buf_data : HWDATA[31:0];
-
-   // ----------------------------------------------------------
-   // Assign outputs
-   // ----------------------------------------------------------
-   assign HREADYOUT = 1'b1;
-   assign HRESP     = 2'b0;
-
-
-endmodule

diff --git a/verilog/rtl/user_project/rtl/IPs/APB_I2C.v b/verilog/rtl/user_project/rtl/IPs/APB_I2C.v
deleted file mode 100644
index 1840960..0000000
--- a/verilog/rtl/user_project/rtl/IPs/APB_I2C.v
+++ /dev/null

@@ -1,86 +0,0 @@
-/*
-	Mohamed Shalan (mshalan@aucegypt.edu)
-*/
-/*
-	APB interface for the OC i2c master controller.
-	The registers:
-
-*/
-
-`timescale 1ns/1ps
-`default_nettype none
-
-module APB_I2C(
-    //APB Inputs
-    input wire PCLK,
-    input wire PRESETn,
-    input wire PWRITE,
-    input wire [31:0] PWDATA,
-    input wire [31:0] PADDR,
-    input wire PENABLE,
-    
-    input PSEL,
-    
-    //APB Outputs
-    output wire PREADY,
-    output wire [31:0] PRDATA,
-
-	output wire IRQ,
-
-    // i2c Ports
-    input 	wire scl_i,	    // SCL-line input
-	output 	wire scl_o,	    // SCL-line output (always 1'b0)
-	output 	wire scl_oen_o, // SCL-line output enable (active low)
-	input	wire sda_i,     // SDA-line input
-	output	wire sda_o,	    // SDA-line output (always 1'b0)
-	output	wire sda_oen_o // SDA-line output enable (active low)
-    
-);
-
-  assign PREADY = 1'b1; //always ready
-  
-  wire[7:0] io_do;
-  wire io_we = PENABLE & PWRITE & PREADY & PSEL;
-  wire io_re = PENABLE & ~PWRITE & PREADY & PSEL;
-
-  wire i2c_irq;
-
-  reg I2C_IM_REG;
-
-  assign IRQ = i2c_irq & I2C_IM_REG;
-
-  // IM Register -- Size: 1 -- Offset: 0x14
-  always @(posedge PCLK, negedge PRESETn)
-  begin
-    if(!PRESETn)
-    begin
-      I2C_IM_REG <= 1'b0;
-    end
-    else if(PENABLE & PWRITE & PREADY & PSEL & (PADDR[4:2] == 3'h7))
-      I2C_IM_REG <= PWDATA[0:0];
-  end
-
-
-  i2c_master i2c (
-    		.sys_clk(PCLK),
-    		.sys_rst(~PRESETn),
-    		//
-    		.io_a(PADDR[7:2]),
-		    .io_di(PWDATA[7:0]),
-			.io_do(io_do),
-			.io_re(io_re),
-			.io_we(io_we),
-			//
-			.i2c_irq(i2c_irq),
-			//
-			.scl_i(scl_i),	   // SCL-line input
-			.scl_o(scl_o),	   // SCL-line output (always 1'b0)
-			.scl_oen_o(scl_oen_o), // SCL-line output enable (active low)
-			.sda_i(sda_i),		// SDA-line input
-			.sda_o(sda_o),	   // SDA-line output (always 1'b0)
-			.sda_oen_o(sda_oen_o)  // SDA-line output enable (active low)
-	);
-  
-  assign PRDATA[31:0] = (PADDR[4:2] == 3'h7) ? I2C_IM_REG : io_do;//I2C_DATA_REG;
-  
-endmodule

diff --git a/verilog/rtl/user_project/rtl/IPs/APB_SPI.v b/verilog/rtl/user_project/rtl/IPs/APB_SPI.v
deleted file mode 100644
index 4e99d28..0000000
--- a/verilog/rtl/user_project/rtl/IPs/APB_SPI.v
+++ /dev/null

@@ -1,153 +0,0 @@
-/*
-	Mohamed Shalan (mshalan@aucegypt.edu)
-*/
-/*
-  Registers
-    cfg (W): 0:cpol, 1:cpha, 8-15: clock divider  [0x08]
-    ctrl (W): 0: go, 1:ssb    [0x04]
-    status (R): 0: done       [0x10]
-    datain (W): 0-7: data in  [0x00]
-    datao (R): 0-7: data out  [0x00]
-*/
-
-`timescale 1ns/1ps
-`default_nettype none
-
-module APB_SPI(
-
-    input wire PCLK,
-    input wire PRESETn,
-    input wire PWRITE,
-    input wire [31:0] PWDATA,
-    input wire [31:0] PADDR,
-    input wire PENABLE,
-
-    input PSEL,
-
-    output wire PREADY,
-    output wire [31:0] PRDATA,
-
-    input  wire MSI,
-    output wire MSO,
-    output wire SSn,
-    output wire SCLK,
-
-    output IRQ
-
-);
-
-  reg   [7:0]   SPI_DATAi_REG;
-  wire  [7:0]   SPI_DATAo_REG;
-
-  reg   [1:0]   SPI_CTRL_REG;
-  wire          SPI_STATUS_REG;
-  reg   [9:0]   SPI_CFG_REG;
-
-  reg   [0:0]   SPI_IM_REG;
-
-  wire go, cpol, cpha, done, busy, csb;
-  wire [7:0] datai, datao, clkdiv;
-
-  // The Control Register -- Size: 2 -- offset: 4
-  always @(posedge PCLK, negedge PRESETn)
-  begin
-    if(!PRESETn)
-    begin
-      SPI_CTRL_REG <= 2'b0;
-    end
-    else if(PENABLE & PWRITE & PREADY & PSEL & PADDR[2] & ~PADDR[3] & ~PADDR[4])
-      SPI_CTRL_REG <= PWDATA[1:0];
-  end
-
-  // Configuration Register -- Size; 10 -- Offset: 8
-  always @(posedge PCLK, negedge PRESETn)
-  begin
-    if(!PRESETn)
-    begin
-      SPI_CFG_REG <= 10'b0;
-    end
-    else if(PENABLE & PWRITE & PREADY & PSEL & PADDR[3] & ~PADDR[2] & ~PADDR[4])
-      SPI_CFG_REG <= PWDATA[9:0];
-  end
-
-  // Data Register -- Size: 8 -- Offset: 0
-  always @(posedge PCLK, negedge PRESETn)
-  begin
-    if(!PRESETn)
-    begin
-      SPI_DATAi_REG <= 8'b0;
-    end
-    else if(PENABLE & PWRITE & PREADY & PSEL & ~PADDR[2] & ~PADDR[3] & ~PADDR[4])
-      SPI_DATAi_REG <= PWDATA[7:0];
-  end
-
-
-  // IM Register -- Size: 1 -- Offset: 0x14
-  always @(posedge PCLK, negedge PRESETn)
-  begin
-    if(!PRESETn)
-    begin
-      SPI_IM_REG <= 1'b0;
-    end
-    else if(PENABLE & PWRITE & PREADY & PSEL & PADDR[2] & ~PADDR[3] & PADDR[4])
-      SPI_IM_REG <= PWDATA[0:0];
-  end
-
-  assign datai          = SPI_DATAi_REG[7:0];
-  assign go             = SPI_CTRL_REG[0];
-  assign SSn            = ~SPI_CTRL_REG[1];
-  assign cpol           = SPI_CFG_REG[0];
-  assign cpha           = SPI_CFG_REG[1];
-  assign clkdiv         = SPI_CFG_REG[9:2];
-
-  assign SPI_STATUS_REG = DONE;
-  assign SPI_DATAo_REG  = datao;
-  
-  reg DONE;
-
-  always @(posedge PCLK, negedge PRESETn)
-     begin
-       if(!PRESETn)
-       begin
-         DONE <= 1'b0;
-       end
-       else if(done)
-         DONE <= 1'b1;
-       else if(go)
-         DONE <= 1'b0;
-  end
-
-  spi_master
-    #(
-      .DATA_WIDTH(8),
-      .CLK_DIVIDER_WIDTH(8)
-      ) SPI_CTRL (
-         .clk(PCLK),
-         .resetb(PRESETn),
-         .CPOL(cpol),
-         .CPHA(cpha),
-         .clk_divider(clkdiv),
-
-         .go(go),
-         .datai(datai),
-         .datao(datao),
-         //.busy(busy),
-         .done(done),
-
-         .dout(MSI),
-         .din(MSO),
-         //.csb(ss),
-         .sclk(SCLK)
-  );
-
-  assign PRDATA[31:0] = (PADDR[2] & PADDR[4]) ? {31'd0, SPI_IM_REG} :
-                        (PADDR[2]) ? {30'd0,SPI_CTRL_REG} :
-                        (PADDR[3]) ? {{22'd0,SPI_CFG_REG}} :
-                        (PADDR[4]) ? {31'd0,SPI_STATUS_REG} :
-                        {24'd0,SPI_DATAo_REG};
-
-  assign PREADY = 1'b1;
-
-  assign IRQ = SPI_IM_REG[0] & DONE;
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/IPs/APB_UART.v b/verilog/rtl/user_project/rtl/IPs/APB_UART.v
deleted file mode 100644
index daddc6e..0000000
--- a/verilog/rtl/user_project/rtl/IPs/APB_UART.v
+++ /dev/null

@@ -1,724 +0,0 @@
-/*
-	Mohamed Shalan (mshalan@aucegypt.edu)
-*/
-/*
-  APB UART that supports 8N1 with the following features
-  - 16-byte TX and RX FIFOs with programmable thresholds
-  - 16-bit prescaler (PR) for programable baud rate generation
-    Baudrate = CLK/((PR+1)*16)
-  - Four Interrupt Sources:
-    + TX Fifo not full
-    + RX Fifo not empty
-    + RX Fifo level exceeded the threshold
-    + TX Fifo level is below the threshold
-
-  offset    I/O Register
-  ------    ------------
-  00        data in/out (RW)
-  04        status: 0:TX_Full, 1: TX_Empty, 2:RX_Full, 3:RX_Empty, 4:tx_less_threshold, 5:rx_more_threshold  (R)
-  04        control: 0: Enable UART 
-  08        PRESCALER (RW)
-  0C        IM: 0: All, 1:~TX_full, 2:~RX_Empty, 3:tx_less_threshold, 4: rx_more_threshold (RW)
-*/
-
-`timescale 1ns/1ps
-`default_nettype none
-
-// `define VERIFY
-
-`define   DATA_ADDR       8'h00
-`define   STATUS_ADDR     8'h04
-`define   CTRL_ADDR       8'h04
-`define   PRESCALE_ADDR   8'h08
-`define   IMASK_ADDR      8'h0c
-`define   TXFIFOTR_ADDR   8'h10
-`define   RXFIFOTR_ADDR   8'h14
-
-
-
-module APB_UART(
-    // APB Bus Interface
-    // APB Inputs
-    input wire        PCLK,
-    input wire        PRESETn,
-    input wire        PWRITE,
-    input wire [31:0] PWDATA,
-    input wire [31:0] PADDR,
-    input wire        PENABLE,
-    input wire        PSEL,
-    // APB Outputs
-    output wire       PREADY,
-    output wire [31:0]PRDATA,
-
-    // Serial Port
-    input wire        RsRx,  
-    output wire       RsTx,  
-
-    // UART Interrupt
-    output wire       uart_irq  //Interrupt
-);
-
-
-    // I/O Registers
-    reg [1:0] STATUS;
-    reg [15:0] PRESCALE;
-    reg [4:0] IMASK;
-    reg [0:0] CTRL;
-    reg [7:0] TXFIFOTR;
-    reg [7:0] RXFIFOTR;
-
-    //Internal Signals
-
-    //Data I/O between Bus and FIFO
-    wire [7:0] uart_wdata;  
-    wire [7:0] uart_rdata;
-
-    //Signals from TX/RX to FIFOs
-    wire uart_wr;
-    wire uart_rd;
-
-    //wires between FIFO and TX/RX
-    wire [7:0] tx_data;
-    wire [7:0] rx_data;
-
-    //FIFO Status
-    wire tx_full;
-    wire tx_empty;
-    wire rx_full;
-    wire rx_empty;
-
-    //UART status ticks
-    wire tx_done;
-    wire rx_done;
-
-    //baud rate signal
-    wire b_tick;
-  
-    // FIFO level
-    wire [7:0] tx_level;
-    wire [7:0] rx_level;
-
-
-    always @(posedge PCLK, negedge PRESETn)
-      if(!PRESETn) begin
-        IMASK <= 3'd0;
-        PRESCALE <= 16'd0;
-        CTRL <= 1'b0;
-      end
-      else if(PSEL & PWRITE & PENABLE) begin
-          if(PADDR[7:0] == `PRESCALE_ADDR) PRESCALE <= PWDATA[15:0];
-          else if(PADDR[7:0] == `IMASK_ADDR) IMASK <= PWDATA[4:0]; 
-          else if(PADDR[7:0] == `CTRL_ADDR) CTRL <= PWDATA[0:0]; 
-          else if(PADDR[7:0] == `TXFIFOTR_ADDR) TXFIFOTR <= PWDATA[7:0];
-          else if(PADDR[7:0] == `RXFIFOTR_ADDR) RXFIFOTR <= PWDATA[7:0];
-          //$display("write to %d data %d, %d", PADDR[3:0], PWDATA, CTRL);
-      end
-
-
-    //assign HREADYOUT = ~tx_full;
-    assign PREADY = 1; //~tx_full;
-    
-    //UART  write select
-    //assign uart_wr = last_HTRANS[1] & last_HWRITE & last_HSEL;
-    assign uart_wr = PSEL & PWRITE & PENABLE & (PADDR[7:0]==`DATA_ADDR);
-    
-    //Only write last 8 bits of Data
-    //assign uart_wdata = HWDATA[7:0];
-    assign uart_wdata = PWDATA;
-
-    //UART read select
-    //assign uart_rd = last_HTRANS[1] & ~last_HWRITE & last_HSEL;
-    //PENABLE & PWRITE & PREADY & PSEL & ~PADDR[2])
-    assign uart_rd = PSEL & ~PWRITE & PENABLE & (PADDR[7:0]==`DATA_ADDR);
-    
-    //Assign UART output to AHB RDATA
-    //assign HRDATA = {24'h0000_00,uart_rdata};
-    assign PRDATA = (PADDR[7:0] == `DATA_ADDR )     ?   {24'h0000_00,uart_rdata}     :
-                    (PADDR[7:0] == `STATUS_ADDR )   ?   {26'h0,rx_more_threshold, tx_less_threshold ,rx_empty, rx_full ,tx_empty, tx_full}  :
-                    (PADDR[7:0] == `PRESCALE_ADDR ) ?   {16'h0, PRESCALE}            :
-                    (PADDR[7:0] == `IMASK_ADDR )    ?   {29'h0,IMASK}                : 
-                    (PADDR[7:0] == `TXFIFOTR_ADDR ) ?   {24'h0,TXFIFOTR}             : 
-                    (PADDR[7:0] == `RXFIFOTR_ADDR ) ?   {24'h0,RXFIFOTR}             :
-                                                        32'hDEADDEAD;
-    
-    wire tx_less_threshold = (tx_level < TXFIFOTR);
-    wire rx_more_threshold = (rx_level > TXFIFOTR);
-    
-
-    assign uart_irq = IMASK[0] & (  (~rx_empty & IMASK[2])  | 
-                                    (~tx_full & IMASK[1])    | 
-                                    (tx_less_threshold & IMASK[3]) | 
-                                    (rx_more_threshold & IMASK[4])
-                                  ); 
-  
-  BAUDGEN uBAUDGEN(
-    .clk(PCLK),
-    .rst_n(PRESETn),
-	  .prescale(PRESCALE),
-    .en(CTRL[0]),
-    .baudtick(b_tick)
-  );
-  
-  FIFO uFIFO_TX 
-  (
-    .clk(PCLK),
-    .rst_n(PRESETn),
-    .rd(tx_done),
-    .wr(uart_wr),
-    .w_data(uart_wdata[7:0]),
-    .empty(tx_empty),
-    .full(tx_full),
-    .r_data(tx_data[7:0]),
-    .level(tx_level)
-  );
-  
-  FIFO uFIFO_RX(
-    .clk(PCLK),
-    .rst_n(PRESETn),
-    .rd(uart_rd),
-    .wr(rx_done),
-    .w_data(rx_data[7:0]),
-    .empty(rx_empty),
-    .full(rx_full),
-    .r_data(uart_rdata[7:0]),
-    .level(rx_level)
-  );
-  
-  UART_RX uUART_RX(
-    .clk(PCLK),
-    .resetn(PRESETn),
-    .b_tick(b_tick),
-    .rx(RsRx),
-    .rx_done(rx_done),
-    .dout(rx_data[7:0])
-  );
-  
-  UART_TX uUART_TX(
-    .clk(PCLK),
-    .resetn(PRESETn),
-    .tx_start(!tx_empty),
-    .b_tick(b_tick),
-    .d_in(tx_data[7:0]),
-    .tx_done(tx_done),
-    .tx(RsTx)
-  );
-  
-  
-endmodule
-
-
-module FIFO #(parameter DWIDTH=8, AWIDTH=4)
-(
-  input wire clk,
-  input wire rst_n,
-  input wire rd,
-  input wire wr,
-  input wire [DWIDTH-1:0] w_data,
-  output wire empty,
-  output wire full,
-  output wire [DWIDTH-1:0] r_data,
-  output wire [AWIDTH-1:0] level
-);
-
-//Internal Signal declarations
-
-  reg [DWIDTH-1:0] array_reg [2**AWIDTH-1:0];
-  reg [AWIDTH-1:0] w_ptr_reg;
-  reg [AWIDTH-1:0] w_ptr_next;
-  reg [AWIDTH-1:0] w_ptr_succ;
-  reg [AWIDTH-1:0] r_ptr_reg;
-  reg [AWIDTH-1:0] r_ptr_next;
-  reg [AWIDTH-1:0] r_ptr_succ;
-
-  // Level
-  reg [AWIDTH-1:0] level_reg;
-  reg [AWIDTH-1:0] level_next; 
-  
-  reg full_reg;
-  reg empty_reg;
-  reg full_next;
-  reg empty_next;
-  
-  wire w_en;
-  
-
-  always @ (posedge clk)
-    if(w_en)
-    begin
-      array_reg[w_ptr_reg] <= w_data;
-    end
-
-  assign r_data = array_reg[r_ptr_reg];   
-
-  assign w_en = wr & ~full_reg;           
-
-//State Machine
-  always @ (posedge clk, negedge rst_n)
-  begin
-    if(!rst_n)
-      begin
-        w_ptr_reg <= 0;
-        r_ptr_reg <= 0;
-        full_reg <= 1'b0;
-        empty_reg <= 1'b1;
-        level_reg <= 4'd0;
-      end
-    else
-      begin
-        w_ptr_reg <= w_ptr_next;
-        r_ptr_reg <= r_ptr_next;
-        full_reg <= full_next;
-        empty_reg <= empty_next;
-        level_reg <= level_next;
-      end
-  end
-
-
-//Next State Logic
-  always @*
-  begin
-    w_ptr_succ = w_ptr_reg + 1;
-    r_ptr_succ = r_ptr_reg + 1;
-    
-    w_ptr_next = w_ptr_reg;
-    r_ptr_next = r_ptr_reg;
-    full_next = full_reg;
-    empty_next = empty_reg;
-    level_next = level_reg;
-    
-    case({w_en,rd})
-      //2'b00: nop
-      2'b01:
-        if(~empty_reg)
-          begin
-            r_ptr_next = r_ptr_succ;
-            full_next = 1'b0;
-            level_next = level_reg - 1;
-            if (r_ptr_succ == w_ptr_reg)
-              empty_next = 1'b1;
-          end
-      2'b10:
-        if(~full_reg)
-          begin
-            w_ptr_next = w_ptr_succ;
-            empty_next = 1'b0;
-            level_next = level_reg + 1;
-            if (w_ptr_succ == r_ptr_reg)
-              full_next = 1'b1;
-          end
-      2'b11:
-        begin
-          w_ptr_next = w_ptr_succ;
-          r_ptr_next = r_ptr_succ;
-        end
-    endcase
-  end
-
-//Set Full and Empty
-
-  assign full = full_reg;
-  assign empty = empty_reg;
-
-  assign level = level_reg;
-  
-endmodule
-
-
-// Baudrate = Clk/((prescale+1)*16)
-// 19200 = 50,000,000 / ((prescale+1)*16)
-// prescale = 161.76 ==> 162
-module BAUDGEN
-(
-  input wire clk,
-  input wire rst_n,
-  input wire [15:0] prescale, 
-  input wire en,
-  output wire baudtick
-);
-
-reg [15:0] count_reg;
-wire [15:0] count_next;
-
-//Counter
-always @ (posedge clk, negedge rst_n)
-  begin
-    if(!rst_n)
-      count_reg <= 0;
-    else if(en)
-      count_reg <= count_next;
-end
-
-assign count_next = ((count_reg == prescale) ? 0 : count_reg + 1'b1);
-assign baudtick = ((count_reg == prescale) ? 1'b1 : 1'b0);
-
-endmodule
-
-
-module UART_RX(
-  input wire clk,
-  input wire resetn,
-  input wire b_tick,        //Baud generator tick
-  input wire rx,            //RS-232 data port
-  
-  output reg rx_done,       //transfer completed
-  output wire [7:0] dout    //output data
-);
-
-//STATE DEFINES  
-  localparam [1:0] idle_st = 2'b00;
-  localparam [1:0] start_st = 2'b01;
-  localparam [1:0] data_st = 2'b11;
-  localparam [1:0] stop_st = 2'b10;
-
-//Internal Signals  
-  reg [1:0] current_state;
-  reg [1:0] next_state;
-  reg [3:0] b_reg; //baud-rate/over sampling counter
-  reg [3:0] b_next;
-  reg [2:0] count_reg; //data-bit counter
-  reg [2:0] count_next;
-  reg [7:0] data_reg; //data register
-  reg [7:0] data_next;
-  
-//State Machine  
-  always @ (posedge clk, negedge resetn)
-  begin
-    if(!resetn)
-      begin
-        current_state <= idle_st;
-        b_reg <= 0;
-        count_reg <= 0;
-        data_reg <=0;
-      end
-    else
-      begin
-        current_state <= next_state;
-        b_reg <= b_next;
-        count_reg <= count_next;
-        data_reg <= data_next;
-      end
-  end
-
-//Next State Logic 
-  always @*
-  begin
-    next_state = current_state;
-    b_next = b_reg;
-    count_next = count_reg;
-    data_next = data_reg;
-    rx_done = 1'b0;
-        
-    case(current_state)
-      idle_st:
-        if(~rx)
-          begin
-            next_state = start_st;
-            b_next = 0;
-          end
-          
-      start_st:
-        if(b_tick)
-          if(b_reg == 7)
-            begin
-              next_state = data_st;
-              b_next = 0;
-              count_next = 0;
-            end
-          else
-            b_next = b_reg + 1'b1;
-            
-      data_st:
-        if(b_tick)
-          if(b_reg == 15)
-            begin
-              b_next = 0;
-              data_next = {rx, data_reg [7:1]};
-              if(count_next ==7) // 8 Data bits
-                next_state = stop_st;
-              else
-                count_next = count_reg + 1'b1;
-            end
-          else
-            b_next = b_reg + 1;
-            
-      stop_st:
-        if(b_tick)
-          if(b_reg == 15) //One stop bit
-            begin
-              next_state = idle_st;
-              rx_done = 1'b1;
-            end
-          else
-           b_next = b_reg + 1;
-    endcase
-  end
-  
-  assign dout = data_reg;
-  
-endmodule
-
-module UART_TX(
-  input wire clk,
-  input wire resetn,
-  input wire tx_start,        
-  input wire b_tick,          //baud rate tick
-  input wire [7:0] d_in,      //input data
-  output reg tx_done,         //transfer finished
-  output wire tx              //output data to RS-232
-  );
-  
-  
-//STATE DEFINES  
-  localparam [1:0] idle_st = 2'b00;
-  localparam [1:0] start_st = 2'b01;
-  localparam [1:0] data_st = 2'b11;
-  localparam [1:0] stop_st = 2'b10;
-  
-//Internal Signals  
-  reg [1:0] current_state;
-  reg [1:0] next_state;
-  reg [3:0] b_reg;          //baud tick counter
-  reg [3:0] b_next;
-  reg [2:0] count_reg;      //data bit counter
-  reg [2:0] count_next;
-  reg [7:0] data_reg;       //data register
-  reg [7:0] data_next;
-  reg tx_reg;               //output data reg
-  reg tx_next;
-  
-//State Machine  
-  always @(posedge clk, negedge resetn)
-  begin
-    if(!resetn)
-      begin
-        current_state <= idle_st;
-        b_reg <= 0;
-        count_reg <= 0;
-        data_reg <= 0;
-        tx_reg <= 1'b1;
-      end
-    else
-      begin
-        current_state <= next_state;
-        b_reg <= b_next;
-        count_reg <= count_next;
-        data_reg <= data_next;
-        tx_reg <= tx_next;
-      end
-  end
-
-
-//Next State Logic  
-  always @*
-  begin
-    next_state = current_state;
-    tx_done = 1'b0;
-    b_next = b_reg;
-    count_next = count_reg;
-    data_next = data_reg;
-    tx_next = tx_reg;
-    
-    case(current_state)
-      idle_st:
-      begin
-        tx_next = 1'b1;
-        if(tx_start)
-        begin
-          next_state = start_st;
-          b_next = 0;
-          data_next = d_in;
-        end
-      end
-      
-      start_st: //send start bit
-      begin
-        tx_next = 1'b0;
-        if(b_tick)
-          if(b_reg==15)
-            begin
-              next_state = data_st;
-              b_next = 0;
-              count_next = 0;
-            end
-          else
-            b_next = b_reg + 1;
-      end
-      
-      data_st: //send data serially
-      begin
-        tx_next = data_reg[0];
-        
-        if(b_tick)
-          if(b_reg == 15)
-            begin
-              b_next = 0;
-              data_next = data_reg >> 1;
-              if(count_reg == 7)    //8 data bits
-                next_state = stop_st;
-              else
-                count_next = count_reg + 1;
-            end
-          else
-            b_next = b_reg + 1;
-      end
-      
-      stop_st: //send stop bit
-      begin
-        tx_next = 1'b1;
-        if(b_tick)
-          if(b_reg == 15)   //one stop bit
-            begin
-              next_state = idle_st;
-              tx_done = 1'b1;
-            end
-          else
-            b_next = b_reg + 1;
-      end
-    endcase
-  end
-  
-  assign tx = tx_reg;
-  
-endmodule
-
-
-`ifdef VERIFY
-
-module uart_tb;
-
-reg PCLK;
-    reg  PRESETn;
-    reg  PWRITE;
-    reg  [31:0] PWDATA;
-    reg  [31:0] PADDR;
-    reg  PENABLE;
-    
-    reg PSEL;
-    
-    //APB Outputs
-     wire PREADY;
-     wire [31:0] PRDATA;
-
-
-  //Serial Port Signals
-   wire         RsRx;  //Input from RS-232
-   wire        RsTx;  //Output to RS-232
-
-  //UART Interrupt
-   wire uart_irq;  //Interrupt
-
-	 always #5 PCLK = !PCLK;
-
-    initial begin
-        $dumpfile("uart.vcd");
-        $dumpvars;
-        # 25000 $finish;
-    end
-
-    initial begin
-        PCLK = 0;
-        PRESETn = 1;
-		PSEL = 0;
-		#10;
-		@(posedge PCLK);
-		PRESETn = 0;
-		#100;
-		@(posedge PCLK);
-		PRESETn = 1;
-
-    // Configure the prescales
-    APB_WR(1, `PRESCALE_ADDR);
-    APB_WR(1, `CTRL_ADDR);
-    APB_WR(0, `IMASK_ADDR);
-    APB_WR(6, `TXFIFOTR_ADDR );
-    APB_WR(9, `IMASK_ADDR);
-    
-
-		// write something
-		APB_WR(8'h7F, 0);
-		APB_WR(8'h7F, 0);
-    APB_WR(8'h7F, 0);
-		APB_WR(8'h7F, 0);
-    APB_WR(8'h7F, 0);
-		APB_WR(8'h7F, 0);
-    APB_WR(8'h7F, 0);
-		APB_WR(8'h7F, 0);
-
-    // wait for the first character to be received
-    APB_RD(`STATUS_ADDR);
-    while (PRDATA!=2) begin
-      APB_RD(`STATUS_ADDR);
-    end  
-
-    // change the baud rate
-    APB_WR(0, `CTRL_ADDR);
-    APB_WR(4, `PRESCALE_ADDR);
-    APB_WR(1, `CTRL_ADDR);
-    
-
-		
-	end
-
-		task APB_WR (input [31:0] data, input [31:0] address);
-			begin
-				@(posedge PCLK);
-				PSEL = 1;
-				PWRITE = 1;
-				PWDATA = data;
-				PENABLE = 0;
-        PADDR = address;
-				@(posedge PCLK);
-        PENABLE = 1;
-				@(posedge PCLK);
-				PSEL = 0;
-				PWRITE = 0;
-				PENABLE = 0;
-			end
-		endtask
-		
-    task APB_RD(input [31:0] address);
-			begin
-				@(posedge PCLK);
-				PSEL = 1;
-				PWRITE = 0;
-				PENABLE = 0;
-        PADDR = address;
-				@(posedge PCLK);
-        PENABLE = 1;
-				@(posedge PCLK);
-				PSEL = 0;
-				PWRITE = 0;
-				PENABLE = 0;
-			end
-		endtask
-	
-
-	APBUART MUV (
-  
-    //APB Inputs
-    PCLK,
-    PRESETn,
-    PWRITE,
-    PWDATA,
-    PADDR,
-    PENABLE,
-    
-    PSEL,
-    
-    //APB Outputs
-    PREADY,
-    PRDATA,
-
-
-  //Serial Port Signals
-  RsRx,  //Input from RS-232
-  RsTx,  //Output to RS-232
-
-  //UART Interrupt
-  uart_irq  //Interrupt
-);
-
-assign RsRx = RsTx;
-
-endmodule
-`endif
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/IPs/DFFRAM.v b/verilog/rtl/user_project/rtl/IPs/DFFRAM.v
deleted file mode 100644
index 7a32654..0000000
--- a/verilog/rtl/user_project/rtl/IPs/DFFRAM.v
+++ /dev/null

@@ -1,123 +0,0 @@
-/*
-    A parameterized DFF based RAM for SKY130A
-    Use the COLS parameter to set the size
-    Valid sizes: 1 (default), 2 or 4
-*/
-/*
-    Author: Mohamed Shalan (mshalan@aucegypt.edu)
-*/
-
-`timescale 1ns / 1ps
-`default_nettype none
-/*
-module DFFRAM #( parameter COLS=4)
-(
-    CLK,
-    WE,
-    EN,
-    Di,
-    Do,
-    A
-);
-
-    input           CLK;
-    input   [3:0]   WE;
-    input           EN;
-    input   [31:0]  Di;
-    output  [31:0]  Do;
-    input   [7+$clog2(COLS):0]   A;
-
-    wire [31:0]     DOUT [COLS-1:0];
-    wire [31:0]     Do_pre;
-    wire [COLS-1:0] EN_lines;
-
-    generate
-        genvar i;
-        for (i=0; i<COLS; i=i+1) begin : COLUMN
-            DFFRAM_COL4 RAMCOLS (   .CLK(CLK), 
-                                    .WE(WE), 
-                                    .EN(EN_lines[i]), 
-                                    .Di(Di), 
-                                    .Do(DOUT[i]), 
-                                    .A(A[7:0]) 
-                                );    
-        end
-        if(COLS==4) begin
-            MUX4x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .A2(DOUT[2]), .A3(DOUT[3]), .S(A[9:8]), .X(Do_pre) );
-            DEC2x4 DEC ( .EN(EN), .A(A[9:8]), .SEL(EN_lines) );
-        end
-        else if(COLS==2) begin
-            MUX2x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .S(A[8]), .X(Do_pre) );
-            //sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) );
-            //sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) );
-            DEC1x2 DEC ( .EN(EN), .A(A[8]), .SEL(EN_lines[1:0]) );
-            
-        end
-        else begin
-            PASS MUX ( .A(DOUT[0]), .X(Do_pre) );
-            sky130_fd_sc_hd__clkbuf_4 ENBUF (.X(EN_lines[0]), .A(EN) );
-        end
-    endgenerate
-    
-    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
-
-endmodule
-
-*/
-
-module DFFRAM #( parameter COLS=4)
-(
-    CLK,
-    WE,
-    EN,
-    Di,
-    Do,
-    A
-);
-
-    input           CLK;
-    input   [3:0]   WE;
-    input           EN;
-    input   [31:0]  Di;
-    output  [31:0]  Do;
-    input   [7+$clog2(COLS):0]   A;
-
-    wire [31:0]     DOUT [COLS-1:0];
-    wire [31:0]     Do_pre;
-    wire [COLS-1:0] EN_lines;
-
-    wire [9:8]      A_buf;
-
-    generate
-        genvar i;
-        for (i=0; i<COLS; i=i+1) begin : COLUMN
-            DFFRAM_COL4 RAMCOLS (   .CLK(CLK), 
-                                    .WE(WE), 
-                                    .EN(EN_lines[i]), 
-                                    .Di(Di), 
-                                    .Do(DOUT[i]), 
-                                    .A(A[7:0]) 
-                                );    
-        end
-        if(COLS==4) begin
-            sky130_fd_sc_hd__clkbuf_8 ABUF[1:0] (.X(A_buf[9:8]), .A(A[9:8]) );
-            MUX4x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .A2(DOUT[2]), .A3(DOUT[3]), .S(A_buf[9:8]), .X(Do_pre) );
-            DEC2x4 DEC ( .EN(EN), .A(A[9:8]), .SEL(EN_lines) );
-        end
-        else if(COLS==2) begin
-            sky130_fd_sc_hd__clkbuf_8 ABUF[8:8] (.X(A_buf[8]), .A(A[8]) );
-            MUX2x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .S(A_buf[8]), .X(Do_pre) );
-            //sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) );
-            //sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) );
-            DEC1x2 DEC ( .EN(EN), .A(A[8]), .SEL(EN_lines[1:0]) );
-            
-        end
-        else begin
-            PASS MUX ( .A(DOUT[0]), .X(Do_pre) );
-            sky130_fd_sc_hd__clkbuf_4 ENBUF (.X(EN_lines[0]), .A(EN) );
-        end
-    endgenerate
-    
-    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
-
-endmodule

diff --git a/verilog/rtl/user_project/rtl/IPs/DFFRAMBB.v b/verilog/rtl/user_project/rtl/IPs/DFFRAMBB.v
deleted file mode 100644
index 2825426..0000000
--- a/verilog/rtl/user_project/rtl/IPs/DFFRAMBB.v
+++ /dev/null

@@ -1,320 +0,0 @@
-/*
-    Building blocks for DFF based RAM compiler for SKY130A 
-    BYTE        :   8 memory cells used as a building block for WORD module
-    WORD        :   32-bit memory word with select and byte-level WE
-    DEC6x64     :   2x4 Binary Decoder
-    DEC6x64     :   6x64 Binary decoder
-    MUX4x1_32   :   32-bit 4x1 MUX
-    MUX2x1_32   :   32-bit 2x1 MUX
-    SRAM64x32   :   Tri-state buffers based 64x32 DFF RAM 
-    DFFRAM_COL4 :   A single column of 4 SRAM64x32 blocks using 4x1 multiplexors
-*/
-/*
-    Author: Mohamed Shalan (mshalan@aucegypt.edu)
-*/
-
-module BYTE (
-    input CLK,
-    input WE,
-    input SEL,
-    input [7:0] Di,
-    output [7:0] Do
-);
-
-    wire [7:0]  q_wire;
-    wire        we_wire;
-    wire        SEL_B;
-    wire        GCLK;
-
-    sky130_fd_sc_hd__inv_1 INV(.Y(SEL_B), .A(SEL));
-    sky130_fd_sc_hd__and2_1 CGAND( .A(SEL), .B(WE), .X(we_wire) );
-    sky130_fd_sc_hd__dlclkp_1 CG( .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) );
-
-    generate 
-        genvar i;
-        for(i=0; i<8; i=i+1) begin : BIT
-            sky130_fd_sc_hd__dfxtp_1 FF ( .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) );
-            sky130_fd_sc_hd__ebufn_2 OBUF ( .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) );
-        end
-    endgenerate 
-
-endmodule
-
-
-module WORD32 (
-    input CLK,
-    input [3:0] WE,
-    input SEL,
-    input [31:0] Di,
-    output [31:0] Do
-);
-
-    BYTE B0 ( .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
-    BYTE B1 ( .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
-    BYTE B2 ( .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
-    BYTE B3 ( .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
-    
-endmodule 
-
-module DEC1x2 (
-    input           EN,
-    input   [0:0]   A,
-    output  [1:0]   SEL
-);
-    sky130_fd_sc_hd__and2b_2    AND1 ( .X(SEL[0]), .A_N(A), .B(EN) );
-    sky130_fd_sc_hd__and2_2     AND3 ( .X(SEL[1]), .A(A), .B(A[0]) );
-    
-endmodule
-
-module DEC2x4 (
-`ifdef USE_POWER_PINS
-    input VPWR,
-    input VGND,
-`endif
-    input           EN,
-    input   [1:0]   A,
-    output  [3:0]   SEL
-);
-    sky130_fd_sc_hd__nor3b_4    AND0 ( 
-    `ifdef USE_POWER_PINS
-        .VPWR(VPWR),
-        .VGND(VGND),
-        .VPB(VPWR),
-        .VNB(VGND),
-    `endif
-        .Y(SEL[0]), .A(A[0]),   .B(A[1]), .C_N(EN) );
-    sky130_fd_sc_hd__and3b_4    AND1 ( 
-    `ifdef USE_POWER_PINS
-        .VPWR(VPWR),
-        .VGND(VGND),
-        .VPB(VPWR),
-        .VNB(VGND),
-    `endif
-        .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) );
-    sky130_fd_sc_hd__and3b_4    AND2 ( 
-    `ifdef USE_POWER_PINS
-        .VPWR(VPWR),
-        .VGND(VGND),
-        .VPB(VPWR),
-        .VNB(VGND),
-    `endif
-        .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) );
-    sky130_fd_sc_hd__and3_4     AND3 ( 
-    `ifdef USE_POWER_PINS
-        .VPWR(VPWR),
-        .VGND(VGND),
-        .VPB(VPWR),
-        .VNB(VGND),
-    `endif
-        .X(SEL[3]), .A(A[1]),   .B(A[0]), .C(EN) );
-    
-endmodule
-
-module DEC3x8 (
-    input           EN,
-    input [2:0]     A,
-    output [7:0]    SEL
-);
-    sky130_fd_sc_hd__nor4b_2   AND0 ( .Y(SEL[0])  , .A(A[0]), .B(A[1])  , .C(A[2]), .D_N(EN) ); // 000
-    sky130_fd_sc_hd__and4bb_2   AND1 ( .X(SEL[1])  , .A_N(A[2]), .B_N(A[1]), .C(A[0])  , .D(EN) ); // 001
-    sky130_fd_sc_hd__and4bb_2   AND2 ( .X(SEL[2])  , .A_N(A[2]), .B_N(A[0]), .C(A[1])  , .D(EN) ); // 010
-    sky130_fd_sc_hd__and4b_2    AND3 ( .X(SEL[3])  , .A_N(A[2]), .B(A[1]), .C(A[0])  , .D(EN) );   // 011
-    sky130_fd_sc_hd__and4bb_2   AND4 ( .X(SEL[4])  , .A_N(A[0]), .B_N(A[1]), .C(A[2])  , .D(EN) ); // 100
-    sky130_fd_sc_hd__and4b_2    AND5 ( .X(SEL[5])  , .A_N(A[1]), .B(A[0]), .C(A[2])  , .D(EN) );   // 101
-    sky130_fd_sc_hd__and4b_2    AND6 ( .X(SEL[6])  , .A_N(A[0]), .B(A[1]), .C(A[2])  , .D(EN) );   // 110
-    sky130_fd_sc_hd__and4_2     AND7 ( .X(SEL[7])  , .A(A[0]), .B(A[1]), .C(A[2])  , .D(EN) ); // 111
-endmodule
-
-
-module DEC6x64 (
-    input           EN,
-    input   [5:0]   A,
-    output  [63:0] SEL
-);
-    wire [7:0] SEL0_w ;
-    wire [2:0] A_buf;
-    
-    DEC3x8 DEC_L0 ( .EN(EN), .A(A[5:3]), .SEL(SEL0_w) );
-
-    sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (.X(A_buf), .A(A[2:0]));
-
-    generate
-        genvar i;
-        for(i=0; i<8; i=i+1) begin : DEC_L1
-            DEC3x8 U ( .EN(SEL0_w[i]), .A(A_buf), .SEL(SEL[7+8*i: 8*i]) );
-        end
-    endgenerate
-endmodule
-
-module MUX2x1_32(
-    input   [31:0]      A0, A1,
-    input   [0:0]       S,
-    output  [31:0]      X
-);
-    sky130_fd_sc_hd__mux2_1 MUX[31:0] (.A0(A0), .A1(A1), .S(S[0]), .X(X) );
-endmodule
-
-module MUX4x1_32(
-`ifdef USE_POWER_PINS
-    input VPWR,
-    input VGND,
-`endif
-    input   [31:0]      A0, A1, A2, A3,
-    input   [1:0]       S,
-    output  [31:0]      X
-);
-    sky130_fd_sc_hd__mux4_1 MUX[31:0] (
-    `ifdef USE_POWER_PINS
-        .VPWR(VPWR),
-        .VGND(VGND),
-        .VPB(VPWR),
-        .VNB(VGND),
-    `endif
-        .A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) );
-endmodule
-
-module PASS (input [31:0] A, output [31:0] X);
-    assign X = A;
-endmodule
-
-module SRAM64x32(
-    input CLK,
-    input [3:0] WE,
-    input EN,
-    input [31:0] Di,
-    output [31:0] Do,
-    input [5:0] A
-);
-
-    wire [63:0]     SEL;
-    wire [31:0]     Do_pre;
-    wire [31:0]     Di_buf;
-    wire            CLK_buf;
-    wire [3:0]      WE_buf;
-
-    sky130_fd_sc_hd__clkbuf_16 CLKBUF (.X(CLK_buf), .A(CLK));
-    sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] (.X(WE_buf), .A(WE));
-    sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] (.X(Di_buf), .A(Di));
-
-    DEC6x64 DEC  ( .EN(EN), .A(A), .SEL(SEL) );
-
-    generate
-        genvar i;
-        for (i=0; i< 64; i=i+1) begin : WORD
-            WORD32 W ( .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di_buf), .Do(Do_pre) );
-        end
-    endgenerate
-
-    // Ensure that the Do_pre lines are not floating when EN = 0
-    wire lo;
-    wire float_buf_en;
-    sky130_fd_sc_hd__clkbuf_4 FBUFENBUF( .X(float_buf_en), .A(EN) );
-    sky130_fd_sc_hd__conb_1 TIE (.LO(lo), .HI());
-    sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] ( .A( lo ), .Z(Do_pre), .TE_B(float_buf_en) );
-
-    generate 
-        //genvar i;
-        for(i=0; i<32; i=i+1) begin : OUT
-            sky130_fd_sc_hd__dfxtp_1 FF ( .D(Do_pre[i]), .Q(Do[i]), .CLK(CLK) );
-        end
-    endgenerate 
-
-endmodule
-
-/*
-module DFFRAM_COL4 
-(
-    CLK,
-    WE,
-    EN,
-    Di,
-    Do,
-    A
-);
-
-    input           CLK;
-    input   [3:0]   WE;
-    input           EN;
-    input   [31:0]  Di;
-    output  [31:0]  Do;
-    input   [7:0]   A;
-
-    
-    wire [31:0]     Di_buf;
-    wire [31:0]     Do_pre;
-    wire            CLK_buf;
-    wire [3:0]      WE_buf;
-    wire [5:3]      A_buf;
-
-    wire [31:0]     Do_B_0_0;
-    wire [31:0]     Do_B_0_1;
-    wire [31:0]     Do_B_0_2;
-    wire [31:0]     Do_B_0_3;
-
-    wire [3:0]      row_sel;
-
-    sky130_fd_sc_hd__clkbuf_8 CLKBUF (.X(CLK_buf), .A(CLK));
-    sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] (.X(WE_buf), .A(WE));
-    sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] (.X(Di_buf), .A(Di));
-
-    sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] ( .X(A_buf), .A(A[5:3]) );
-    
-    DEC2x4 DEC ( .EN(EN), .A(A[7:6]), .SEL(row_sel) );
-
-    SRAM64x32 B_0_0 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A({A_buf,A[2:0]}) );
-    SRAM64x32 B_0_1 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A({A_buf,A[2:0]}) );
-    SRAM64x32 B_0_2 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A({A_buf,A[2:0]}) );
-    SRAM64x32 B_0_3 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A({A_buf,A[2:0]}) );
-
-    MUX4x1_32 MUX ( .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A[7:6]), .X(Do) );
-
-endmodule
-*/
-module DFFRAM_COL4 
-(
-    CLK,
-    WE,
-    EN,
-    Di,
-    Do,
-    A
-);
-
-    input           CLK;
-    input   [3:0]   WE;
-    input           EN;
-    input   [31:0]  Di;
-    output  [31:0]  Do;
-    input   [7:0]   A;
-
-    
-    wire [31:0]     Di_buf;
-    wire [31:0]     Do_pre;
-    wire            CLK_buf;
-    wire [3:0]      WE_buf;
-    wire [7:0]      A_buf;
-
-    wire [31:0]     Do_B_0_0;
-    wire [31:0]     Do_B_0_1;
-    wire [31:0]     Do_B_0_2;
-    wire [31:0]     Do_B_0_3;
-
-    wire [3:0]      row_sel;
-
-    sky130_fd_sc_hd__clkbuf_8 CLKBUF (.X(CLK_buf), .A(CLK));
-    sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] (.X(WE_buf), .A(WE));
-    sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] (.X(Di_buf), .A(Di));
-
-    sky130_fd_sc_hd__clkbuf_8 ABUF[7:0] ( .X(A_buf), .A(A[7:0]) );
-  
-    DEC2x4 DEC ( .EN(EN), .A(A[7:6]), .SEL(row_sel) );
-
-    SRAM64x32 B_0_0 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A(A_buf[5:0]) );
-    SRAM64x32 B_0_1 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A(A_buf[5:0]) );
-    SRAM64x32 B_0_2 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A(A_buf[5:0]) );
-    SRAM64x32 B_0_3 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A(A_buf[5:0]) );
-
-    MUX4x1_32 MUX ( .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A_buf[7:6]), .X(Do) );
-
-endmodule
-

diff --git a/verilog/rtl/user_project/rtl/IPs/DMC_32x16HC.v b/verilog/rtl/user_project/rtl/IPs/DMC_32x16HC.v
deleted file mode 100644
index fa05012..0000000
--- a/verilog/rtl/user_project/rtl/IPs/DMC_32x16HC.v
+++ /dev/null

@@ -1,224 +0,0 @@
-`timescale 1ns / 1ps
-`default_nettype none
-
-//`define     STANDALONE
-/*
-    Hand-crafted 32 lines x 16 bytes Direct Mapped Cache
-    It can operate @ 200MHz clock!
-    Number of instances: 10654
-    ICG cells are used to reduce dynamic power consumption
-    A custom clock tree is embedded
-*/
-
-module HWORD (
-    input CLK,
-    input WE,
-    input SELW,
-    input SELR,
-    input [15:0] Di,
-    output [15:0] Do
-);
-
-    wire [15:0]  q_wire;
-    wire        we_wire;
-    wire        SEL_B;
-    wire        GCLK;
-
-    sky130_fd_sc_hd__inv_2 INV(.Y(SEL_B), .A(SELR));
-    sky130_fd_sc_hd__and2_1 CGAND( .A(SELW), .B(WE), .X(we_wire) );
-    sky130_fd_sc_hd__dlclkp_1 CG( .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) );
-
-    generate 
-        genvar i;
-        for(i=0; i<16; i=i+1) begin : BIT
-            sky130_fd_sc_hd__dfxtp_1 FF ( .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) );
-            sky130_fd_sc_hd__ebufn_2 OBUF ( .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) );
-        end
-    endgenerate 
-
-endmodule
-
-
-module LINE16 (
-    input CLK,
-    input WE,
-    input SELW,
-    input SELR,
-    input [127:0] Di,
-    output [127:0] Do
-);
-
-    wire [7:0] CLK_buf;
-
-    wire SELW_buf, SELR_buf;
-
-    sky130_fd_sc_hd__clkbuf_4 CLKBUF[7:0] ( .X(CLK_buf), .A(CLK) );
-
-    sky130_fd_sc_hd__clkbuf_4 SELWBUF( .X(SELW_buf), .A(SELW) );
-    sky130_fd_sc_hd__clkbuf_4 SELRBUF ( .X(SELR_buf), .A(SELR) );
-
-    
-    generate 
-        genvar i;
-        for(i=0; i<8; i=i+1)
-            HWORD HW ( .CLK(CLK_buf[i]), .WE(WE), .SELW(SELW_buf), .SELR(SELR_buf), .Di(Di[i*16+15:i*16]), .Do(Do[i*16+15:i*16]) );
-    endgenerate
-
-endmodule 
-
-module DEC2x4_DMC (
-    input   [1:0]   A,
-    output  [3:0]   SEL
-);
-    sky130_fd_sc_hd__nor2_2    AND0 ( .Y(SEL[0]), .A(A[0]),   .B(A[1]) );
-    sky130_fd_sc_hd__and2b_2    AND1 ( .X(SEL[1]), .A_N(A[1]), .B(A[0]) );
-    sky130_fd_sc_hd__and2b_2    AND2 ( .X(SEL[2]), .A_N(A[0]), .B(A[1]) );
-    sky130_fd_sc_hd__and2_2     AND3 ( .X(SEL[3]), .A(A[1]),   .B(A[0]) );
-    
-endmodule
-
-module DEC3x8_DMC (
-    input           EN,
-    input [2:0]     A,
-    output [7:0]    SEL
-);
-
-    wire [2:0] A_buf;
-    sky130_fd_sc_hd__clkbuf_2 ABUF[2:0] (.X(A_buf), .A(A));
-    sky130_fd_sc_hd__nor4b_4   AND0 ( .Y(SEL[0])  , .A(A_buf[0]), .B(A_buf[1]), .C(A_buf[2]), .D_N(EN) ); // 000
-    sky130_fd_sc_hd__and4bb_4   AND1 ( .X(SEL[1])  , .A_N(A_buf[2]), .B_N(A_buf[1]), .C(A_buf[0])  , .D(EN) ); // 001
-    sky130_fd_sc_hd__and4bb_4   AND2 ( .X(SEL[2])  , .A_N(A_buf[2]), .B_N(A_buf[0]), .C(A_buf[1])  , .D(EN) ); // 010
-    sky130_fd_sc_hd__and4b_4    AND3 ( .X(SEL[3])  , .A_N(A_buf[2]), .B(A_buf[1]), .C(A_buf[0])  , .D(EN) );   // 011
-    sky130_fd_sc_hd__and4bb_4   AND4 ( .X(SEL[4])  , .A_N(A_buf[0]), .B_N(A_buf[1]), .C(A_buf[2])  , .D(EN) ); // 100
-    sky130_fd_sc_hd__and4b_4    AND5 ( .X(SEL[5])  , .A_N(A_buf[1]), .B(A_buf[0]), .C(A_buf[2])  , .D(EN) );   // 101
-    sky130_fd_sc_hd__and4b_4    AND6 ( .X(SEL[6])  , .A_N(A_buf[0]), .B(A_buf[1]), .C(A_buf[2])  , .D(EN) );   // 110
-    sky130_fd_sc_hd__and4_4     AND7 ( .X(SEL[7])  , .A(A_buf[0]), .B(A_buf[1]), .C(A_buf[2])  , .D(EN) ); // 111
-endmodule
-
-module DEC5x32_DMC (
-    input   [4:0]   A,
-    output  [31:0]   SEL
-);
-    wire [3:0] en;
-    DEC2x4_DMC DEC0 ( .A(A[4:3]), .SEL(en) );
-
-    generate 
-        genvar i;
-        for(i=0; i<4; i=i+1)
-            DEC3x8_DMC DEC1 ( .A(A[2:0]), .EN(en[i]), .SEL(SEL[i*8+7:i*8]) );
-
-    endgenerate
-
-endmodule
-
-`ifdef STANDALONE
-module MUX4x1_32(
-    input   [31:0]      A0, A1, A2, A3,
-    input   [1:0]       S,
-    output  [31:0]      X
-);
-    sky130_fd_sc_hd__mux4_1 MUX[31:0] (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) );
-endmodule
-`endif
-
-module OVERHEAD(
-    input CLK,
-    input RSTn,
-    input SELR, SELW,
-    input VDi,
-    output VDo,
-    input[14:0] TDi,
-    output [14:0] TDo,
-    input WE
-);
-
-    wire SEL_B;
-    wire GCLK;
-    wire we_wire;
-    wire[15:0] q_wire;
-    
-    sky130_fd_sc_hd__inv_8 INV(.Y(SEL_B), .A(SELR));
-    sky130_fd_sc_hd__and2_4 CGAND( .A(SELW), .B(WE), .X(we_wire) );
-    sky130_fd_sc_hd__dlclkp_1 CG( .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) );
-
-    // Valid Bit
-    sky130_fd_sc_hd__dfrtp_1 V( .Q(q_wire[15]), .CLK(GCLK), .D(VDi), .RESET_B(RSTn) );
-    sky130_fd_sc_hd__ebufn_2 VOBUF ( .A(q_wire[15]), .Z(VDo), .TE_B(SEL_B) );
-
-    // 15-bit TAG
-    generate 
-        genvar i;
-        for(i=0; i<15; i=i+1) begin : VALID
-            sky130_fd_sc_hd__dfxtp_1 FF ( .D(TDi[i]), .Q(q_wire[i]), .CLK(GCLK) );
-            sky130_fd_sc_hd__ebufn_2 TOBUF ( .A(q_wire[i]), .Z(TDo[i]), .TE_B(SEL_B) );
-        end
-    endgenerate 
-
-endmodule
-
-module DMC_32x16HC (
-    input wire          clk,
-    input wire          rst_n,
-    // 
-    input wire  [23:0]  A,
-    input wire  [23:0]  A_h,
-    output wire [31:0]  Do,
-    output wire         hit,
-    //
-    input wire [127:0]  line,
-    input wire          wr
-);
-
-    wire [127:0] data;
-    wire [3:0]  offset  = A[3:0];
-    wire [4:0]  index   = A[8:4];
-    wire [14:0] tag     = A[23:9];
-
-    wire [4:0]  index_h   = A_h[8:4];
-    wire [14:0] tag_h     = A_h[23:9];
-
-    wire c_valid;
-    wire[14:0] c_tag;
-
-    wire [31:0] SELH, SEL;
-
-    wire [31:0] Do_pre;
-
-    wire CLK_buf;
-
-    wire hi;
-
-    DEC5x32_DMC DECH ( .A(index_h), .SEL(SELH) );
-    DEC5x32_DMC DEC ( .A(index), .SEL(SEL) );
-
-    sky130_fd_sc_hd__conb_1 TIE (.LO(), .HI(hi));
-    sky130_fd_sc_hd__clkbuf_16 CLKBUF (.X(CLK_buf), .A(clk));
-
-    OVERHEAD OVHB [31:0] (
-        .CLK(clk),
-        .RSTn(rst_n),
-        .SELR(SELH), 
-        .SELW(SEL),
-        .VDi(hi),
-        .VDo(c_valid),
-        .TDi(tag),
-        .TDo(c_tag),
-        .WE(wr)
-    );
-
-    LINE16 DATA [31:0] (
-        .CLK(clk),
-        .WE(wr),
-        .SELR(SEL), 
-        .SELW(SEL),
-        .Di(line),
-        .Do(data)
-    );
-
-    assign  hit =   c_valid & (c_tag == tag_h);
-
-    MUX4x1_32 MUX ( .A0(data[31:0]), .A1(data[63:32]), .A2(data[95:64] ), .A3(data[127:96]), .S(offset[3:2]), .X(Do_pre) );
-
-    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
-
-endmodule

diff --git a/verilog/rtl/user_project/rtl/IPs/GPIO.v b/verilog/rtl/user_project/rtl/IPs/GPIO.v
deleted file mode 100644
index 8f8f978..0000000
--- a/verilog/rtl/user_project/rtl/IPs/GPIO.v
+++ /dev/null

@@ -1,24 +0,0 @@
-
-`timescale 1ns/1ps
-`default_nettype none
-
-module GPIO (
-		// Wrapper ports
-		output 	wire [15:0] WGPIODIN,
-        input 	wire [15:0] WGPIODOUT,
-        input 	wire [15:0] WGPIOPU,
-        input 	wire [15:0] WGPIOPD,
-        input 	wire [15:0] WGPIODIR,		
-		// Externals
-        input 	wire [15:0] GPIOIN,
-        output 	wire [15:0] GPIOOUT,
-        output 	wire [15:0] GPIOPU,
-        output 	wire [15:0] GPIOPD,
-        output 	wire [15:0] GPIOOEN		
-);
-		assign GPIOOEN 	= WGPIODIR;
-		assign GPIOPU 	= WGPIOPU;
-		assign GPIOPD 	= WGPIOPD;
-		assign GPIOOUT	= WGPIODOUT;
-		assign WGPIODIN = GPIOIN;
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/IPs/PWM32.v b/verilog/rtl/user_project/rtl/IPs/PWM32.v
deleted file mode 100644
index 014305b..0000000
--- a/verilog/rtl/user_project/rtl/IPs/PWM32.v
+++ /dev/null

@@ -1,67 +0,0 @@
-/*
-	Mohamed Shalan (mshalan@aucegypt.edu)
-*/
-
-/*
-	A simple 32-bit PWM generator
-	PRE: clock prescalar (tmer_clk = clk / (PRE+1))
-	TMRCMP1: Timer CMP register (period)
-	TMRCMP2: PWN level change Comparator
-
-	PWM period = (TMRCMP1 + 1)/timer_clk = (TMRCMP1 + 1)*(PRE + 1)/clk
-	PWM off cyle % = (TMRCMP1 + 1)/(TMRCMP2 + 1)
-*/
-
-`timescale 1ns/1ps
-`default_nettype none
-
-module PWM32 (
-		input wire clk,
-		input wire rst,
-		input wire [31:0] PRE,
-		input wire [31:0] TMRCMP1,
-		input wire [31:0] TMRCMP2,
-		input wire 				TMREN,
-		output reg pwm
-	);
-
-	reg [31:0]	TMR;
-	reg [31:0] 	clkdiv;
-	wire 		timer_clk = (clkdiv==PRE) ;
-	wire 		tmrov = (TMR == TMRCMP1);
-	wire 		pwmov = (TMR == TMRCMP2);
-
-	// Prescalar
-	always @(posedge clk or posedge rst)
-	begin
-		if(rst)
-			clkdiv <= 32'd0;
-		else if(timer_clk)
-			clkdiv <= 32'd0;
-		else if(TMREN)
-			clkdiv <= clkdiv + 32'd1;
-	end
-
-	// Timer
-	always @(posedge clk or posedge rst)
-	begin
-		if(rst)
-			TMR <= 32'd0;
-		else if(tmrov)
-			TMR <= 32'd0;
-		else if(timer_clk)
-			TMR <= TMR + 32'd1;
-	end
-
-	// PWM Output
-	always @(posedge clk or posedge rst)
-	begin
-		if(rst)
-			pwm <= 1'd0;
-		else if(pwmov)
-			pwm <= 1'd1;
-		else if (tmrov)
-			pwm <= 1'd0;
-	end
-
-endmodule

diff --git a/verilog/rtl/user_project/rtl/IPs/QSPI_XIP_CTRL.v b/verilog/rtl/user_project/rtl/IPs/QSPI_XIP_CTRL.v
deleted file mode 100644
index 482902c..0000000
--- a/verilog/rtl/user_project/rtl/IPs/QSPI_XIP_CTRL.v
+++ /dev/null

@@ -1,296 +0,0 @@
-`timescale 1ns/1ps
-`default_nettype none
-
-// uncomment the following line to use the optimized cache (SKY130A only)
-//`define NO_HC_CACHE
-
-/*
-    AHB-Lite Quad I/O flash reader with 32x16 DM$
-    Intended to be used to execute from an external Quad I/O SPI Flash Memory
-*/
-module QSPI_XIP_CTRL(
-    // AHB-Lite Slave Interface
-    input               HCLK,
-    input               HRESETn,
-    input               HSEL,
-    input wire [31:0]   HADDR,
-    input wire [1:0]    HTRANS,
-    //input wire [31:0]   HWDATA,
-    input wire          HWRITE,
-    input wire          HREADY,
-    output reg          HREADYOUT,
-    output wire [31:0]  HRDATA,
-
-    // External Interface to Quad I/O
-    output              sck,
-    output              ce_n,
-    input   wire[3:0]   din,
-    output      [3:0]   dout,
-    output  wire        douten     
-);
-
-    // Cache wires/buses
-    wire [31:0]     c_datao;
-    wire [127:0]    c_line;
-    wire            c_hit;
-    reg [1:0]       c_wr;
-    wire [23:0]     c_A;
-
-    // Flash Reader wires
-    wire            fr_rd;
-    wire            fr_done;
-
-    // The State Machine
-    localparam [1:0] st_idle    = 2'b00;
-    localparam [1:0] st_wait    = 2'b01;
-    localparam [1:0] st_rw      = 2'b10;
-    reg [1:0]   state, nstate;
-
-    //AHB-Lite Address Phase Regs
-    reg             last_HSEL;
-    reg [31:0]      last_HADDR;
-    reg             last_HWRITE;
-    reg [1:0]       last_HTRANS;
-
-    always@ (posedge HCLK) begin
-        if(HREADY) begin
-            last_HSEL       <= HSEL;
-            last_HADDR      <= HADDR;
-            last_HWRITE     <= HWRITE;
-            last_HTRANS     <= HTRANS;
-        end
-    end
-
-    always @ (posedge HCLK or negedge HRESETn)
-        if(HRESETn == 0) state <= st_idle;
-        else 
-            state <= nstate;
-
-    always @* begin
-        nstate = st_idle;
-        case(state)
-            st_idle :   if(HTRANS[1] & HSEL & HREADY & c_hit) nstate = st_rw;
-                        else if(HTRANS[1] & HSEL & HREADY & ~c_hit) nstate = st_wait;
-            st_wait :   if(c_wr[1]) nstate = st_rw; 
-                        else  nstate = st_wait;
-            st_rw   :   //nstate = st_idle; 
-                        if(HTRANS[1] & HSEL & HREADY & c_hit) nstate = st_rw;
-                        else if(HTRANS[1] & HSEL & HREADY & ~c_hit) nstate = st_wait;
-        endcase
-    end
-    
-    //assign HREADYOUT    = (state==st_rw);
-    always @(posedge HCLK or negedge HRESETn)
-        if(!HRESETn) HREADYOUT <= 1'b1;
-        else
-            case (state)
-                st_idle :   if(HTRANS[1] & HSEL & HREADY & c_hit) HREADYOUT <= 1'b1;
-                            else if(HTRANS[1] & HSEL & HREADY & ~c_hit) HREADYOUT <= 1'b0;
-                            else HREADYOUT <= 1'b1;
-                st_wait :   if(c_wr[1]) HREADYOUT <= 1'b1;
-                            else HREADYOUT <= 1'b0;
-                st_rw   :   if(HTRANS[1] & HSEL & HREADY & c_hit) HREADYOUT <= 1'b1;
-                            else if(HTRANS[1] & HSEL & HREADY & ~c_hit) HREADYOUT <= 1'b0;
-                            //else HREADYOUT <= 1'b1;
-            endcase
-        
-
-    assign fr_rd        =   ( HTRANS[1] & HSEL & HREADY & ~c_hit & (state==st_idle) ) |
-                            ( HTRANS[1] & HSEL & HREADY & ~c_hit & (state==st_rw) );
-
-    assign c_A          = //((state==st_idle) || (state==st_wait)) ? HADDR[23:0] : 
-                            last_HADDR[23:0];
-`ifdef NO_HC_CACHE
-    DMC_32x16
-`else
-    DMC_32x16HC
-`endif
-                CACHE ( .clk(HCLK), .rst_n(HRESETn), 
-                        .A(last_HADDR[23:0]), .A_h(HADDR[23:0]), .Do(c_datao), .hit(c_hit), 
-                        .line(c_line), .wr(c_wr[1]) );
-    
-    FLASH_READER FR (   .clk(HCLK), .rst_n(HRESETn), 
-                        .addr({HADDR[23:4], 4'd0}), .rd(fr_rd), .done(fr_done), .line(c_line),
-                        .sck(sck), .ce_n(ce_n), .din(din), .dout(dout), .douten(douten) );
-
-    assign HRDATA   = c_datao;
-    //always @(posedge HCLK)
-    //    HRDATA <= c_datao;
-
-    //assign c_wr     = fr_done;
-    always @ (posedge HCLK) begin
-        c_wr[0] <= fr_done;
-        c_wr[1] <= c_wr[0];
-    end
-  
-endmodule
-
-/*
-    RTL Model for reading from Quad I/O flash using the QUAD I/O FAST READ (0xEB) command
-    The Quad I/O bit has to be set in the flash memory (through flash programming); the 
-    provided flash memory model has the bit set.
-
-    Every transaction reads 128 bits (16 bytes) from the flash.
-    To start a transaction, provide the memory address and assert rd for 1 clock cycle.
-    done is a sserted for 1 clock cycle when the data is ready
-
-*/
-module FLASH_READER #(parameter LINE_SIZE=128)(
-    input   wire                    clk,
-    input   wire                    rst_n,
-    input   wire [23:0]             addr,
-    input   wire                    rd,
-    output  wire                    done,
-    output  wire [LINE_SIZE-1: 0]   line,      
-
-    output  reg                     sck,
-    output  reg                     ce_n,
-    input   wire[3:0]               din,
-    output      [3:0]               dout,
-    output  wire                    douten
-);
-
-    localparam LINE_BYTES = LINE_SIZE/8;
-    localparam LINE_CYCLES = LINE_BYTES * 8;
-
-    parameter IDLE=1'b0, READ=1'b1;
-
-    reg         state, nstate;
-    reg [7:0]   counter;
-    reg [23:0]  saddr;
-    reg [7:0]   data [LINE_BYTES-1 : 0]; 
-
-    reg         first;
-
-    wire[7:0]   EBH     = 8'heb;
-    
-    // for debugging
-    wire [7:0] data_0 = data[0];
-    wire [7:0] data_1 = data[1];
-    wire [7:0] data_15 = data[15];
-
-
-    always @*
-        case (state)
-            IDLE: if(rd) nstate = READ; else nstate = IDLE;
-            READ: if(done) nstate = IDLE; else nstate = READ;
-        endcase 
-
-    always @ (posedge clk or negedge rst_n)
-        if(!rst_n) first = 1'b1;
-        else if(first & done) first <= 0;
-
-    
-    always @ (posedge clk or negedge rst_n)
-        if(!rst_n) state = IDLE;
-        else state <= nstate;
-
-    always @ (posedge clk or negedge rst_n)
-        if(!rst_n) sck <= 1'b0;
-        else if(~ce_n) sck <= ~ sck;
-        else if(state == IDLE) sck <= 1'b0;
-
-    always @ (posedge clk or negedge rst_n)
-        if(!rst_n) ce_n <= 1'b1;
-        else if(state == READ) ce_n <= 1'b0;
-        else ce_n <= 1'b1;
-
-    always @ (posedge clk or negedge rst_n)
-        if(!rst_n) counter <= 8'b0;
-        else if(sck & ~done) counter <= counter + 1'b1;
-        else if(state == IDLE) 
-            if(first) counter <= 8'b0;
-            else counter <= 8'd8;
-
-    always @ (posedge clk or negedge rst_n)
-        if(!rst_n) saddr <= 24'b0;
-        else if((state == IDLE) && rd) saddr <= addr;
-
-    always @ (posedge clk)
-        if(counter >= 20 && counter <= 19+LINE_BYTES*2)
-            if(sck) data[counter/2 - 10] <= {data[counter/2 - 10][3:0], din}; // Optimize!
-
-    //assign busy = (state == READ);
-
-    assign dout     =   (counter < 8)   ? EBH[7 - counter] :
-                        (counter == 8)  ? saddr[23:20] : 
-                        (counter == 9)  ? saddr[19:16] :
-                        (counter == 10)  ? saddr[15:12] :
-                        (counter == 11)  ? saddr[11:8] :
-                        (counter == 12)  ? saddr[7:4] :
-                        (counter == 13)  ? saddr[3:0] :
-                        (counter == 14)  ? 4'hA :
-                        (counter == 15)  ? 4'h5 : 4'h0;    
-        
-    assign douten   = (counter < 20);
-
-    assign done     = (counter == 19+LINE_BYTES*2);
-
-
-    generate
-        genvar i; 
-        for(i=0; i<LINE_BYTES; i=i+1)
-            assign line[i*8+7: i*8] = data[i];
-    endgenerate
-
-endmodule
-
-
-
-/*
-    32 lines x 16 bytes Direct Mapped Cache
-*/
-`ifdef NO_HC_CACHE
-
-module DMC_32x16 (
-    input wire          clk,
-    input wire          rst_n,
-    // 
-    input wire  [23:0]  A,
-    input wire  [23:0]  A_h,
-    output wire [31:0]  Do,
-    output wire         hit,
-    //
-    input wire [127:0]  line,
-    input wire          wr
-);
-
-    //
-    reg [127:0] LINES   [31:0];
-    reg [14:0]  TAGS    [31:0];
-    reg         VALID   [31:0];
-
-    wire [3:0]  offset  = A[3:0];
-    wire [4:0]  index   = A[8:4];
-    wire [14:0] tag     = A[23:9];
-
-    wire [4:0]  index_h   = A_h[8:4];
-    wire [14:0] tag_h     = A_h[23:9];
-
-    
-    assign  hit =   VALID[index_h] & (TAGS[index_h] == tag_h);
-
-    assign  Do  =   (offset[3:2] == 2'd0) ?  LINES[index][31:0] :
-                    (offset[3:2] == 2'd1) ?  LINES[index][63:32] :
-                    (offset[3:2] == 2'd2) ?  LINES[index][95:64] :
-                    LINES[index][127:96];
-
-    // clear the VALID flags
-    integer i;
-    always @ (posedge clk or negedge rst_n)
-        if(!rst_n) 
-            for(i=0; i<32; i=i+1)
-                VALID[i] <= 1'b0;
-        else  if(wr)  VALID[index]    <= 1'b1;
-
-    always @(posedge clk)
-        if(wr) begin
-            LINES[index]    <= line;
-            TAGS[index]     <= tag;
-        end
-
-endmodule
-`endif
-
-
-

diff --git a/verilog/rtl/user_project/rtl/IPs/RAM_3Kx32.v b/verilog/rtl/user_project/rtl/IPs/RAM_3Kx32.v
deleted file mode 100644
index d9d1125..0000000
--- a/verilog/rtl/user_project/rtl/IPs/RAM_3Kx32.v
+++ /dev/null

@@ -1,73 +0,0 @@
-`timescale 1ns / 1ps
-`default_nettype none
-
-module RAM_3Kx32 (
-`ifdef USE_POWER_PINS
-    VPWR,
-    VGND,
-`endif
-    CLK,
-    WE,
-    EN,
-    Di,
-    Do,
-    A
-);
-    input           CLK;
-    input   [3:0]   WE;
-    input           EN;
-    input   [31:0]  Di;
-    output  [31:0]  Do;
-    input   [11:0]   A;
-
-    localparam BLOCKS=3;
-    wire  [3:0]       _EN_ ;
-    wire [31:0] _Do_ [BLOCKS-1:0];
-    wire [31:0] Do_pre;
-
-    generate 
-        genvar gi;
-        for(gi=0; gi<BLOCKS; gi=gi+1) 
-
-`ifdef NO_DFFRAM
-	DFFRAM_beh 
-`else
-	DFFRAM
-`endif
-            #(.COLS(4)) RAM (
-                .CLK(CLK),
-                .WE(WE),
-                .EN(_EN_[gi]),
-                .Di(Di),
-                .Do(_Do_[gi]),
-                .A(A[9:0])
-            );
-        
-    endgenerate 
-    
-    MUX4x1_32 MUX ( 
-    `ifdef USE_POWER_PINS
-        .VPWR(VPWR),
-        .VGND(VGND),
-    `endif
-        .A0(_Do_[0]), .A1(_Do_[1]), .A2(_Do_[2]), .A3(32'b0), .S(A[11:10]), .X(Do_pre) 
-    );
-    DEC2x4 DEC ( 
-    `ifdef USE_POWER_PINS
-        .VPWR(VPWR),
-        .VGND(VGND),
-    `endif
-        .EN(EN), .A(A[11:10]), .SEL(_EN_)
-    );
-
-    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (
-    `ifdef USE_POWER_PINS
-        .VPWR(VPWR),
-        .VGND(VGND),
-        .VPB(VPWR),
-        .VNB(VGND),
-    `endif
-        .X(Do), .A(Do_pre)
-    );
-    
-endmodule

diff --git a/verilog/rtl/user_project/rtl/IPs/RAM_4Kx32.v b/verilog/rtl/user_project/rtl/IPs/RAM_4Kx32.v
deleted file mode 100644
index 146ffa2..0000000
--- a/verilog/rtl/user_project/rtl/IPs/RAM_4Kx32.v
+++ /dev/null

@@ -1,52 +0,0 @@
-`timescale 1ns / 1ps
-`default_nettype none
-
-module RAM_4Kx32 (
-    CLK,
-    WE,
-    EN,
-    Di,
-    Do,
-    A
-);
-    input           CLK;
-    input   [3:0]   WE;
-    input           EN;
-    input   [31:0]  Di;
-    output  [31:0]  Do;
-    input   [11:0]   A;
-
-    localparam BLOCKS=4;
-    wire  [BLOCKS-1:0]       _EN_ ;
-    wire [31:0] _Do_ [BLOCKS-1:0];
-    wire [31:0] Do_pre;
-    wire [11:10] A_buf;
-    
-    generate 
-        genvar gi;
-        for(gi=0; gi<BLOCKS; gi=gi+1) 
-
-`ifdef USE_DFFRAM_BEH
-	DFFRAM_beh 
-`else
-	DFFRAM
-`endif
-            #(.COLS(4)) RAM (
-                .CLK(CLK),
-                .WE(WE),
-                .EN(_EN_[gi]),
-                .Di(Di),
-                .Do(_Do_[gi]),
-                .A(A[9:0])
-            );
-        
-    endgenerate 
-    
-    sky130_fd_sc_hd__clkbuf_8 ABUF[11:10] (.X(A_buf), .A(A[11:10]));
-
-    MUX4x1_32 MUX ( .A0(_Do_[0]), .A1(_Do_[1]), .A2(_Do_[2]), .A3(_Do_[3]), .S(A_buf), .X(Do_pre) );
-    DEC2x4 DEC ( .EN(EN), .A(A[11:10]), .SEL(_EN_) );
-
-    sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
-    
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/IPs/TIMER32.v b/verilog/rtl/user_project/rtl/IPs/TIMER32.v
deleted file mode 100644
index dc2f87f..0000000
--- a/verilog/rtl/user_project/rtl/IPs/TIMER32.v
+++ /dev/null

@@ -1,64 +0,0 @@
-/*
-	Mohamed Shalan (mshalan@aucegypt.edu)
-*/
-/*
-	A simple 32-bit timer
-	TMR : 32-bit counter
-	PRE: clock prescalar (tmer_clk = clk / (PRE+1))
-	TMRCMP: Timer CMP register
-	TMROV: Timer overflow (TMR>=TMRCMP)
-	TMROVCLR: Control signal to clear the TMROV flag
-*/
-
-
-`timescale 1ns/1ps
-`default_nettype none
-
-module TIMER32 (
-		input wire clk,
-		input wire rst,
-		output reg [31:0] TMR,
-		input wire [31:0] PRE,
-		input wire [31:0] TMRCMP,
-		output reg TMROV,
-		input wire TMROVCLR,
-		input wire TMREN
-	);
-
-	reg [31:0] 	clkdiv;
-	wire 		timer_clk = (clkdiv==PRE) ;
-	wire 		tmrov = (TMR == TMRCMP);
-
-	// Prescalar
-	always @(posedge clk or posedge rst)
-	begin
-		if(rst)
-			clkdiv <= 32'd0;
-		else if(timer_clk)
-			clkdiv <= 32'd0;
-		else if(TMREN)
-			clkdiv <= clkdiv + 32'd1;
-	end
-
-	// Timer
-	always @(posedge clk or posedge rst)
-	begin
-		if(rst)
-			TMR <= 32'd0;
-		else if(tmrov)
-			TMR <= 32'd0;
-		else if(timer_clk)
-			TMR <= TMR + 32'd1;
-	end
-
-	always @(posedge clk or posedge rst)
-	begin
-		if(rst)
-			TMROV <= 1'd0;
-		else if(TMROVCLR)
-			TMROV <= 1'd0;
-		else if(tmrov)
-			TMROV <= 1'd1;
-	end
-
-endmodule

diff --git a/verilog/rtl/user_project/rtl/IPs/WDT32.v b/verilog/rtl/user_project/rtl/IPs/WDT32.v
deleted file mode 100644
index 3eeea1e..0000000
--- a/verilog/rtl/user_project/rtl/IPs/WDT32.v
+++ /dev/null

@@ -1,56 +0,0 @@
-/*
-	Mohamed Shalan (mshalan@aucegypt.edu)
-*/
-
-/*
-	A simple 32-bit watchdog timer
-	WDTMR	: 32-bit down counter
-	WDLOAD	: 32-bit load value
-	WDOV	: WD Timer overflow (WDTMR==0)
-	TMROVCLR: Control signal to clear the WDOV flag
-*/
-
-
-`timescale 1ns/1ps
-`default_nettype none
-
-module WDT32 (
-		input wire clk,
-		input wire rst,
-		output reg [31:0] WDTMR,
-		input wire [31:0] WDLOAD,
-		output reg WDOV,
-		input wire WDOVCLR,
-		input wire WDEN
-);
-
-	wire	wdov = (WDTMR == 32'd0);
-	
-	// WDTimer
-	always @(posedge clk or posedge rst)
-	begin
-		if(rst)
-			WDTMR <= 32'h0;
-		else if(wdov & WDEN)
-			WDTMR <= WDLOAD;
-		else if(WDEN)
-			WDTMR <= WDTMR - 32'd1;
-		else if(~WDEN)
-		  WDTMR <= 32'h0;
-	end
-	
-	reg wden_p;
-	always @(posedge clk) 
-	  wden_p <= WDEN;
-
-	always @(posedge clk or posedge rst)
-	begin
-		if(rst)
-			WDOV <= 1'd0;
-		else if(WDOVCLR)
-			WDOV <= 1'd0;
-		else if(wdov & wden_p)
-			WDOV <= 1'd1;
-	end
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/IPs/apb2i2c/apb2i2c.v b/verilog/rtl/user_project/rtl/IPs/apb2i2c/apb2i2c.v
deleted file mode 100644
index 4995421..0000000
--- a/verilog/rtl/user_project/rtl/IPs/apb2i2c/apb2i2c.v
+++ /dev/null

@@ -1,56 +0,0 @@
-module APB_I2C(
-    //APB Inputs
-    input wire PCLK,
-    input wire PRESETn,
-    input wire PWRITE,
-    input wire [31:0] PWDATA,
-    input wire [31:0] PADDR,
-    input wire PENABLE,
-    
-    input PSEL,
-    
-    //APB Outputs
-    output wire PREADY,
-    output wire [31:0] PRDATA,
-
-    // i2c Ports
-    input 	wire scl_i,	    // SCL-line input
-	output 	wire scl_o,	    // SCL-line output (always 1'b0)
-	output 	wire scl_oen_o, // SCL-line output enable (active low)
-	input	wire sda_i,     // SDA-line input
-	output	wire sda_o,	    // SDA-line output (always 1'b0)
-	output	wire sda_oen_o // SDA-line output enable (active low)
-    
-);
-
-  assign PREADY = 1'b1; //always ready
-  
-  wire[7:0] io_do;
-  wire io_we = PENABLE & PWRITE & PREADY & PSEL;
-  wire io_re = PENABLE & ~PWRITE & PREADY & PSEL;
-
-  wire i2c_irq;
-  
-  i2c_master i2c (
-    		.sys_clk(PCLK),
-    		.sys_rst(~PRESETn),
-    		//
-    		.io_a(PADDR[7:2]),
-		    .io_di(PWDATA[7:0]),
-			.io_do(io_do),
-			.io_re(io_re),
-			.io_we(io_we),
-			//
-			.i2c_irq(i2c_irq),
-			//
-			.scl_i(scl_i),	   // SCL-line input
-			.scl_o(scl_o),	   // SCL-line output (always 1'b0)
-			.scl_oen_o(scl_oen_o), // SCL-line output enable (active low)
-			.sda_i(sda_i),		// SDA-line input
-			.sda_o(sda_o),	   // SDA-line output (always 1'b0)
-			.sda_oen_o(sda_oen_o)  // SDA-line output enable (active low)
-	);
-  
-  assign PRDATA[31:0] = io_do;//I2C_DATA_REG;
-  
-endmodule

diff --git a/verilog/rtl/user_project/rtl/IPs/i2c_master.v b/verilog/rtl/user_project/rtl/IPs/i2c_master.v
deleted file mode 100644
index a729e98..0000000
--- a/verilog/rtl/user_project/rtl/IPs/i2c_master.v
+++ /dev/null

@@ -1,931 +0,0 @@
-/*
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2001 Richard Herveille                        ////
-////                    richard@asics.ws                         ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-*/
-/*
-	i2c master controller. 
-	Based on the OpenCores i2c master controller by Richard Herveille 
-	Updated to: 
-		(1) remove unnecessary latches and
-		(2) enable asynchronous reading
-	Author: Mohamed Shalan
-*/
-
-
-`timescale 1ns/1ps
-`default_nettype none
-
-
-// bitcontroller states
-`define I2C_CMD_NOP   4'b0000
-`define I2C_CMD_START 4'b0001
-`define I2C_CMD_STOP  4'b0010
-`define I2C_CMD_WRITE 4'b0100
-`define I2C_CMD_READ  4'b1000
-
-
-module i2c_master_bit_ctrl (
-    input             clk,      // system clock
-    input             rst,      // asynchronous active high reset
-    input             ena,      // core enable signal
-
-    input      [15:0] clk_cnt,  // clock prescale value
-
-    input      [ 3:0] cmd,      // command (from byte controller)
-    output reg        cmd_ack,  // command complete acknowledge
-    output reg        busy,     // i2c bus busy
-    output reg        al,       // i2c bus arbitration lost
-
-    input             din,
-    output reg        dout,
-
-    input             scl_i,    // i2c clock line input
-    output            scl_o,    // i2c clock line output
-    output reg        scl_oen,  // i2c clock line output enable (active low)
-    input             sda_i,    // i2c data line input
-    output            sda_o,    // i2c data line output
-    output reg        sda_oen   // i2c data line output enable (active low)
-);
-
-    //
-    // variable declarations
-    //
-
-    reg [ 1:0] cSCL, cSDA;      // capture SCL and SDA
-    reg [ 2:0] fSCL, fSDA;      // SCL and SDA filter inputs
-    reg        sSCL, sSDA;      // filtered and synchronized SCL and SDA inputs
-    reg        dSCL, dSDA;      // delayed versions of sSCL and sSDA
-    reg        dscl_oen;        // delayed scl_oen
-    reg        sda_chk;         // check SDA output (Multi-master arbitration)
-    reg        clk_en;          // clock generation signals
-    reg        slave_wait;      // slave inserts wait states
-    reg [15:0] cnt;             // clock divider counter (synthesis)
-    reg [13:0] filter_cnt;      // clock divider for filter
-
-
-    // state machine variable
-    reg [17:0] c_state;
-
-    //
-    // module body
-    //
-
-    // whenever the slave is not ready it can delay the cycle by pulling SCL low
-    // delay scl_oen
-    always @(posedge clk)
-      dscl_oen <= #1 scl_oen;
-
-    // slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
-    // slave_wait remains asserted until the slave releases SCL
-    always @(posedge clk or posedge rst)
-      if (rst) slave_wait <= 1'b0;
-      else         slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
-
-    // master drives SCL high, but another master pulls it low
-    // master start counting down its low cycle now (clock synchronization)
-    wire scl_sync   = dSCL & ~sSCL & scl_oen;
-
-
-    // generate clk enable signal
-    always @(posedge clk or posedge rst)
-      if (rst)
-      begin
-          cnt    <= #1 16'h0;
-          clk_en <= #1 1'b1;
-      end
-      else if ( ~|cnt || !ena || scl_sync)
-      begin
-          cnt    <= #1 clk_cnt;
-          clk_en <= #1 1'b1;
-      end
-      else if (slave_wait)
-      begin
-          cnt    <= #1 cnt;
-          clk_en <= #1 1'b0;    
-      end
-      else
-      begin
-          cnt    <= #1 cnt - 16'h1;
-          clk_en <= #1 1'b0;
-      end
-
-
-    // generate bus status controller
-
-    // capture SDA and SCL
-    // reduce metastability risk
-    always @(posedge clk or posedge rst)
-      if (rst)
-      begin
-          cSCL <= #1 2'b00;
-          cSDA <= #1 2'b00;
-      end
-      else
-      begin
-          cSCL <= {cSCL[0],scl_i};
-          cSDA <= {cSDA[0],sda_i};
-      end
-
-
-    // filter SCL and SDA signals; (attempt to) remove glitches
-    always @(posedge clk or posedge rst)
-      if      (rst) filter_cnt <= 14'h0;
-      else if (!ena ) filter_cnt <= 14'h0;
-      else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
-      else                   filter_cnt <= filter_cnt -1;
-
-
-    always @(posedge clk or posedge rst)
-      if (rst)
-      begin
-          fSCL <= 3'b111;
-          fSDA <= 3'b111;
-      end
-      else if (~|filter_cnt)
-      begin
-          fSCL <= {fSCL[1:0],cSCL[1]};
-          fSDA <= {fSDA[1:0],cSDA[1]};
-      end
-
-
-    // generate filtered SCL and SDA signals
-    always @(posedge clk or posedge rst)
-	  if (rst)
-      begin
-          sSCL <= #1 1'b1;
-          sSDA <= #1 1'b1;
-
-          dSCL <= #1 1'b1;
-          dSDA <= #1 1'b1;
-      end
-      else
-      begin
-          sSCL <= #1 &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
-          sSDA <= #1 &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
-
-          dSCL <= #1 sSCL;
-          dSDA <= #1 sSDA;
-      end
-
-    // detect start condition => detect falling edge on SDA while SCL is high
-    // detect stop condition => detect rising edge on SDA while SCL is high
-    reg sta_condition;
-    reg sto_condition;
-    always @(posedge clk or posedge rst)
-      if (rst)
-      begin
-          sta_condition <= #1 1'b0;
-          sto_condition <= #1 1'b0;
-      end
-      else
-      begin
-          sta_condition <= #1 ~sSDA &  dSDA & sSCL;
-          sto_condition <= #1  sSDA & ~dSDA & sSCL;
-      end
-
-
-    // generate i2c bus busy signal
-    always @(posedge clk or posedge rst)
-      if (rst    ) busy <= #1 1'b0;
-      else              busy <= #1 (sta_condition | busy) & ~sto_condition;
-
-
-    // generate arbitration lost signal
-    // aribitration lost when:
-    // 1) master drives SDA high, but the i2c bus is low
-    // 2) stop detected while not requested
-    reg cmd_stop;
-    always @(posedge clk or posedge rst)
-      if (rst)
-          cmd_stop <= #1 1'b0;
-      else if (clk_en)
-          cmd_stop <= #1 cmd == `I2C_CMD_STOP;
-
-    always @(posedge clk or posedge rst)
-      if (rst)
-          al <= #1 1'b0;
-      else
-          al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
-
-
-    // generate dout signal (store SDA on rising edge of SCL)
-    always @(posedge clk)
-      if (sSCL & ~dSCL) dout <= #1 sSDA;
-
-
-    // generate statemachine
-
-    // nxt_state decoder
-    parameter [17:0] idle    = 18'b0_0000_0000_0000_0000;
-    parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
-    parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
-    parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
-    parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
-    parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
-    parameter [17:0] stop_a  = 18'b0_0000_0000_0010_0000;
-    parameter [17:0] stop_b  = 18'b0_0000_0000_0100_0000;
-    parameter [17:0] stop_c  = 18'b0_0000_0000_1000_0000;
-    parameter [17:0] stop_d  = 18'b0_0000_0001_0000_0000;
-    parameter [17:0] rd_a    = 18'b0_0000_0010_0000_0000;
-    parameter [17:0] rd_b    = 18'b0_0000_0100_0000_0000;
-    parameter [17:0] rd_c    = 18'b0_0000_1000_0000_0000;
-    parameter [17:0] rd_d    = 18'b0_0001_0000_0000_0000;
-    parameter [17:0] wr_a    = 18'b0_0010_0000_0000_0000;
-    parameter [17:0] wr_b    = 18'b0_0100_0000_0000_0000;
-    parameter [17:0] wr_c    = 18'b0_1000_0000_0000_0000;
-    parameter [17:0] wr_d    = 18'b1_0000_0000_0000_0000;
-
-    always @(posedge clk or posedge rst)
-      if (rst)
-      begin
-          c_state <= #1 idle;
-          cmd_ack <= #1 1'b0;
-          scl_oen <= #1 1'b1;
-          sda_oen <= #1 1'b1;
-          sda_chk <= #1 1'b0;
-      end
-      else if (al)
-      begin
-          c_state <= #1 idle;
-          cmd_ack <= #1 1'b0;
-          scl_oen <= #1 1'b1;
-          sda_oen <= #1 1'b1;
-          sda_chk <= #1 1'b0;
-      end
-      else
-      begin
-          cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
-
-          if (clk_en)
-              case (c_state)
-                    // idle state
-                    idle:
-                    begin
-                        case (cmd)
-                             `I2C_CMD_START: c_state <= #1 start_a;
-                             `I2C_CMD_STOP:  c_state <= #1 stop_a;
-                             `I2C_CMD_WRITE: c_state <= #1 wr_a;
-                             `I2C_CMD_READ:  c_state <= #1 rd_a;
-                             default:        c_state <= #1 idle;
-                        endcase
-
-                        scl_oen <= #1 scl_oen; // keep SCL in same state
-                        sda_oen <= #1 sda_oen; // keep SDA in same state
-                        sda_chk <= #1 1'b0;    // don't check SDA output
-                    end
-
-                    // start
-                    start_a:
-                    begin
-                        c_state <= #1 start_b;
-                        scl_oen <= #1 scl_oen; // keep SCL in same state
-                        sda_oen <= #1 1'b1;    // set SDA high
-                        sda_chk <= #1 1'b0;    // don't check SDA output
-                    end
-
-                    start_b:
-                    begin
-                        c_state <= #1 start_c;
-                        scl_oen <= #1 1'b1; // set SCL high
-                        sda_oen <= #1 1'b1; // keep SDA high
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    start_c:
-                    begin
-                        c_state <= #1 start_d;
-                        scl_oen <= #1 1'b1; // keep SCL high
-                        sda_oen <= #1 1'b0; // set SDA low
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    start_d:
-                    begin
-                        c_state <= #1 start_e;
-                        scl_oen <= #1 1'b1; // keep SCL high
-                        sda_oen <= #1 1'b0; // keep SDA low
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    start_e:
-                    begin
-                        c_state <= #1 idle;
-                        cmd_ack <= #1 1'b1;
-                        scl_oen <= #1 1'b0; // set SCL low
-                        sda_oen <= #1 1'b0; // keep SDA low
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    // stop
-                    stop_a:
-                    begin
-                        c_state <= #1 stop_b;
-                        scl_oen <= #1 1'b0; // keep SCL low
-                        sda_oen <= #1 1'b0; // set SDA low
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    stop_b:
-                    begin
-                        c_state <= #1 stop_c;
-                        scl_oen <= #1 1'b1; // set SCL high
-                        sda_oen <= #1 1'b0; // keep SDA low
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    stop_c:
-                    begin
-                        c_state <= #1 stop_d;
-                        scl_oen <= #1 1'b1; // keep SCL high
-                        sda_oen <= #1 1'b0; // keep SDA low
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    stop_d:
-                    begin
-                        c_state <= #1 idle;
-                        cmd_ack <= #1 1'b1;
-                        scl_oen <= #1 1'b1; // keep SCL high
-                        sda_oen <= #1 1'b1; // set SDA high
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    // read
-                    rd_a:
-                    begin
-                        c_state <= #1 rd_b;
-                        scl_oen <= #1 1'b0; // keep SCL low
-                        sda_oen <= #1 1'b1; // tri-state SDA
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    rd_b:
-                    begin
-                        c_state <= #1 rd_c;
-                        scl_oen <= #1 1'b1; // set SCL high
-                        sda_oen <= #1 1'b1; // keep SDA tri-stated
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    rd_c:
-                    begin
-                        c_state <= #1 rd_d;
-                        scl_oen <= #1 1'b1; // keep SCL high
-                        sda_oen <= #1 1'b1; // keep SDA tri-stated
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    rd_d:
-                    begin
-                        c_state <= #1 idle;
-                        cmd_ack <= #1 1'b1;
-                        scl_oen <= #1 1'b0; // set SCL low
-                        sda_oen <= #1 1'b1; // keep SDA tri-stated
-                        sda_chk <= #1 1'b0; // don't check SDA output
-                    end
-
-                    // write
-                    wr_a:
-                    begin
-                        c_state <= #1 wr_b;
-                        scl_oen <= #1 1'b0; // keep SCL low
-                        sda_oen <= #1 din;  // set SDA
-                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
-                    end
-
-                    wr_b:
-                    begin
-                        c_state <= #1 wr_c;
-                        scl_oen <= #1 1'b1; // set SCL high
-                        sda_oen <= #1 din;  // keep SDA
-                        sda_chk <= #1 1'b0; // don't check SDA output yet
-                                            // allow some time for SDA and SCL to settle
-                    end
-
-                    wr_c:
-                    begin
-                        c_state <= #1 wr_d;
-                        scl_oen <= #1 1'b1; // keep SCL high
-                        sda_oen <= #1 din;
-                        sda_chk <= #1 1'b1; // check SDA output
-                    end
-
-                    wr_d:
-                    begin
-                        c_state <= #1 idle;
-                        cmd_ack <= #1 1'b1;
-                        scl_oen <= #1 1'b0; // set SCL low
-                        sda_oen <= #1 din;
-                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
-                    end
-
-              endcase
-      end
-
-
-    // assign scl and sda output (always gnd)
-    assign scl_o = 1'b0;
-    assign sda_o = 1'b0;
-
-endmodule
-
-module i2c_master_byte_ctrl (
-	clk, rst, ena, clk_cnt, start, stop, read, write, ack_in, din,
-	cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
-
-	//
-	// inputs & outputs
-	//
-	input clk;     // master clock
-	input rst;     // asynchronous active high reset
-	input ena;     // core enable signal
-
-	input [15:0] clk_cnt; // 4x SCL
-
-	// control inputs
-	input       start;
-	input       stop;
-	input       read;
-	input       write;
-	input       ack_in;
-	input [7:0] din;
-
-	// status outputs
-	output       cmd_ack;
-	reg cmd_ack;
-	output       ack_out;
-	reg ack_out;
-	output       i2c_busy;
-	output       i2c_al;
-	output [7:0] dout;
-
-	// I2C signals
-	input  scl_i;
-	output scl_o;
-	output scl_oen;
-	input  sda_i;
-	output sda_o;
-	output sda_oen;
-
-
-	//
-	// Variable declarations
-	//
-
-	// statemachine
-	parameter [4:0] ST_IDLE  = 5'b0_0000;
-	parameter [4:0] ST_START = 5'b0_0001;
-	parameter [4:0] ST_READ  = 5'b0_0010;
-	parameter [4:0] ST_WRITE = 5'b0_0100;
-	parameter [4:0] ST_ACK   = 5'b0_1000;
-	parameter [4:0] ST_STOP  = 5'b1_0000;
-
-	// signals for bit_controller
-	reg  [3:0] core_cmd;
-	reg        core_txd;
-	wire       core_ack, core_rxd;
-
-	// signals for shift register
-	reg [7:0] sr; //8bit shift register
-	reg       shift, ld;
-
-	// signals for state machine
-	wire       go;
-	reg  [2:0] dcnt;
-	wire       cnt_done;
-
-	//
-	// Module body
-	//
-
-	// hookup bit_controller
-	i2c_master_bit_ctrl bit_controller (
-		.clk     ( clk      ),
-		.rst     ( rst      ),
-		.ena     ( ena      ),
-		.clk_cnt ( clk_cnt  ),
-		.cmd     ( core_cmd ),
-		.cmd_ack ( core_ack ),
-		.busy    ( i2c_busy ),
-		.al      ( i2c_al   ),
-		.din     ( core_txd ),
-		.dout    ( core_rxd ),
-		.scl_i   ( scl_i    ),
-		.scl_o   ( scl_o    ),
-		.scl_oen ( scl_oen  ),
-		.sda_i   ( sda_i    ),
-		.sda_o   ( sda_o    ),
-		.sda_oen ( sda_oen  )
-	);
-
-	// generate go-signal
-	assign go = (read | write | stop) & ~cmd_ack;
-
-	// assign dout output to shift-register
-	assign dout = sr;
-
-	// generate shift register
-	always @(posedge clk or posedge rst)
-	  if (rst)
-	    sr <= #1 8'h0;
-	  else if (ld)
-	    sr <= #1 din;
-	  else if (shift)
-	    sr <= #1 {sr[6:0], core_rxd};
-
-	// generate counter
-	always @(posedge clk or posedge rst)
-	  if (rst)
-	    dcnt <= #1 3'h0;
-	  else if (ld)
-	    dcnt <= #1 3'h7;
-	  else if (shift)
-	    dcnt <= #1 dcnt - 3'h1;
-
-	assign cnt_done = ~(|dcnt);
-
-	//
-	// state machine
-	//
-	reg [4:0] c_state;
-
-	always @(posedge clk or posedge rst)
-	  if (rst)
-	    begin
-	        core_cmd <= #1 `I2C_CMD_NOP;
-	        core_txd <= #1 1'b0;
-	        shift    <= #1 1'b0;
-	        ld       <= #1 1'b0;
-	        cmd_ack  <= #1 1'b0;
-	        c_state  <= #1 ST_IDLE;
-	        ack_out  <= #1 1'b0;
-	    end
-	  else if (i2c_al)
-	   begin
-	       core_cmd <= #1 `I2C_CMD_NOP;
-	       core_txd <= #1 1'b0;
-	       shift    <= #1 1'b0;
-	       ld       <= #1 1'b0;
-	       cmd_ack  <= #1 1'b0;
-	       c_state  <= #1 ST_IDLE;
-	       ack_out  <= #1 1'b0;
-	   end
-	else
-	  begin
-	      // initially reset all signals
-	      core_txd <= #1 sr[7];
-	      shift    <= #1 1'b0;
-	      ld       <= #1 1'b0;
-	      cmd_ack  <= #1 1'b0;
-
-	      case (c_state) // synopsys full_case parallel_case
-	        ST_IDLE:
-	          if (go)
-	            begin
-	                if (start)
-	                  begin
-	                      c_state  <= #1 ST_START;
-	                      core_cmd <= #1 `I2C_CMD_START;
-	                  end
-	                else if (read)
-	                  begin
-	                      c_state  <= #1 ST_READ;
-	                      core_cmd <= #1 `I2C_CMD_READ;
-	                  end
-	                else if (write)
-	                  begin
-	                      c_state  <= #1 ST_WRITE;
-	                      core_cmd <= #1 `I2C_CMD_WRITE;
-	                  end
-	                else // stop
-	                  begin
-	                      c_state  <= #1 ST_STOP;
-	                      core_cmd <= #1 `I2C_CMD_STOP;
-	                  end
-
-	                ld <= #1 1'b1;
-	            end
-
-	        ST_START:
-	          if (core_ack)
-	            begin
-	                if (read)
-	                  begin
-	                      c_state  <= #1 ST_READ;
-	                      core_cmd <= #1 `I2C_CMD_READ;
-	                  end
-	                else
-	                  begin
-	                      c_state  <= #1 ST_WRITE;
-	                      core_cmd <= #1 `I2C_CMD_WRITE;
-	                  end
-
-	                ld <= #1 1'b1;
-	            end
-
-	        ST_WRITE:
-	          if (core_ack)
-	            if (cnt_done)
-	              begin
-	                  c_state  <= #1 ST_ACK;
-	                  core_cmd <= #1 `I2C_CMD_READ;
-	              end
-	            else
-	              begin
-	                  c_state  <= #1 ST_WRITE;       // stay in same state
-	                  core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
-	                  shift    <= #1 1'b1;
-	              end
-
-	        ST_READ:
-	          if (core_ack)
-	            begin
-	                if (cnt_done)
-	                  begin
-	                      c_state  <= #1 ST_ACK;
-	                      core_cmd <= #1 `I2C_CMD_WRITE;
-	                  end
-	                else
-	                  begin
-	                      c_state  <= #1 ST_READ;       // stay in same state
-	                      core_cmd <= #1 `I2C_CMD_READ; // read next bit
-	                  end
-
-	                shift    <= #1 1'b1;
-	                core_txd <= #1 ack_in;
-	            end
-
-	        ST_ACK:
-	          if (core_ack)
-	            begin
-	               if (stop)
-	                 begin
-	                     c_state  <= #1 ST_STOP;
-	                     core_cmd <= #1 `I2C_CMD_STOP;
-	                 end
-	               else
-	                 begin
-	                     c_state  <= #1 ST_IDLE;
-	                     core_cmd <= #1 `I2C_CMD_NOP;
-
-	                     // generate command acknowledge signal
-	                     cmd_ack  <= #1 1'b1;
-	                 end
-
-	                 // assign ack_out output to bit_controller_rxd (contains last received bit)
-	                 ack_out <= #1 core_rxd;
-
-	                 core_txd <= #1 1'b1;
-	             end
-	           else
-	             core_txd <= #1 ack_in;
-
-	        ST_STOP:
-	          if (core_ack)
-	            begin
-	                c_state  <= #1 ST_IDLE;
-	                core_cmd <= #1 `I2C_CMD_NOP;
-
-	                // generate command acknowledge signal
-	                cmd_ack  <= #1 1'b1;
-	            end
-
-	      endcase
-	  end
-endmodule
-
-
-module i2c_master #(
-	parameter base_addr = 6'h0
-)
-(
-	//
-    input wire sys_clk,
-    input wire sys_rst,
-    //
-    input wire [5:0] io_a,
-    input wire [7:0] io_di,
-    output reg [7:0] io_do,
-    input wire io_re,
-    input wire io_we,
-    //
-	output reg i2c_irq,
-	//
-	input wire scl_i,	   // SCL-line input
-	output wire scl_o,	   // SCL-line output (always 1'b0)
-	output wire scl_oen_o, // SCL-line output enable (active low)
-	input wire sda_i,      // SDA-line input
-	output wire sda_o,	   // SDA-line output (always 1'b0)
-	output wire sda_oen_o  // SDA-line output enable (active low)
-);
-
-    // register address	
-	localparam prer_low_addr 	= base_addr;
-	localparam prer_high_addr 	= base_addr + 6'd1;
-	localparam ctr_addr  		= base_addr + 6'd2;
-	localparam txr_addr  		= base_addr + 6'd3;
-	localparam rxr_addr  		= base_addr + 6'd4;
-	localparam cr_addr  			= base_addr + 6'd5;
-	localparam sr_addr  			= base_addr + 6'd6;
-	
-	wire csr_selected = (io_a == prer_low_addr) | (io_a == prer_high_addr) |
-						(io_a == ctr_addr) | (io_a == rxr_addr) |
-						(io_a == sr_addr) | (io_a == txr_addr) |
-						(io_a == cr_addr);
-	
-	//
-	// variable declarations
-	//
-
-	// registers
-	reg  [15:0] prer; // clock prescale register
-	reg  [ 7:0] ctr;  // control register
-	reg  [ 7:0] txr;  // transmit register
-	wire [ 7:0] rxr;  // receive register
-	reg  [ 7:0] cr;   // command register
-	wire [ 7:0] sr;   // status register
-
-	// done signal: command completed, clear command register
-	wire done;
-
-	// core enable signal
-	wire core_en;
-	wire ien;
-
-	// status register signals
-	wire irxack;
-	reg  rxack;       // received aknowledge from slave
-	reg  tip;         // transfer in progress
-	reg  irq_flag;    // interrupt pending flag
-	wire i2c_busy;    // bus busy (start signal detected)
-	wire i2c_al;      // i2c bus arbitration lost
-	reg  al;          // status register arbitration lost bit
-
-	//
-	// module body
-	//
-
-	// assign io_do
-	always @*
-	begin
-	  io_do = 8'd00;
-	  if(io_re & csr_selected)
-		case (io_a)
-			prer_low_addr: 		io_do = #1 prer[ 7:0];
-			prer_high_addr: 	io_do = #1 prer[15:8];
-			ctr_addr: 			io_do = #1 ctr;
-			rxr_addr: 			io_do = #1 rxr;
-			sr_addr: 			io_do = #1 sr;
-			txr_addr: 			io_do = #1 txr;
-			cr_addr: 			io_do = #1 cr;
-			default: 			io_do = 8'hff;   			 // reserved
-		endcase
-	end
-
-	/*
-	always @(posedge sys_clk)
-	begin
-	  //io_do <= 8'd00;
-	  if(io_re & csr_selected)
-		case (io_a)
-			prer_low_addr: 		io_do <= #1 prer[ 7:0];
-			prer_high_addr: 	io_do <= #1 prer[15:8];
-			ctr_addr: 			io_do <= #1 ctr;
-			rxr_addr: 			io_do <= #1 rxr;
-			sr_addr: 			io_do <= #1 sr;
-			txr_addr: 			io_do <= #1 txr;
-			cr_addr: 			io_do <= #1 cr;
-			default: 			;   			 // reserved
-		endcase
-	end
-*/
-	// generate registers
-	always @(posedge sys_clk or posedge sys_rst)
-	  if (sys_rst)
-	    begin
-	        prer <= #1 16'hffff;
-	        ctr  <= #1  8'h0;
-	        txr  <= #1  8'h0;
-	    end
-	  else
-	    if (io_we & csr_selected)
-	      case (io_a)
-	         prer_low_addr : 	prer [ 7:0] <= #1 io_di;
-	         prer_high_addr : 	prer [15:8] <= #1 io_di;
-	         ctr_addr : 				ctr <= #1 io_di;
-	         txr_addr : 				txr <= #1 io_di;
-	         default: ;
-	      endcase
-
-	// generate command register (special case)
-	always @(posedge sys_clk or posedge sys_rst)
-	  if (sys_rst)
-	    cr <= #1 8'h0;
-	  else if (io_we & (io_a == cr_addr))
-	    begin
-	        if (core_en)
-	          cr <= #1 io_di;
-	    end
-	  else
-	    begin
-	        if (done | i2c_al)
-	          cr[7:4] <= #1 4'h0;           // clear command bits when done
-	                                        // or when aribitration lost
-	        cr[2:1] <= #1 2'b0;             // reserved bits
-	        cr[0]   <= #1 1'b0;             // clear IRQ_ACK bit
-	    end
-
-
-	// decode command register
-	wire sta  = cr[7];
-	wire sto  = cr[6];
-	wire rd   = cr[5];
-	wire wr   = cr[4];
-	wire ack  = cr[3];
-	wire iack = cr[0];
-
-	// decode control register
-	assign core_en = ctr[7];
-	assign ien = ctr[6];
-
-	// hookup byte controller block
-	i2c_master_byte_ctrl byte_controller (
-		.clk      ( sys_clk     ),
-		.rst      ( sys_rst     ),
-		.ena      ( core_en      ),
-		.clk_cnt  ( prer         ),
-		.start    ( sta          ),
-		.stop     ( sto          ),
-		.read     ( rd           ),
-		.write    ( wr           ),
-		.ack_in   ( ack          ),
-		.din      ( txr          ),
-		.cmd_ack  ( done         ),
-		.ack_out  ( irxack       ),
-		.dout     ( rxr          ),
-		.i2c_busy ( i2c_busy     ),
-		.i2c_al   ( i2c_al       ),
-		.scl_i    ( scl_i    ),
-		.scl_o    ( scl_o    ),
-		.scl_oen  ( scl_oen_o ),
-		.sda_i    ( sda_i    ),
-		.sda_o    ( sda_o    ),
-		.sda_oen  ( sda_oen_o )
-	);
-
-	// status register block + interrupt request signal
-	always @(posedge sys_clk or posedge sys_rst)
-	  if (sys_rst)
-	    begin
-	        al       <= #1 1'b0;
-	        rxack    <= #1 1'b0;
-	        tip      <= #1 1'b0;
-	        irq_flag <= #1 1'b0;
-	    end
-	  else
-	    begin
-	        al       <= #1 i2c_al | (al & ~sta);
-	        rxack    <= #1 irxack;
-	        tip      <= #1 (rd | wr);
-	        irq_flag <= #1 (done | i2c_al /*| irq_flag*/) & ~iack; // interrupt request flag is always generated
-	    end
-
-	// generate interrupt request signals
-	always @(posedge sys_clk or posedge sys_rst)
-	  if (sys_rst)
-	    i2c_irq <= #1 1'b0;
-	  else
-	    i2c_irq <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
-
-	// assign status register bits
-	assign sr[7]   = rxack;
-	assign sr[6]   = i2c_busy;
-	assign sr[5]   = al;
-	assign sr[4:2] = 3'h0; // reserved
-	assign sr[1]   = tip;
-	assign sr[0]   = irq_flag;
-
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/IPs/spi_master.v b/verilog/rtl/user_project/rtl/IPs/spi_master.v
deleted file mode 100644
index c812ee4..0000000
--- a/verilog/rtl/user_project/rtl/IPs/spi_master.v
+++ /dev/null

@@ -1,250 +0,0 @@
-/**
- * Copyright (C) 2009 Ubixum, Inc.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
- **/
-
-// Author:    Lane Brooks
-// Date:      10/31/2009
-// Desc: Implements a low level SPI master interface. Set the
-//       DATA_WIDTH parameter at instatiation. Put the data you want
-//       to send on the 'datai' port and strobe the 'go' signal. The
-//       bits of 'datai' will get serially shifted out to the device
-//       and the bits coming back from the device will get serially
-//       shifted into the 'datao' register.  Hook up the 'csb',
-//       'sclk', 'din', and 'dout' wires to the device.  'busy' is
-//       high while the shift is running and goes low when the shift
-//       is complete.
-//
-//       The NUM_PORTS parameter can be used when the 'csb' and 'sclk'
-//       lines are shared with multiple devices and the 'din' and 'dout'
-//       lines are unique. For example, if you have two devices, the
-//       specify NUM_PORTS=2 and 'din' and 'dout' become width 2 ports
-//       and 'datai' and 'datao' become DATA_WIDTH*NUM_PORTS wide.
-//
-//       Set the CLK_DIVIDER_WIDTH at instantiation. The rate of
-//       'sclk' to the device is then set by the input 'clk_divider'.
-//       'clk_divider' must be at least 4.
-//
-//       The clock polarity and phasing of this master is set via the
-//       CPOL and CPHA inputs. See
-//       http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
-//       a description of these conventions.
-//
-
-
-`timescale 1ns/1ps
-`default_nettype none
-
-
-module spi_master
-  #(parameter DATA_WIDTH=16,
-    NUM_PORTS=1,
-    CLK_DIVIDER_WIDTH=8,
-    SAMPLE_PHASE=0
-    )
-  (input clk,
-   input resetb,
-   input CPOL,
-   input CPHA,
-   input [CLK_DIVIDER_WIDTH-1:0] clk_divider,
-
-   input go,
-   input [(NUM_PORTS*DATA_WIDTH)-1:0] datai,
-   output [(NUM_PORTS*DATA_WIDTH)-1:0] datao,
-   output reg busy,
-   output reg done,
-
-   input [NUM_PORTS-1:0] dout,
-   output [NUM_PORTS-1:0] din,
-   output reg csb,
-   output reg sclk
-   );
-
-   reg  [CLK_DIVIDER_WIDTH-1:0]  clk_count;
-   wire [CLK_DIVIDER_WIDTH-1:0]  next_clk_count = clk_count + 1;
-   wire pulse = next_clk_count == (clk_divider >> 1);
-   reg    state;
-
-`ifdef verilator
-   localparam LOG2_DATA_WIDTH = $clog2(DATA_WIDTH+1);
-`else
-   function integer log2;
-      input integer value;
-      integer       count;
-      begin
-         value = value-1;
-         for (count=0; value>0; count=count+1)
-           value = value>>1;
-         log2=count;
-      end
-   endfunction
-   localparam LOG2_DATA_WIDTH = log2(DATA_WIDTH+1);
-`endif
-
-   reg [LOG2_DATA_WIDTH:0] shift_count;
-
-   wire start = shift_count == 0;
-   /* verilator lint_off WIDTH */
-   wire stop  = shift_count >= 2*DATA_WIDTH-1;
-   /* verilator lint_on WIDTH */
-   reg 	stop_s;
-
-   localparam IDLE_STATE = 0,
-              RUN_STATE = 1;
-
-   sro #(.DATA_WIDTH(DATA_WIDTH)) sro[NUM_PORTS-1:0]
-     (.clk(clk),
-      .resetb(resetb),
-      .shift(pulse && !csb && (shift_count[0] == SAMPLE_PHASE) && !stop_s),
-      .dout(dout),
-      .datao(datao));
-
-   sri #(.DATA_WIDTH(DATA_WIDTH)) sri[NUM_PORTS-1:0]
-     (.clk(clk),
-      .resetb(resetb),
-      .datai(datai),
-      .sample(go && (state == IDLE_STATE)), // we condition on state so that if the user holds 'go' high, this will sample only at the start of the transfer
-      .shift(pulse && !csb && (shift_count[0] == 1) && !stop),
-      .din(din));
-
-`ifdef SYNC_RESET
-   always @(posedge clk) begin
-`else
-   always @(posedge clk or negedge resetb) begin
-`endif
-      if(!resetb) begin
-         clk_count <= 0;
-         shift_count <= 0;
-         sclk  <= 1;
-         csb   <= 1;
-         state <= IDLE_STATE;
-         busy  <= 0;
-         done  <= 0;
-	 stop_s <= 0;
-      end else begin
-         // generate the pulse train
-         if(pulse) begin
-            clk_count <= 0;
-	    stop_s <= stop;
-         end else begin
-            clk_count <= next_clk_count;
-         end
-
-
-         // generate csb
-         if(state == IDLE_STATE) begin
-            csb  <= 1;
-            shift_count <= 0;
-            done <= 0;
-            if(go && !busy) begin // the !busy condition here allows the user to hold go high and this will then run transactions back-to-back at maximum speed where busy drops at for at least one clock cycle but we stay in this idle state for two clock cycles. Staying in idle state for two cycles probably isn't a big deal since the serial clock is running slower anyway.
-               state  <= RUN_STATE;
-               busy   <= 1;
-            end else begin
-               busy   <= 0;
-            end
-         end else begin
-            if(pulse) begin
-               if(stop) begin
-                  //csb <= 1;
-                  if(done) begin
-		     state <= IDLE_STATE;
-		     done <= 0;
-		     busy <= 0;
-		  end else begin
-                     done  <= 1;
-		  end
-               end else begin
-                  csb <= 0;
-                  if(!csb) begin
-                     shift_count <= shift_count + 1;
-                  end
-               end
-            end
-         end
-
-         // generate sclk
-         if(pulse) begin
-            if((CPHA==1 && state==RUN_STATE && !stop) ||
-               (CPHA==0 && !csb && !stop)) begin
-               sclk <= !sclk;
-            end else begin
-               sclk <= CPOL;
-            end
-         end
-      end
-   end
-endmodule // spi_master
-
-module sri
-  // This is a shift register that sends data out to the di lines of
-  // spi slaves.
-  #(parameter DATA_WIDTH=16)
-  (input clk,
-   input resetb,
-   input [DATA_WIDTH-1:0] datai,
-   input sample,
-   input shift,
-   output din
-   );
-
-   reg [DATA_WIDTH-1:0] sr_reg;
-   assign din = sr_reg[DATA_WIDTH-1];
-
-`ifdef SYNC_RESET
-   always @(posedge clk) begin
-`else
-   always @(posedge clk or negedge resetb) begin
-`endif
-      if(!resetb) begin
-         sr_reg <= 0;
-      end else begin
-         if(sample) begin
-            sr_reg <= datai;
-         end else if(shift) begin
-            sr_reg <= sr_reg << 1;
-         end
-      end
-   end
-endmodule
-
-module sro
-  // This is a shift register that receives data on the dout lines
-  // from spi slaves.
-  #(parameter DATA_WIDTH=16)
-  (input clk,
-   input resetb,
-   input shift,
-   input dout,
-   output reg [DATA_WIDTH-1:0] datao
-   );
-   reg                     dout_s;
-
-`ifdef SYNC_RESET
-   always @(posedge clk) begin
-`else
-   always @(posedge clk or negedge resetb) begin
-`endif
-      if(!resetb) begin
-         dout_s <= 0;
-         datao <= 0;
-      end else begin
-         dout_s <= dout;
-         if(shift) begin
-            datao <= { datao[DATA_WIDTH-2:0], dout_s };
-         end
-      end
-   end
-endmodule
\ No newline at end of file

diff --git a/verilog/rtl/user_project/rtl/NfiVe32.v b/verilog/rtl/user_project/rtl/NfiVe32.v
deleted file mode 100755
index 97f0688..0000000
--- a/verilog/rtl/user_project/rtl/NfiVe32.v
+++ /dev/null

@@ -1,1281 +0,0 @@
-/*
- 	 _   _  __ ___     __   _________  
-	| \ | |/ _(_) \   / /__|___ /___ \ 
-	|  \| | |_| |\ \ / / _ \ |_ \ __) |
-	| |\  |  _| | \ V /  __/___) / __/ 
-	|_| \_|_| |_|  \_/ \___|____/_____|
-	Copyright 2020 Mohamed Shalan
-	
-	Licensed under the Apache License, Version 2.0 (the "License"); 
-	you may not use this file except in compliance with the License. 
-	You may obtain a copy of the License at:
-
-	http://www.apache.org/licenses/LICENSE-2.0
-
-	Unless required by applicable law or agreed to in writing, software 
-	distributed under the License is distributed on an "AS IS" BASIS, 
-	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
-	See the License for the specific language governing permissions and 
-	limitations under the License.
-*/
-/*
-	Started as a One day project on May 2, 2020 by Mohamed Shalan 
-	NfiVe32 is area optimized RV32IC core with the following features:
-	* Target clock frequency > 100MHz in 130nm technologies
-	* CPI ~ 3
-	* ASIC cell count: < 10K 
-		+ SKY130A (HD): ~8.5K @ CP=5.8ns (DLY3)
-	* Instruction Cycles (3/4)
-	    + C0 : Fetch and Decompress, 
-	    + C1 : Fetch cyle 2; optional, only used for unaligned 32-bit instructions
-	    + C2 : RF read, ALU & Branch, 
-	    + C3 : Memory & RF write-back
-	* A single AHB-Lite Master interface for both instructions and data
-	    + Instr: A(C3), I(C0)
-	    + Data: A(C2), D(C3)
-
-	To do:
-		- [X] Exception Handeling + PIC
-		- [X] Bus wait states
-		- [X] Some Performance counters (CYCLE and INSTRET)
-		- [X] Systick timer
-		- [] Wait for Interrupt Instruction (wfi)
-		- [] Comprehensive testing
-		- [X] Add a latch based Register File
-		- [X] Add hand-crafted ALU 
-*/
-
-
-`timescale 1ns/1ps
-`default_nettype none
-
-`define		USE_RF_MODULE
-//`define		USE_HC_REGF
-
-//`define		USE_RF_HC
-//`define		USE_ALU_HC
-
-//`define DBG
-
-// Macros used by all modules
-`define     SYNC_BEGIN(r, v)  always @ (posedge HCLK or negedge HRESETn) if(!HRESETn) r <= v; else begin
-`define     SYNC_END          end
-
-`define     IR_rs1          19:15
-`define     IR_rs2          24:20
-`define     IR_rd           11:7
-`define     IR_opcode       6:2
-`define     IR_funct3       14:12
-`define     IR_cond       	14:12
-`define     IR_funct7       31:25
-`define     IR_shamt        24:20
-`define     IR_csr          31:20
-
-`define     OPCODE_Branch   5'b11_000
-`define     OPCODE_Load     5'b00_000
-`define     OPCODE_Store    5'b01_000
-`define     OPCODE_JALR     5'b11_001
-`define     OPCODE_JAL      5'b11_011
-`define     OPCODE_Arith_I  5'b00_100
-`define     OPCODE_Arith_R  5'b01_100
-`define     OPCODE_AUIPC    5'b00_101
-`define     OPCODE_LUI      5'b01_101
-`define     OPCODE_SYSTEM   5'b11_100
-`define     OPCODE_Custom   5'b10_001
-
-`define     F3_ADD          3'b000
-`define     F3_SLL          3'b001
-`define     F3_SLT          3'b010
-`define     F3_SLTU         3'b011
-`define     F3_XOR          3'b100
-`define     F3_SRL          3'b101
-`define     F3_OR           3'b110
-`define     F3_AND          3'b111
-
-`define     BR_BEQ          3'b000
-`define     BR_BNE          3'b001
-`define     BR_BLT          3'b100
-`define     BR_BGE          3'b101
-`define     BR_BLTU         3'b110
-`define     BR_BGEU         3'b111
-
-//`define     OPCODE          IR[`IR_opcode]
-
-`define     ALU_ADD         4'b00_00
-`define     ALU_SUB         4'b00_01
-`define     ALU_PASS        4'b00_11
-`define     ALU_OR          4'b01_00
-`define     ALU_AND         4'b01_01
-`define     ALU_XOR         4'b01_11
-`define     ALU_SRL         4'b10_00
-`define     ALU_SRA         4'b10_10
-`define     ALU_SLL         4'b10_01
-`define     ALU_SLT         4'b11_01
-`define     ALU_SLTU        4'b11_11
-
-`define     SYS_EC_EB       3'b000
-`define     SYS_CSRRW       3'b001
-`define     SYS_CSRRS       3'b010
-`define     SYS_CSRRC       3'b011
-`define     SYS_CSRRWI      3'b101
-`define     SYS_CSRRSI      3'b110
-`define     SYS_CSRRCI      3'b111
-
-module RV32_DECOMP	(	
-				    	input   [15:0]  IRi,
-				    	output  [31:0]  IRo
-					);
-
-
-	reg     [31:0]  Instout;
-	wire    [15:0]  InstIn;
-
-	assign  InstIn = IRi; 
-
-	assign IRo  =  Instout;
-
-	//signals used for decoding the 16bit instruction: case and if statements
-	wire [1:0] op   =   InstIn[1:0];
-	wire [2:0] fun3 =   InstIn[15:13];
-	wire [1:0] fun2 =   InstIn[11:10];
-	wire [1:0] fun  =   InstIn[6:5];
-	wire [4:0] Brs1 =   InstIn[11:7];
-	wire [4:0] Brs2 =   InstIn[6:2];
-
-	//Decoding and encoding process
-	always @(*) begin
-		Instout = 32'd0;
-	    case(op)
-	        2'b00:begin 					//C0
-	            case(fun3)
-	                3'b000:begin            //C.ADDI4SPN
-	                    //addi rd0, x2, nzuimm[9:2].
-						Instout = {	2'b00,
-									InstIn[10:7],
-									InstIn[12:11],
-									InstIn[5],
-									InstIn[6],
-									2'b00,
-									5'b00010,
-									3'b000,
-									2'b01,
-									InstIn[4:2],
-									7'b0010011
-								};
-	                end
-	                3'b010:begin            //C.LW
-	                   //lw rd',offset[6:2](rs1').
-	                    Instout = {
-	                    			5'd0,InstIn[5],
-	                    			InstIn[12:10],
-	                    			InstIn[6],
-	                    			2'b00,2'b01,
-	                    			InstIn[9:7],
-	                    			3'b010,2'b01,
-	                    			InstIn[4:2],
-	                    			7'b0000011
-	                    		};
-	                end
-	                3'b110:begin 			//C.SW
-	                    //sw rs2',offset[6:2](rs1').
-	                    Instout = {
-	                    			5'd0,InstIn[5],
-	                    			InstIn[12],
-	                    			2'b01,
-	                    			InstIn[4:2],
-	                    			2'b01,
-	                    			InstIn[9:7],
-	                    			3'b010,
-	                    			InstIn[11:10],
-	                    			InstIn[6],
-	                    			2'b00,
-	                    			7'b0100011
-	                    		};
-	                end
-	            endcase
-	        end
-
-	        2'b01:begin                 //C1
-	            case(fun3)
-	                3'b000:begin            //C.ADDI
-	                	//addi rd, rd, nzimm[5:0].
-	                    Instout = {
-	                    			{6{InstIn[12]}},
-	                    			InstIn[12],
-	                    			InstIn[6:2],
-	                    			InstIn[11:7],
-	                    			3'b000,
-	                    			InstIn[11:7],
-	                    			7'b0010011
-	                    		};
-	                end
-	                3'b001:begin         //C.JAL
-	                	//jal x1, offset[11:1].
-	                    Instout = {
-	                    			InstIn[12],
-	                    			InstIn[8],
-	                    			InstIn[10:9],
-	                    			InstIn[6],
-	                    			InstIn[7],
-	                    			InstIn[2],
-	                    			InstIn[11],
-	                    			InstIn[5:3],
-	                    			InstIn[12],
-	                    			{8{InstIn[12]}},
-	                    			5'b00001,
-	                    			7'b1101111
-	                    		};
-	                end
-	                3'b010:begin            //C.LI
-	                	//addi rd, x0, imm[5:0].
-	                    Instout = {
-	                    			{6{InstIn[12]}},
-	                    			InstIn[12],
-	                    			InstIn[6:2],
-	                    			5'b00000,3'b000,
-	                    			InstIn[11:7],
-	                    			7'b0010011
-	                    		};
-	                end
-	                3'b011:begin            //C.LUI,C.ADDI16SP
-	                    case(Brs1)
-							5'b00010: begin     //C.ADDI16SP
-								//addi x2, x2, nzimm[9:4].
-								Instout = {
-											{3{InstIn[12]}},
-											InstIn[12],
-											InstIn[4:3],
-											InstIn[5],
-											InstIn[2],
-											InstIn[6],
-											4'd0,
-											Brs1,
-											3'b000,
-											Brs1,
-											7'b0010011
-										};
-							end
-	                    default: begin      //C.LUI
-	                    //lui rd, nzuimm[17:12].
-	                        Instout = {{14{InstIn[12]}},InstIn[12],InstIn[6:2],Brs1,7'b0110111};
-	                    end
-	                    endcase
-	                end
-	                3'b100:begin         //C.SRLI, C.SRAI, C.ANDI
-	                    case(fun2)
-	                    2'b00:begin     //C.SRLI
-	                    //srli rd', rd', shamt[5:0]
-	                        Instout = {7'b0000000,InstIn[6:2],2'b01,InstIn[9:7],3'b101,2'b01,InstIn[9:7],7'b0010011};
-	                    end
-	                    2'b01:begin     //C.SRAI
-	                    //srai rd', rd', shamt[5:0],
-	                        Instout = {7'b0100000,InstIn[6:2],2'b01,InstIn[9:7],3'b101,2'b01,InstIn[9:7],7'b0010011};
-	                    end
-	                    2'b10:begin     //C.ANDI
-	                    //andi rd', rd', imm[5:0].
-	                        Instout = {
-	                        			{6{InstIn[12]}},
-	                        			InstIn[12],
-	                        			InstIn[6:2],
-	                        			2'b01,
-	                        			InstIn[9:7],
-	                        			3'b111,2'b01,
-	                        			InstIn[9:7],
-	                        			7'b0010011
-	                        		};
-	                    end
-	                    2'b11:
-	                        if(!InstIn[12])begin
-	                            case(fun)
-	                                2'b11: begin    //C.AND
-	                                //and rd', rd', rs2'.
-	                                    Instout = {
-	                                    			7'b0000000,2'b01, 
-	                                    			InstIn[4:2],
-	                                    			2'b01,
-	                                    			InstIn[9:7],
-	                                    			3'b111,2'b01,
-	                                    			InstIn[9:7],
-	                                    			7'b0110011
-	                                    			};
-	                                end
-	                                2'b10: begin    //C.OR
-	                                //or rd', rd', rs2'.
-	                                    Instout = {
-	                                    			7'b0000000,2'b01, 
-	                                    			InstIn[4:2],
-	                                    			2'b01,
-	                                    			InstIn[9:7],
-	                                    			3'b110,2'b01,
-	                                    			InstIn[9:7],
-	                                    			7'b0110011
-	                                    			};
-	                                end
-	                                2'b01: begin    //C.XOR
-	                                //xor rd', rd', rs2'.
-	                                    Instout = {
-	                                    			7'b0000000,2'b01, 
-	                                    			InstIn[4:2],
-	                                    			2'b01,
-	                                    			InstIn[9:7],
-	                                    			3'b100,2'b01,
-	                                    			InstIn[9:7],
-	                                    			7'b0110011
-	                                    			};
-	                                end
-	                                2'b00: begin    //C.SUB
-	                                //sub rd', rd', rs2'.
-	                                    Instout = {7'b0100000,2'b01, InstIn[4:2],2'b01,InstIn[9:7],3'b000,2'b01,InstIn[9:7],7'b0110011};
-	                                end
-
-	                            endcase
-	                        end
-	                    endcase
-	                end
-	                3'b101:begin         //C.J
-	                //jal x0,offset[11:1].
-	                    Instout = {
-	                    			InstIn[12],
-	                    			InstIn[8],
-	                    			InstIn[10:9],
-	                    			InstIn[6],
-	                    			InstIn[7],
-	                    			InstIn[2],
-	                    			InstIn[11],
-	                    			InstIn[5:3],
-	                    			InstIn[12],
-	                    			{8{InstIn[12]}},
-	                    			5'b00000,
-	                    			7'b1101111
-	                    		};
-	                end
-	                3'b110:begin         //C.BEQZ
-	                //beq rs1', x0, offset[8:1].
-	                    Instout = {
-	                    			InstIn[12],
-	                    			{2{InstIn[12]}},
-	                    			InstIn[12],
-	                    			InstIn[6:5],
-	                    			InstIn[2],
-	                    			5'b00000,
-	                    			2'b01,
-	                    			InstIn[9:7],
-	                    			3'b000,
-	                    			InstIn[11:10],
-	                    			InstIn[4:3],
-	                    			InstIn[12],
-	                    			7'b1100011
-	                    		};
-	                end
-
-	                3'b111:begin         //C.BNEZ
-	                //bne rs1', x0, offset[8:1].
-	                    Instout = {
-	                    			InstIn[12],
-	                    			{2{InstIn[12]}},
-	                    			InstIn[12],
-	                    			InstIn[6:5],
-	                    			InstIn[2],
-	                    			5'b00000,
-	                    			2'b01,
-	                    			InstIn[9:7],
-	                    			3'b001,
-	                    			InstIn[11:10],
-	                    			InstIn[4:3],
-	                    			InstIn[12],
-	                    			7'b1100011
-	                    		};
-	                end
-	            endcase
-	        end
-
-	        2'b10:begin                 //C2
-	            case(fun3)
-	                3'b000:begin            //C.SLLI
-	                	//slli rd, rd, shamt[5:0],.
-	                    Instout = {
-	                    			7'b0000000,
-	                    			InstIn[6:2],
-	                    			InstIn[11:7],
-	                    			3'b001,
-	                    			InstIn[11:7],
-	                    			7'b0010011
-	                    		};
-	                end
-	                3'b010:begin            //C.LWSP
-	                	//lw rd,offset[7:2](x2).
-	                    Instout = 	{
-		                    			4'd0,InstIn[3:2],
-		                    			InstIn[12],
-		                    			InstIn[6:4],
-		                    			2'b00,5'b00010,3'b010,
-		                    			InstIn[11:7],
-		                    			7'b000011
-	                    			};
-	                end
-	                3'b100:begin            //C.JR, C.JALR, C.MV, C.ADD, C.EBREAK
-	                    case(InstIn[12])
-	                        1'b0: begin
-	                            if(!Brs2) begin             //C.JR
-	                            	//jalr x0, rs1, 0.
-	                                Instout = {12'd0,Brs1,3'b000,5'b00000,7'b1100111};
-	                            end
-	                            else begin                  //C.MV
-	                            //add rd, x0, rs2.
-	                                Instout = {7'b0000000,Brs2,5'b00000,3'b000,Brs1,7'b0110011};
-	                            end
-	                        end
-	                        1'b1: begin
-	                            if(!Brs2&&!Brs1) begin      //C.EBREAK
-	                                //EBREAK
-	                                Instout = {12'd1,5'd0,3'b000,5'd0,7'b1110011};
-	                            end
-	                            else if(!Brs2) begin        //C.JALR
-	                            //jalr x1, rs1, 0.
-	                                Instout = {12'd0,Brs1,3'b000,5'b00001,7'b1100111};
-	                            end
-	                            else begin                  //C.ADD
-	                            //add rd, rd, rs2.
-	                                Instout = {7'b0000000,Brs2,Brs1,3'b000,Brs1,7'b0110011};
-	                            end
-	                        end
-	                    endcase
-	                end
-	                3'b110:begin         //C.SWSP
-	                	//sw rs2,offset[7:2](x2).
-	                    Instout = {
-	                    			4'd0,InstIn[8:7],
-	                    			InstIn[12],
-	                    			InstIn[6:2],
-	                    			5'b00010,3'b010,
-	                    			InstIn[11:9],
-	                    			2'b00,7'b0100011
-	                    		};
-	                end
-	            endcase
-	        end
-	    endcase
-	end
-endmodule
-
-// The ALU and its modules
-`ifdef	USE_ALU_HC
-`include "../rtl/ALU_HC.v"
-`else
-// Mirioring Unit for the Shifter
-module mirror (input [31:0] in, output reg [31:0] out);
-    integer i;
-    always @ *
-        for(i=0; i<32; i=i+1)
-            out[i] = in[31-i];
-endmodule
-
-// Shift Right Unit
-module shr(input [31:0] a, output [31:0] r, input [4:0] shamt, input ar);
-
-    wire [31:0] r1, r2, r3, r4;
-
-    wire fill = ar ? a[31] : 1'b0;
-    assign r1 = shamt[0] ? {{1{fill}}, a[31:1]} : a;
-    assign r2 = shamt[1] ? {{2{fill}}, r1[31:2]} : r1;
-    assign r3 = shamt[2] ? {{4{fill}}, r2[31:4]} : r2;
-    assign r4 = shamt[3] ? {{8{fill}}, r3[31:8]} : r3;
-    assign r = shamt[4] ? {{16{fill}}, r4[31:16]} : r4;
-
-endmodule
-
-// The Shifter
-module shift(
-	input wire [31:0] a,
-	input wire [4:0] shamt,
-	input wire [1:0] typ,	// type[0] sll or srl - type[1] sra
-							// 00 : srl, 10 : sra, 01 : sll
-	output wire [31:0] r
-	);
-    wire [31 : 0] ma, my, y, x, sy;
-
-    mirror m1(.in(a), .out(ma));
-    mirror m2(.in(y), .out(my));
-
-    assign x = typ[0] ? ma : a;
-    shr sh0(.a(x), .r(y), .shamt(shamt), .ar(typ[1]));
-
-    assign r = typ[0] ? my : y;
-
-endmodule
-
-// The ALU
-module ALU(
-	input   wire [31:0] a, b,
-	input   wire [4:0]  shamt,
-	output  reg  [31:0] r,
-	output  wire        cf, zf, vf, sf,
-	input   wire [3:0]  alufn
-);
-
-    wire [31:0] add, sub, op_b;
-    wire cfa, cfs;
-
-    assign op_b = (~b);
-
-    assign {cf, add} = alufn[0] ? (a + op_b + 1'b1) : (a + b);
-
-    assign zf = (add == 0);
-    assign sf = add[31];
-    assign vf = (a[31] ^ (op_b[31]) ^ add[31] ^ cf);
-
-    wire[31:0] sh;
-    shift shift0 (
-        .a(a),
-        .shamt(shamt),
-        .typ(alufn[1:0]),
-        .r(sh)
-	);
-
-    always @ * begin
-        //r = 0;
-				(* full_case *)
-				(* parallel_case *)
-        case (alufn)
-            // arithmetic
-            4'b00_00 : r = add;
-            4'b00_01 : r = add;
-            4'b00_11 : r = b;
-            // logic
-            4'b01_00:  r = a | b;
-            4'b01_01:  r = a & b;
-            4'b01_11:  r = a ^ b;
-            // shift
-            4'b10_00:  r=sh;
-            4'b10_01:  r=sh;
-            4'b10_10:  r=sh;
-            // slt & sltu
-            4'b11_01:  r = {31'b0,(sf != vf)};
-            4'b11_11:  r = {31'b0,(~cf)};
-
-			default:	r = add;
-        endcase
-    end
-endmodule
-`endif
-// Immediate Generator
-module IMMGEN (
-    input  wire [31:0]  INSTR,
-    output reg  [31:0]  IMM
-);
-
-always @(*) begin
-	case (INSTR[`IR_opcode])
-		`OPCODE_Arith_I   : 	IMM = { {21{INSTR[31]}}, INSTR[30:25], INSTR[24:21], INSTR[20] };
-		`OPCODE_Store     :   	IMM = { {21{INSTR[31]}}, INSTR[30:25], INSTR[11:8], INSTR[7] };
-		`OPCODE_LUI       :   	IMM = { INSTR[31], INSTR[30:20], INSTR[19:12], 12'b0 };
-		`OPCODE_AUIPC     :   	IMM = { INSTR[31], INSTR[30:20], INSTR[19:12], 12'b0 };
-		`OPCODE_JAL       : 	IMM = { {12{INSTR[31]}}, INSTR[19:12], INSTR[20], INSTR[30:25], INSTR[24:21], 1'b0 };
-		`OPCODE_JALR      : 	IMM = { {21{INSTR[31]}}, INSTR[30:25], INSTR[24:21], INSTR[20] };
-		`OPCODE_Branch    : 	IMM = { {20{INSTR[31]}}, INSTR[7], INSTR[30:25], INSTR[11:8], 1'b0};
-		default           : 	IMM = { {21{INSTR[31]}}, INSTR[30:25], INSTR[24:21], INSTR[20] }; 
-	endcase
-end
-
-endmodule
-
-// Instruction decoder that generates the ALU operation
-module RV32_DEC(
-    input [31:0] INSTR,
-    output	reg  [3:0]	  alu_fn,
-    output alu_op2_src
-    
-);
-    wire [2:0]  func3       =   INSTR[`IR_funct3];
-    wire [6:0]  func7       =   INSTR[`IR_funct7];
-    wire [11:0] csr         =   INSTR[`IR_csr];
-    wire [4:0]  opcode      =   INSTR[`IR_opcode];
-    wire        W32         =   1;//sz[0] & sz[1];
-    wire        I           =   W32 & (opcode == `OPCODE_Arith_I);
-	wire        R           =   W32 & (opcode == `OPCODE_Arith_R);
-	wire        IorR        =   I | R;
-	wire        instr_logic = 	((IorR==1'b1) && ((func3==`F3_XOR) || (func3==`F3_AND) || (func3==`F3_OR)));
-	wire        instr_shift = 	((IorR==1'b1) && ((func3==`F3_SLL) || (func3==`F3_SRL) ));
-
-    wire        instr_slt   = 	((IorR==1'b1) && (func3==`F3_SLT));
-	wire        instr_sltu  = 	((IorR==1'b1) && (func3==`F3_SLTU));
-	wire        instr_store = 	W32 & (opcode == `OPCODE_Store);
-	wire        instr_load  = 	W32 & (opcode == `OPCODE_Load);
-	wire        instr_add   = 	R & (func3 == `F3_ADD) & (~func7[5]);
-	wire        instr_sub   = 	R & (func3 == `F3_ADD) & (func7[5]);
-	wire        instr_addi  = 	I & (func3 == `F3_ADD);
-	wire        instr_lui   = 	W32 & (opcode == `OPCODE_LUI);
-	wire        instr_auipc = 	W32 & (opcode == `OPCODE_AUIPC);
-	wire        instr_branch= 	W32 & (opcode == `OPCODE_Branch);
-	wire        instr_jalr  = 	W32 & (INSTR[`IR_opcode] == `OPCODE_JALR);
-	wire        instr_jal   = 	W32 & (INSTR[`IR_opcode] == `OPCODE_JAL);
-	wire        instr_sll   = 	((IorR==1'b1) && (func3 == `F3_SLL) && (func7 == 7'b0));
-	wire        instr_srl   = 	((IorR==1'b1) && (func3 == `F3_SRL) && (func7 == 7'b0));
-	wire        instr_sra   = 	((IorR==1'b1) && (func3 == `F3_SRL) && (func7 != 7'b0));
-	wire        instr_and   = 	((IorR==1'b1) && (func3 == `F3_AND));
-	wire        instr_or    = 	((IorR==1'b1) && (func3 == `F3_OR));
-	wire        instr_xor   = 	((IorR==1'b1) && (func3 == `F3_XOR));
-
-    assign      alu_op2_src =   R;
-
-    always @ * begin
-            case (1'b1)
-                instr_load  :   alu_fn = `ALU_ADD;
-                instr_addi  :   alu_fn = `ALU_ADD;
-                instr_store :   alu_fn = `ALU_ADD;
-                instr_add   :   alu_fn = `ALU_ADD;
-                instr_jalr  :   alu_fn = `ALU_ADD;
-
-                instr_lui   :   alu_fn = `ALU_PASS;
-
-                instr_sll   :   alu_fn = `ALU_SLL;
-                instr_srl   :   alu_fn = `ALU_SRL;
-                instr_sra   :   alu_fn = `ALU_SRA;
-
-                instr_slt   :   alu_fn = `ALU_SLT;
-                instr_sltu  :   alu_fn = `ALU_SLTU;
-
-                instr_and   :   alu_fn = `ALU_AND;
-                instr_or    :   alu_fn = `ALU_OR;
-                instr_xor   :   alu_fn = `ALU_XOR;
-
-                default     :   alu_fn = `ALU_SUB;
-            endcase
-        end
-
-endmodule
-
-
-// Conditional Branchig Unit. It checks whether the branch is taken or not
-module BRANCH (
-		input [2:0] 	cond,
-		input [31:0] 	R1, R2,
-		output 			taken
-);
-	wire 		zf, cf, vf, sf;
-	wire [31:0] add, op_b;
-	reg 		taken;
-
-	assign op_b         = (~R2);
-    assign {cf, add}    = (R1 + op_b + 1'b1);
-    assign zf           = (add == 0);
-    assign sf           = add[31];
-    assign vf           = (R1[31] ^ (op_b[31]) ^ add[31] ^ cf);
-
-	always @ * begin
-      (* full_case *)
-      case(cond)
-          `BR_BEQ: 	taken = zf;          	// BEQ
-          `BR_BNE: 	taken = ~zf;         	// BNE
-          `BR_BLT: 	taken = (sf != vf);  	// BLT
-          `BR_BGE: 	taken = (sf == vf);  	// BGE
-          `BR_BLTU: taken = (~cf);      	// BLTU
-          `BR_BGEU: taken = (cf);       	// BGEU
-          default: 	taken = 1'b0;
-      endcase
-	end
-endmodule
-
-// Memory data (R) aligner
-module mrdata_align(
-    input wire [31:0] d,
-    output wire [31:0] ed,
-    input wire [1:0] size,
-    input wire [1:0] A,
-    input wire sign
-);
-
-    wire [31:0] s_ext, u_ext;
-    wire [7:0] _byte_;
-    wire [15:0] hword;
-
-    assign _byte_ = 	(A==2'd0) ? d[7:0] :
-                	(A==2'd1) ? d[15:8] :
-                	(A==2'd2) ? d[23:16] : d[31:24];
-
-    assign hword = 	(A[1]==0) ? d[15:0] : d[31:16];
-
-    assign u_ext =  (size==2'd0)  ? {24'd0,_byte_}  :
-                    (size==2'd1)  ? {16'd0,hword} : d;
-
-    assign s_ext =  (size==2'd0)  ? {{24{_byte_[7]}},_byte_}   :
-                    (size==2'd1)  ? {{24{hword[15]}},hword} : d;
-
-    assign ed = sign ? u_ext : s_ext;
-
-endmodule
-
-// Memory data (W) aligner
-module mwdata_align(
-    input wire [31:0] d,
-    output wire [31:0] fd,
-    input wire [1:0] size,
-    input wire [1:0] A
-  );
-
-    wire [7:0] _byte_ = d[7:0];
-    wire [15:0] hword = d[15:0];
-
-    wire [31:0] _byte__word, hw_word;
-
-    assign  _byte__word = (A==2'd0) ? d :
-                        (A==2'd1) ? {16'd0, _byte_, 8'd0} :
-                        (A==2'd2) ? {8'd0, _byte_, 16'd0} : {_byte_, 24'd0} ;
-    assign  hw_word   = (~A[1])  ? d : {hword, 16'd0};
-
-    assign fd = (size==2'd0) ? _byte__word :
-                (size==2'd1) ? hw_word : d;
-
-endmodule
-
-
-// The Instruction Fetch Unit
-module NfiVe32_FU(
-    input wire [31:0]   IDATA0,
-    input wire [31:0]   IDATA1,
-    input wire [31:0]   PC,
-    input wire          C1,
-    output wire [31:0]  INSTR,
-    output wire         IS32
-);
-
-    wire [31:0] instr32;
-    wire [31:0] instr   =   (~C1 & ~PC[1]) ? IDATA0 :                   // Aligned 32 or Lower 16
-                            (~C1 & PC[1]) ? {16'h0, IDATA0[31:16]} :    // Upper 16
-                            {IDATA0[15:0], IDATA1[31:16]} ;             // Unaligned 32
-
-    wire        is32    =   instr[0] & instr[1];
-      
-    RV32_DECOMP nfive_decomp (.IRi(instr[15:0]), .IRo(instr32));
-
-    assign INSTR    =   is32 ? instr : instr32;
-    assign IS32     =   is32;
-
-endmodule
-
-
-// Instruction Execution Unit (ALU + next PC generation)
-module NfiVe32_XU(
-    output wire [31:0]  ALUR,
-    output wire [31:0]  NPC,
-    output wire [31:0]  PC24,
-    output wire [31:0]  PCI,
-    input wire [31:0]   PC,
-    input wire [31:0]   INSTR,
-    input wire [31:0]   R1,
-    input wire [31:0]   R2, 
-    input wire          IS32
-);
-    wire        instr_branch    = 	(INSTR[`IR_opcode] == `OPCODE_Branch);
-	wire        instr_jalr      = 	(INSTR[`IR_opcode] == `OPCODE_JALR);
-	wire        instr_jal       = 	(INSTR[`IR_opcode] == `OPCODE_JAL);
-
-    wire        alu_op2_src;
-
-    wire [31:0] imm;
-    wire [31:0] pc4         = PC + 32'h4;
-    wire [31:0] pc2         = PC + 32'h2;
-    wire [31:0] pci         = PC + imm;
-    wire [31:0] alu_op2     = alu_op2_src ? R2 : imm;
-    wire [4:0]  alu_shamt 	= INSTR[`IR_shamt];
-    wire [3:0]  alu_fn;
-    wire        branch_taken;
-
-    IMMGEN      immgen      (.INSTR(INSTR), .IMM(imm));
-`ifdef	USE_ALU_HC
-	ALU_HC         
-`else
-	ALU
-`endif
-				alu         (.a(R1), .b(alu_op2),.shamt(alu_shamt),.r(ALUR),.alufn(alu_fn));
-	BRANCH      brunint     (.cond(INSTR[`IR_cond]),.R1(R1),.R2(R2),.taken(branch_taken));
-	RV32_DEC    decoder     (.INSTR(INSTR),.alu_fn(alu_fn),.alu_op2_src(alu_op2_src));
-
-    assign NPC = ((branch_taken & instr_branch) | (instr_jal)) ? pci :  (instr_jalr) ? ALUR : IS32 ? pc4 : pc2;
-
-    assign PC24 = IS32 ? pc4 : pc2;
-
-    assign PCI = pci;
-
-endmodule
-
-module NfiVe32_RF (
-	input			HCLK,							// System clock
-	input			WR,
-	input [ 4:0]	RA,
-	input [ 4:0]	RB,
-	input [ 4:0]	RW,
-	input [31:0]	DW, 
-	output [31:0]	DA, 
-	output [31:0]	DB
-);
- 	reg [31:0] RF [31:0];
-
-	assign DA = RF[RA] & {32{~(RA==5'd0)}};
-	assign DB = RF[RB] & {32{~(RB==5'd0)}};
-	
-	always @ (posedge HCLK) 
-		if(WR)
-			if(RW!=5'd0) begin 
-				RF[RW] <= DW;
-				`ifdef DBG
-				#1 $display("Write: RF[%d]=0x%X []", RW, RF[RW]);
-				`endif
-			end
-endmodule
-
-// The CPU Core
-`define 	CYC_C0		2'h0
-`define 	CYC_C1		2'h1
-`define 	CYC_C2		2'h2
-`define 	CYC_C3		2'h3
-
-
-module NfiVe32 (
-	input	HCLK,							// System clock
-	input	HRESETn,						// System Reset, active low
-
-	// AHB-LITE MASTER PORT for Instructions
-	output wire [31:0]  HADDR,				// AHB transaction address
-	output wire [ 2:0]  HSIZE,				// AHB size: _byte_, half-word or word
-	output wire [ 1:0]  HTRANS,				// AHB transfer: non-sequential only
-	output wire [31:0]  HWDATA,				// AHB write-data
-	output wire         HWRITE,				// AHB write control
-	input  wire [31:0]  HRDATA,				// AHB read-data
-	input  wire         HREADY,				// AHB stall signal
-	
-	// MISCELLANEOUS 
-  	input  wire         NMI,				// Non-maskable interrupt input
-  	input  wire         IRQ,				// Interrupt request line
-    input  wire [4:0]   IRQ_NUM,			// Interrupt number from the PIC			
-  	input  wire 	    SYSTICKCLK,			// SYSTICK clock; ON pulse width is one HCLK period
-  	output wire [31:0]	IRQ_MASK
-);
-
-    reg [1:0]   CYC, NCYC;
-    reg         RUN;
-    reg         IS32;
-    reg         INEXCEPTION;
-
-    reg [31:0]  PC;
-	reg [31:0]  PCI;
-	
-    reg [31:0]  IDATA;
-    reg [31:0]  PC24;
-    reg [31:0]  INSTR;
-
-	reg [31:0] ALU_R;
-
-    reg [31:0]  CSR_CYCLE; 
-    reg [31:0]  CSR_INSTRET;
-    reg [31:0]  CSR_TIME;
-    reg [31:0]  CSR_TIMELOAD;
-    reg [31:0]  CSR_MIE;
-    reg [31:0]  CSR_IRQMASK;
- //   reg [31:0]  CSR_MIP;
-    reg [31:0]  CSR_EPC;
-    
-
-    wire [31:0] instr;
-    wire [31:0] hrdata;
-    wire [31:0] hwdata;
-
-    wire [31:0] alur;
-    wire [31:0] npc;
-    wire [31:0] pc24, pci;
-    wire        is32;
-
-    wire        tmr_int;
-
-    wire        unaligned = PC[1] & HRDATA[16] & HRDATA[17];
-
-    wire        C0 = (CYC==2'h0), C1 = (CYC==2'h1), C2 = (CYC==2'h2), C3 = (CYC==2'h3);
-
-    wire        shamt 	    =   INSTR[`IR_shamt];
-
-    wire        instr_i     =   (INSTR[`IR_opcode] == `OPCODE_Arith_I);
-	wire        instr_r     =   (INSTR[`IR_opcode] == `OPCODE_Arith_R);
-    wire        instr_lui   = 	(INSTR[`IR_opcode] == `OPCODE_LUI);
-	wire        instr_auipc = 	(INSTR[`IR_opcode] == `OPCODE_AUIPC);
-	wire        instr_branch = 	(INSTR[`IR_opcode] == `OPCODE_Branch);
-	wire        instr_jalr  = 	(INSTR[`IR_opcode] == `OPCODE_JALR);
-	wire        instr_jal   = 	(INSTR[`IR_opcode] == `OPCODE_JAL);
-    wire        instr_store = 	(INSTR[`IR_opcode] == `OPCODE_Store);
-	wire        instr_load  = 	(INSTR[`IR_opcode] == `OPCODE_Load);
-
-    wire [11:0] csr_num     =   INSTR[`IR_csr]; 
-    wire        instr_priv  =   (INSTR[`IR_opcode] ==  5'h1C);
-    wire	    instr_rdcsr	=	instr_priv & (INSTR[`IR_funct3] == 3'd2);
-    wire        instr_wrcsr =   instr_priv & (INSTR[`IR_funct3] == 3'd1);
-    wire        instr_ecall =   instr_priv & (INSTR[`IR_funct3] == 3'b0) & (csr_num == 12'h0);
-    wire        instr_ebreak=   instr_priv & (INSTR[`IR_funct3] == 3'b0) & (csr_num == 12'h1);
-	wire        instr_mret  =   instr_priv & (INSTR[`IR_funct3] == 3'b0) & (csr_num == 12'h302);
-	wire        instr_wfi   =   instr_priv & (INSTR[`IR_funct3] == 3'b0) & (csr_num == 12'h105);
-           
-    wire        rf_wr       =   instr_load | instr_r | instr_i | instr_jal | instr_jalr | instr_lui | instr_auipc;
-
-    wire        exception   =   (CSR_MIE[0] & ((tmr_int & CSR_MIE[1]) | (IRQ & CSR_MIE[2]))) | NMI | instr_ecall;
-    wire [31:0] pc_ex       =   instr_ecall ?   32'd12              :
-								instr_ebreak?	32'd16				:
-                                NMI         ?   32'd4               :
-                                tmr_int     ?   32'd8               :
-                                IRQ         ?   (32'd64+(IRQ_NUM<<2)) :   32'd60;
-
-
-    assign IRQ_MASK = CSR_IRQMASK;
-
-    // The Register File
-	
-	wire [4:0] rs1 	    = 	INSTR[`IR_rs1];
-	wire [4:0] rs2 	    = 	INSTR[`IR_rs2];
-	wire [4:0] rd 	    = 	INSTR[`IR_rd];
-	wire [31:0] r1, r2;
-	wire [31:0] rf_dw	= 	(instr_jal | instr_jalr)    ?   PC24    : 
-                            (instr_auipc)               ?   PCI     : 
-                            (instr_load)                ?   hrdata  : 
-                            (instr_rdcsr)               ?   csr     :   alur;
-
-`ifdef USE_RF_MODULE
-`ifdef USE_HC_REGF
-	DFFRFile RF (
-		.R1(rs1), .R2(rs2), .RW(rd),
-		.DW(rf_dw),
-		.D1(r1), .D2(r2),
-		.CLK(HCLK),
-		.WE(rf_wr&C3)
-	);
-`else
-	NfiVe32_RF RF (
-		.HCLK(HCLK),
-		.WR(rf_wr & C3),
-		.RA(rs1),
-		.RB(rs2),
-		.RW(rd),
-		.DW(rf_dw),
-		.DA(r1),
-		.DB(r2)
-	);
-`endif
-`ifdef DBG
-	always @(posedge HCLK)
-		if(rd != 5'd0)
-			if(rf_wr & C3) begin
-                $display("RF[%02d]=%X (%d)", rd, rf_dw, rf_dw);
-				if(rd == 10) $display("<===");
-            end
-`endif
-`else
-	reg [31:0] RF[31:0];
-    assign r1 = RF[rs1] & {32{~(rs1==5'd0)}};
-	assign r2 = RF[rs2] & {32{~(rs2==5'd0)}};
-	always @(posedge HCLK)
-		if(rd != 5'd0)
-			if(rf_wr & C3) begin
-                RF[rd] <=   rf_dw;
-				`ifdef DBG
-                #1 $display("Write: RF[%d]=0x%X [PC=0x%X, INSTR=0x%X]", rd, RF[rd], PC, INSTR);
-				`endif
-            end
-`endif
-
-
-
-    wire [31:0] csr =   (csr_num==12'hC00) ? CSR_CYCLE      :
-                        (csr_num==12'hC01) ? CSR_TIME       :
-                        (csr_num==12'hC02) ? CSR_INSTRET    :
-                        (csr_num==12'hC03) ? CSR_TIMELOAD   :   
-                        (csr_num==12'h304) ? CSR_MIE        :   
-                        (csr_num==12'h310) ? CSR_IRQMASK    :   
-                        32'hBAAAAAAD;
-
-	
-    assign HADDR        = ~RUN ? 32'h0 : C3 ? {PC[31:2],2'b0} : C0 ? ({PC[31:2],2'b0}+32'h4) : C2 ? alur : 32'd0;
-    assign HTRANS[0]    = 1'h0;
-    assign HTRANS[1]    = ~RUN | C3 | (C0 & unaligned) | (C2 & (instr_load | instr_store));
-    assign HWRITE       = C2 & instr_store;
-    assign HSIZE        = {1'b0,INSTR[13:12]};
-    assign HWDATA       = (C3 & instr_store) ? hwdata : 32'd0;
-
-    mrdata_align mralign(
-        .d(HRDATA),
-        .ed(hrdata),
-        .size(HSIZE[1:0]),
-        //.A(alur[1:0]),
-		.A(ALU_R[1:0]),
-        .sign(INSTR[14])
-    );
-
-    mwdata_align mwalign(
-        .d(r2),
-        .fd(hwdata),
-        .size(HSIZE[1:0]),
-        .A(alur[1:0])
-    );
-    
-	NfiVe32_FU fetch_unit(
-        .IDATA0(HRDATA),
-        .IDATA1(IDATA),
-        .PC(PC),
-        .C1(C1),
-        .INSTR(instr),
-        .IS32(is32)
-    );
-
-    NfiVe32_XU exec_unit(
-        .ALUR(alur),
-        .NPC(npc),
-        .PC24(pc24),
-        .PCI(pci),
-        .PC(PC),
-        .INSTR(INSTR),
-        .R1(r1),
-        .R2(r2), 
-        .IS32(IS32)
-    );
-
-    // CPU Cycle
-    always @*
-        case (CYC)
-            `CYC_C0:   	if(HREADY) begin
-	            			if(~PC[1]) NCYC = `CYC_C2;                         // Alighed
-	                    	else if(HRDATA[16]&HRDATA[17]) NCYC = `CYC_C1;     // Not aligned and 32-bit instruction
-	                    	else NCYC = `CYC_C2;                               // Not aligned but 16-bit instruction
-                    	end 
-                    	else 
-                    		NCYC = `CYC_C0;
-            
-            `CYC_C1:   	if(HREADY) 
-            				NCYC = `CYC_C2; 
-            			else 
-            				NCYC = `CYC_C1;
-            
-            `CYC_C2:   	NCYC = `CYC_C3;
-            
-            `CYC_C3:   	if(HREADY) 
-            				NCYC = `CYC_C0; 
-            			else 
-            				NCYC = `CYC_C3; 
-            
-            default: 	NCYC = `CYC_C0;
-        
-        endcase
-
-    // The resgisters: 4 x 32 + 2 x 1 + 1 x 2 = 132 Bits
-    // Synthesized into 118 bits only:
-    //  + CYC is expanded from 2 to 4 (OHE FSM)
-    //  + IDATA lower 16 bits are not used -> removed during optimization
-    always @(posedge HCLK or negedge HRESETn)
-		if(!HRESETn) RUN <= 0;
-		else RUN <= 1;
-		/*
-	`SYNC_BEGIN(RUN, 1'h0)
-        //if(~RUN) 
-		RUN <= 1'b1;
-    `SYNC_END
-*/
-    `SYNC_BEGIN(CYC, 2'h0)
-        if(RUN) CYC <= NCYC;
-    `SYNC_END
-    
-    `SYNC_BEGIN(INEXCEPTION, 1'h0)
-        if(exception & C3 & !INEXCEPTION) INEXCEPTION <= 1'h1;
-        else if(instr_mret & C3) INEXCEPTION <= 1'h0;
-    `SYNC_END
-    
-    `SYNC_BEGIN(IDATA, 32'h0)
-        if(C0)    
-            IDATA <= HRDATA; 
-    `SYNC_END
-    /*
-	`SYNC_BEGIN(ALUR, 32'h0)
-        if(C2)    
-            ALUR <= alur; 
-    `SYNC_END
-	*/
-	always @(posedge HCLK or negedge HRESETn)
-		if(!HRESETn) ALU_R <= 0;
-		else if(C2) ALU_R <= alur;
-
-    `SYNC_BEGIN(INSTR, 32'h0)
-        if(C0 | C1)    
-            INSTR <= instr; 
-    `SYNC_END
-    
-    `SYNC_BEGIN(IS32, 1'h0)
-        if(C0 | C1) IS32 <= is32;
-    `SYNC_END
-
-    `SYNC_BEGIN(PC24, 32'h0)
-        if(C2)    
-            PC24 <= pc24; 
-    `SYNC_END
-    
-	`SYNC_BEGIN(PCI, 32'h0)
-        if(C2)    
-            PCI <= pci; 
-    `SYNC_END
-
-    `SYNC_BEGIN(PC, 32'h0)
-        if(C2 & instr_mret)
-            PC <= CSR_EPC;
-        else if(C2 & exception & !INEXCEPTION)
-            PC <= pc_ex;
-        else if(C2)    
-            PC <= npc; 
-		//#1 $display ("PC=%x", PC);
-    `SYNC_END
-
-    // Counters and Special function Registers (CSRs)
-    // Retired Instruction
-    `SYNC_BEGIN(CSR_INSTRET, 32'h0)
-        if(C3)    
-            CSR_INSTRET <= CSR_INSTRET + 32'h1;
-    `SYNC_END
-
-    // Number of CPU cycles
-    `SYNC_BEGIN(CSR_CYCLE, 32'h0)   
-            if(RUN) CSR_CYCLE <= CSR_CYCLE + 32'h1;
-    `SYNC_END
-
-    // SYSTICK Timer
-    wire    csr_time_zero   =   (CSR_TIME == 32'h0);
-    assign  tmr_int         =   csr_time_zero;
-
-    `SYNC_BEGIN(CSR_TIME, 32'hFFFF_FFFF)   
-        if(SYSTICKCLK)
-            if(csr_time_zero)
-                CSR_TIME <= CSR_TIMELOAD;
-            else 
-                CSR_TIME <= CSR_TIME - 32'h1;
-    `SYNC_END
-
-    // SYSTICK TimeLoad register
-    `SYNC_BEGIN(CSR_TIMELOAD, 32'hFFFF_FFFF)   
-        if(instr_wrcsr & (csr_num == 12'hC03))
-            CSR_TIMELOAD <= r1;
-    `SYNC_END
-
-    // Non Standard Machine Interrupt Enable CSR
-    // Bit 0: Global Int En
-    // Bit 1: Timer Int En
-    // Bit 2: External Int En
-    `SYNC_BEGIN(CSR_MIE, 32'h0)   
-        if(instr_wrcsr & (csr_num == 12'h304))
-            CSR_MIE <= r1;
-    `SYNC_END
-
-	// Non standard IRQ MASK CSR    
-    `SYNC_BEGIN(CSR_IRQMASK, 32'h0)   
-        if(instr_wrcsr & (csr_num == 12'h310))
-            CSR_IRQMASK <= r1;
-    `SYNC_END
-
-    // Exception PC CSR
-    `SYNC_BEGIN(CSR_EPC, 32'h0)   
-        if(exception & C2 & !INEXCEPTION)
-            CSR_EPC <= npc;
-    `SYNC_END
-
-endmodule
-
-// A very simple Programmable Interrupts Controller
-module NfiVe32_PIC(
-  input  wire [31:0]	IRQ,
-  output reg 			irq,
-  output wire [4:0]		IRQ_NUM,
-  input  wire [31:0]	IRQ_MASK
-);
-
-	reg  [4:0]		irq_num;
-
-	assign IRQ_NUM = irq_num;
-
-	integer i;
-	always @ * begin
-	irq = 0;
-	irq_num = 0;
-	for(i=0; i<32; i=i+1)
-	    if(IRQ_MASK[i] & IRQ[i]) begin
-	        irq = 1'b1;
-	        irq_num = i;
-	    end
-	end
-
-endmodule
-
-/* 
-	NfiVe Top Level Integration 
-	NfiVe CPU + PIC + SYSTICK 
-*/
-module NfiVe32_SYS (
-	input	HCLK,							// System clock
-	input	HRESETn,						// System Reset, active low
-
-	// AHB-LITE MASTER PORT for Instructions
-	output wire [31:0]  HADDR,				// AHB transaction address
-	output wire [ 2:0]  HSIZE,				// AHB size: _byte_, half-word or word
-	output wire [ 1:0]  HTRANS,				// AHB transfer: non-sequential only
-	output wire [31:0]  HWDATA,				// AHB write-data
-	output wire         HWRITE,				// AHB write control
-	input  wire [31:0]  HRDATA,				// AHB read-data
-	input  wire         HREADY,				// AHB stall signal
-	
-	// MISCELLANEOUS 
-  	input  wire         NMI,				// Non-maskable interrupt input
-  	input  wire [31:0] 	IRQ,				// 32 IRQ Line
-  	input  wire [7:0]	SYSTICKCLKDIV		
-);
-
-	wire irq;
-	wire [4:0] 	irq_num;
-	wire [31:0] irq_mask;
-	//wire [31:0] IRQ;
-	wire div;
-	reg  [7:0]  clkdiv;
-	reg 		systickclk;
-
-	NfiVe32 N5(
-		.HCLK(HCLK),
-		.HRESETn(HRESETn),
-
-		// AHB-LITE MASTER PORT for Instructions and Data
-		.HADDR(HADDR),             
-		.HSIZE(HSIZE),             
-		.HTRANS(HTRANS),           
-		.HWDATA(HWDATA),           
-		.HWRITE(HWRITE),           
-		.HRDATA(HRDATA),           
-		.HREADY(HREADY),           
-		
-		// MISCELLANEOUS 
-	  	.NMI(NMI),               
-	  	.IRQ(irq),
-	  	.IRQ_NUM(irq_num),               
-	  	.SYSTICKCLK(systickclk),
-	  	.IRQ_MASK(irq_mask)
-	);
-
-	NfiVe32_PIC PIC(
-  		.IRQ(IRQ),
-  		.irq(irq),
-  		.IRQ_NUM(irq_num),
-  		.IRQ_MASK(irq_mask)
-	);
-
-	assign div = (clkdiv == SYSTICKCLKDIV);
-
-	`SYNC_BEGIN(clkdiv, 8'b0)
-		if(div) 
-				clkdiv <= 8'h0;
-			else
-				clkdiv <= clkdiv + 8'h1; 
-	`SYNC_END
-	
-	`SYNC_BEGIN(systickclk, 1'b0)
-		if(div) 
-				systickclk <= 1'b1;
-			else
-				systickclk <= 1'b0;	 
-	`SYNC_END
-
-endmodule

diff --git a/verilog/rtl/user_project/rtl/acc/AHB_SPM.v b/verilog/rtl/user_project/rtl/acc/AHB_SPM.v
deleted file mode 100644
index 10cafdb..0000000
--- a/verilog/rtl/user_project/rtl/acc/AHB_SPM.v
+++ /dev/null

@@ -1,267 +0,0 @@
-module TCMP(clk, rst, a, s);
-    input clk, rst;
-    input a;
-    output reg s;
-
-    reg z;
-
-    always @(posedge clk  or posedge rst) begin
-        if (rst) begin
-            //Reset logic goes here.
-            s <= 1'b0;
-            z <= 1'b0;
-        end
-        else begin
-            //Sequential logic goes here.
-            z <= a | z;
-            s <= a ^ z;
-        end
-    end
-endmodule
-
-module CSADD(clk, rst, x, y, sum);
-    input clk, rst;
-    input x, y;
-    output reg sum;
-
-    reg sc;
-
-    // Half Adders logic
-    wire hsum1, hco1;
-    assign hsum1 = y ^ sc;
-    assign hco1 = y & sc;
-
-    wire hsum2, hco2;
-    assign hsum2 = x ^ hsum1;
-    assign hco2 = x & hsum1;
-
-    always @(posedge clk or posedge rst) begin
-        if (rst) begin
-            //Reset logic goes here.
-            sum <= 1'b0;
-            sc <= 1'b0;
-        end
-        else begin
-            //Sequential logic goes here.
-            sum <= hsum2;
-            sc <= hco1 ^ hco2;
-        end
-    end
-endmodule
-
-module SPM(clk, rst, x, y, p);
-    parameter size = 32;
-    input clk, rst;
-    input y;
-    input[size-1:0] x;
-    output p;
-
-    wire[size-1:1] pp;
-    wire[size-1:0] xy;
-
-    genvar i;
-
-    CSADD csa0 (.clk(clk), .rst(rst), .x(x[0]&y), .y(pp[1]), .sum(p));
-    generate for(i=1; i<size-1; i=i+1) begin
-        CSADD csa (.clk(clk), .rst(rst), .x(x[i]&y), .y(pp[i+1]), .sum(pp[i]));
-    end endgenerate
-    TCMP tcmp (.clk(clk), .rst(rst), .a(x[size-1]&y), .s(pp[size-1]));
-
-endmodule
-
-module AHB_SPM #(parameter SIZE=32) (
-    input  wire         HCLK,      
-    input  wire         HRESETn,   
-    input  wire         HSEL,      
-    input  wire         HREADY,    
-    input  wire [1:0]   HTRANS,    
-    input  wire [2:0]   HSIZE,     
-    input  wire         HWRITE,    
-    input  wire [31:0]  HADDR,     
-    input  wire [31:0]  HWDATA,    
-    output wire         HREADYOUT, 
-    output wire [1:0]   HRESP,
-    output wire [31:0]  HRDATA
-);
-
-    localparam  X_OFF = 0, Y_OFF = 4, P1_OFF = 8, P2_OFF = 12;
-    localparam  S0=0, S1=1, S2=2, S3=3;
-
-    reg [7:0]   AHB_ADDR;    
-    wire        ahb_access   = HTRANS[1] & HSEL & HREADY;
-    wire        ahb_write    = ahb_access &  HWRITE;
-    wire        ahb_read     = ahb_access & (~HWRITE);
-    reg         AHB_WRITE;
-    reg         AHB_READ;
-
-    wire        p;
-    reg [31:0]  X, Y, P0, P1; 
-    reg [7:0]   CNT, ncnt;
-
-    reg [3:0]   STATE, nstate;
-
-    always @(posedge HCLK or negedge HRESETn)
-    if(~HRESETn) begin
-        AHB_WRITE   <=  1'b0;
-        AHB_READ    <=  1'b0;
-        AHB_ADDR    <=  8'b0;
-    end
-    else begin
-        AHB_WRITE   <=  ahb_write;
-        AHB_READ    <=  ahb_read;
-        AHB_ADDR    <=  HADDR[7:0];  
-    end
-
-    always @(posedge HCLK or negedge HRESETn)
-        if(~HRESETn)
-            X  <= 32'b0;
-        else if(AHB_WRITE && (AHB_ADDR == X_OFF))
-            X <= HWDATA;
-
-    always @(posedge HCLK or negedge HRESETn)
-        if(~HRESETn)
-            Y  <= 32'b0;
-        else if(AHB_WRITE && (AHB_ADDR == Y_OFF))
-            Y <= HWDATA;
-        else if(STATE==S1) Y <= Y >> 1;
-
-    always @(posedge HCLK or negedge HRESETn)
-        if(~HRESETn)
-            P0  <= 32'b0;
-        else if(STATE==S1)
-            P0 <= {p,P0[31:1]};
-
-    always @(posedge HCLK or negedge HRESETn)
-        if(~HRESETn)
-            STATE  <= S0;
-        else 
-            STATE <= nstate;
-
-    always @*
-        case(STATE)
-            S0: if(AHB_WRITE && (AHB_ADDR == Y_OFF)) nstate=S1; else nstate=S0;
-            S1: if(CNT==31) nstate=S0; else nstate=S1;
-        endcase
-    
-    always @(posedge HCLK or negedge HRESETn)
-        if(~HRESETn)
-            CNT  <= 8'd0;
-        else 
-            CNT <= ncnt;
-
-    always @* begin
-        ncnt = 0;
-        if(CNT==31) ncnt <= 0;
-        else if(STATE==S1) ncnt=CNT+1;
-    end
-
-    SPM spm(
-      .clk(~HCLK),
-      .rst(~HRESETn),
-      .x(X),
-      .y(Y[0]),
-      .p(p)
-    );
-
-    assign HREADYOUT = (STATE == S0);
-
-    assign HRDATA = P0;
-
-endmodule
-/*
-module SPM_EXT(clk, rst, X, Y, P, start, done);
-    parameter size = 32;
-    input clk, rst;
-    input [size-1:0] X, Y;
-    output reg [size-1:0] P;
-    output done;
-    input start;
-
-    reg [31:0] Y_reg;
-    wire p, y;
-    assign y=Y_reg[0];
-    reg [1:0] done_state, done_state_next;
-
-    assign done = done_state[1];
-    SPM spm(
-      .clk(clk),
-      .rst(rst),
-      .x(X),
-      .y(y),
-      .p(p));
-
-    reg [7:0] count;
-
-    always @(posedge clk or posedge rst)
-      if(rst) count <= 7'd0;
-      else if(start) count <= count + 1'd1;
-      else if(done) count <= 7'd0;
-
-    always@(posedge clk)
-      if(count==0 && start==1) P<= 64'b0;
-      else if(!done) P <= {p, P[31:1]};
-
-    always@(posedge clk or posedge rst)
-      if(rst) Y_reg <= 0;
-      else if(count==0 && start==1) Y_reg<= Y;
-      else if(!done) Y_reg <= (Y_reg>>1);
-
-    always @(posedge clk or posedge rst)
-      if(rst) done_state <= 2'd00;
-      else done_state <= done_state_next;
-
-    always @* begin
-        done_state_next = done_state;
-      case (done_state)
-        2'b00: if(start) done_state_next = 2'b01;
-        2'b01: if(count==8'd33) done_state_next = 2'b10;
-        2'b10: done_state_next = 2'b11;
-        2'b11: done_state_next = 2'b00;
-        default: done_state_next = done_state;
-      endcase
-    end
-      //else if(count==7'd33) done <= 1;
-      //else if(start) done <= 0;
-
-endmodule
-*/
-/*
-module spm_tb;
-reg clk, rst, start;
-wire p;
-
-
-wire done;
-
-initial begin
-  rst = 0;
-  clk = 0;
-
-  start = 0;
-  #100;
-  rst = 1;
-  #500;
-  rst = 0;
-  #1000;
-  @(posedge clk);
-  start = 1;
-  @(posedge done);
-  start = 0;
-end
-
-always #10 clk = ~clk;
-
-initial begin
-  $dumpfile("spm.vcd");
-  $dumpvars(0);
-  #100_000 ;
-  $display("Timeout -- Exiting");
-  $finish;
-end
-
-wire [31:0] P;
-
-SPM_EXT spm_dut(.clk(clk), .rst(rst), .X(-15), .Y(20), .P(P), .start(start), .done(done));
-
-endmodule
-*/

diff --git a/verilog/rtl/user_project/rtl/soc_core.v b/verilog/rtl/user_project/rtl/soc_core.v
deleted file mode 100644
index bc70016..0000000
--- a/verilog/rtl/user_project/rtl/soc_core.v
+++ /dev/null

@@ -1,224 +0,0 @@
-
-`default_nettype none
-`timescale 1ns/1ns
-
-module soc_core (
-`ifdef USE_POWER_PINS
-	input VPWR,
-	input VGND,
-`endif
-	input HCLK, 
-	input HRESETn,
-	
-	input wire 			NMI,
-	input wire [7:0]	SYSTICKCLKDIV,
-
-	input wire [3: 0] 	fdi_Sys0_S0,
-	output wire [3: 0] 	fdo_Sys0_S0,
-	output wire [0: 0] 	fdoe_Sys0_S0,
-	output wire [0: 0] 	fsclk_Sys0_S0,
-	output wire [0: 0] 	fcen_Sys0_S0,
-
-	input wire [15: 0] GPIOIN_Sys0_S2,
-	output wire [15: 0] GPIOOUT_Sys0_S2,
-	output wire [15: 0] GPIOPU_Sys0_S2,
-	output wire [15: 0] GPIOPD_Sys0_S2,
-	output wire [15: 0] GPIOOEN_Sys0_S2,
-
-	input wire [0: 0] RsRx_Sys0_SS0_S0,
-	output wire [0: 0] RsTx_Sys0_SS0_S0,
-
-	input wire [0: 0] RsRx_Sys0_SS0_S1,
-	output wire [0: 0] RsTx_Sys0_SS0_S1,
-
-	input wire [0: 0] MSI_Sys0_SS0_S2,
-	output wire [0: 0] MSO_Sys0_SS0_S2,
-	output wire [0: 0] SSn_Sys0_SS0_S2,
-	output wire [0: 0] SCLK_Sys0_SS0_S2,
-	input wire [0: 0] MSI_Sys0_SS0_S3,
-	output wire [0: 0] MSO_Sys0_SS0_S3,
-	output wire [0: 0] SSn_Sys0_SS0_S3,
-	output wire [0: 0] SCLK_Sys0_SS0_S3,
-	input wire [0: 0] scl_i_Sys0_SS0_S4,
-	output wire [0: 0] scl_o_Sys0_SS0_S4,
-	output wire [0: 0] scl_oen_o_Sys0_SS0_S4,
-	input wire [0: 0] sda_i_Sys0_SS0_S4,
-	output wire [0: 0] sda_o_Sys0_SS0_S4,
-	output wire [0: 0] sda_oen_o_Sys0_SS0_S4,
-
-	input wire [0: 0] scl_i_Sys0_SS0_S5,
-	output wire [0: 0] scl_o_Sys0_SS0_S5,
-	output wire [0: 0] scl_oen_o_Sys0_SS0_S5,
-	input wire [0: 0] sda_i_Sys0_SS0_S5,
-	output wire [0: 0] sda_o_Sys0_SS0_S5,
-	output wire [0: 0] sda_oen_o_Sys0_SS0_S5,
-
-	output wire [0: 0] pwm_Sys0_SS0_S6,
-	output wire [0: 0] pwm_Sys0_SS0_S7
-);
-
-	wire [31: 0] HADDR_Sys0;
-	wire [31: 0] HWDATA_Sys0;
-	wire HWRITE_Sys0;
-	wire [1: 0] HTRANS_Sys0;
-	wire [2:0] HSIZE_Sys0;
-
-	wire HREADY_Sys0;
-	wire [31: 0] HRDATA_Sys0;
-
-	wire [31: 0] SRAMRDATA_Sys0_S1;
-	wire [3: 0] SRAMWEN_Sys0_S1;
-	wire [31: 0] SRAMWDATA_Sys0_S1;
-	wire [0: 0] SRAMCS0_Sys0_S1;
-	wire [11: 0] SRAMADDR_Sys0_S1;
-
-	// AHB LITE Master2 Signals
-	wire [31:0] M2_HADDR;
-	wire [0:0] M2_HREADY;
-	wire [0:0] M2_HWRITE;
-	wire [1:0] M2_HTRANS;
-	wire [2:0] M2_HSIZE;
-	wire [31:0] M2_HWDATA;
-	wire [31:0] M2_HRDATA;
-	
-	wire [31: 0] M2_IRQ;
-
-	wire [3:0] M2_HPROT;
-	wire [2:0] M2_HBURST;
-	wire M2_HBUSREQ;
-	wire M2_HLOCK;
-	wire M2_HGRANT;
-
-	wire [31:0] SRAMRDATA0, SRAMRDATA1, SRAMRDATA2; 
-
-	assign M2_HREADY = HREADY_Sys0; 
-	assign M2_HRDATA = HRDATA_Sys0;
-
-	assign HADDR_Sys0 = M2_HADDR; 
-	assign HWDATA_Sys0 = M2_HWDATA; 
-	assign HWRITE_Sys0 = M2_HWRITE; 
-	assign HTRANS_Sys0 = M2_HTRANS; 
-	assign HSIZE_Sys0 = M2_HSIZE;
-	assign M2_HGRANT = 1'b1;
-	assign M2_HBUSREQ = 1'b1;
-
-
-	//AHBlite_SYS0 instantiation
-	AHBlite_sys_0 ahb_sys_0_uut(
-
-		.HCLK(HCLK),
-		.HRESETn(HRESETn),
-         
-		.HADDR(HADDR_Sys0),
-		.HWDATA(HWDATA_Sys0),
-		.HWRITE(HWRITE_Sys0),
-		.HTRANS(HTRANS_Sys0),
-		.HSIZE(HSIZE_Sys0),
-    
-		.HREADY(HREADY_Sys0),
-		.HRDATA(HRDATA_Sys0),
-		
-		// QSPI Interface
-		.fdi_S0(fdi_Sys0_S0),
-		.fdo_S0(fdo_Sys0_S0),
-		.fdoe_S0(fdoe_Sys0_S0),
-		.fsclk_S0(fsclk_Sys0_S0),
-		.fcen_S0(fcen_Sys0_S0),
-
-		// SRAM Interface
-		.SRAMRDATA_S1(SRAMRDATA_Sys0_S1),
-		.SRAMWEN_S1(SRAMWEN_Sys0_S1),
-		.SRAMWDATA_S1(SRAMWDATA_Sys0_S1),
-		.SRAMCS0_S1(SRAMCS0_Sys0_S1),
-		.SRAMADDR_S1(SRAMADDR_Sys0_S1),
-
-		// GPIO Interface
-		.GPIOIN_S2(GPIOIN_Sys0_S2),
-		.GPIOOUT_S2(GPIOOUT_Sys0_S2),
-		.GPIOPU_S2(GPIOPU_Sys0_S2),
-		.GPIOPD_S2(GPIOPD_Sys0_S2),
-		.GPIOOEN_S2(GPIOOEN_Sys0_S2),
-		
-		// APB Bus
-		// UART 0
-		.RsRx_SS0_S0(RsRx_Sys0_SS0_S0),
-		.RsTx_SS0_S0(RsTx_Sys0_SS0_S0),
-		
-		// UART 1
-		.RsRx_SS0_S1(RsRx_Sys0_SS0_S1),
-		.RsTx_SS0_S1(RsTx_Sys0_SS0_S1),
-
-		// SPI 0 Interface
-		.MSI_SS0_S2(MSI_Sys0_SS0_S2),
-		.MSO_SS0_S2(MSO_Sys0_SS0_S2),
-		.SSn_SS0_S2(SSn_Sys0_SS0_S2),
-		.SCLK_SS0_S2(SCLK_Sys0_SS0_S2),
-
-		// SPI 1 Interface
-		.MSI_SS0_S3(MSI_Sys0_SS0_S3),
-		.MSO_SS0_S3(MSO_Sys0_SS0_S3),
-		.SSn_SS0_S3(SSn_Sys0_SS0_S3),
-		.SCLK_SS0_S3(SCLK_Sys0_SS0_S3),
-
-		// I2C 0 Interface
-		.scl_i_SS0_S4(scl_i_Sys0_SS0_S4),
-		.scl_o_SS0_S4(scl_o_Sys0_SS0_S4),
-		.scl_oen_o_SS0_S4(scl_oen_o_Sys0_SS0_S4),
-		.sda_i_SS0_S4(sda_i_Sys0_SS0_S4),
-		.sda_o_SS0_S4(sda_o_Sys0_SS0_S4),
-		.sda_oen_o_SS0_S4(sda_oen_o_Sys0_SS0_S4),
-
-		// I2C 1 Interface
-		.scl_i_SS0_S5(scl_i_Sys0_SS0_S5),
-		.scl_o_SS0_S5(scl_o_Sys0_SS0_S5),
-		.scl_oen_o_SS0_S5(scl_oen_o_Sys0_SS0_S5),
-		.sda_i_SS0_S5(sda_i_Sys0_SS0_S5),
-		.sda_o_SS0_S5(sda_o_Sys0_SS0_S5),
-		.sda_oen_o_SS0_S5(sda_oen_o_Sys0_SS0_S5),
-
-		// PMW 0 & 1 Interfaces
-		.pwm_SS0_S6(pwm_Sys0_SS0_S6),
-		.pwm_SS0_S7(pwm_Sys0_SS0_S7),
-
-		.IRQ(M2_IRQ)
-
-	);
-
-
-	RAM_3Kx32 RAM (
-	`ifdef USE_POWER_PINS
-		.VPWR(VPWR),
-		.VGND(VGND),
-	`endif
-		.CLK(HCLK),
-		.WE(SRAMWEN_Sys0_S1),
-		.EN(SRAMCS0_Sys0_S1),
-		.Di(SRAMWDATA_Sys0_S1),
-		.Do(SRAMRDATA_Sys0_S1),
-		.A(SRAMADDR_Sys0_S1[11:0])
-	);
-
-	// Instantiation of NfiVe32
-	NfiVe32_SYS CPU (
-		.HCLK(HCLK),
-		.HRESETn(HRESETn),
-
-		.HADDR(M2_HADDR),
-		.HREADY(M2_HREADY),
-		.HWRITE(M2_HWRITE),
-		.HTRANS(M2_HTRANS),
-		.HSIZE(M2_HSIZE),
-		.HWDATA(M2_HWDATA),
-		.HRDATA(M2_HRDATA),
-
-		//NMI
-		.NMI(NMI),
-
-		//Interrupts
-		.IRQ(M2_IRQ),
-
-		// SYSTICK Divisor
-		.SYSTICKCLKDIV(SYSTICKCLKDIV)
-	);
-  endmodule
-  

diff --git a/verilog/rtl/user_project/rtl/user_project_wrapper.v b/verilog/rtl/user_project/rtl/user_project_wrapper.v
deleted file mode 100644
index 863412a..0000000
--- a/verilog/rtl/user_project/rtl/user_project_wrapper.v
+++ /dev/null

@@ -1,183 +0,0 @@
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_project_wrapper
- *
- * This wrapper enumerates all of the pins available to the
- * user for the user project.
- *
- * An example user project is provided in this wrapper.  The
- * example should be removed and replaced with the actual
- * user project.
- *
- *-------------------------------------------------------------
- */
-
-`define MPRJ_IO_PADS 38
-
-module user_project_wrapper (
-`ifdef USE_POWER_PINS
-    inout vdda1,	// User area 1 3.3V supply
-    inout vdda2,	// User area 2 3.3V supply
-    inout vssa1,	// User area 1 analog ground
-    inout vssa2,	// User area 2 analog ground
-    inout vccd1,	// User area 1 1.8V supply
-    inout vccd2,	// User area 2 1.8v supply
-    inout vssd1,	// User area 1 digital ground
-    inout vssd2,	// User area 2 digital ground
-`endif
-
-    // Wishbone Slave ports (WB MI A)
-    input wb_clk_i,
-    input wb_rst_i,
-    input wbs_stb_i,
-    input wbs_cyc_i,
-    input wbs_we_i,
-    input [3:0] wbs_sel_i,
-    input [31:0] wbs_dat_i,
-    input [31:0] wbs_adr_i,
-    output wbs_ack_o,
-    output [31:0] wbs_dat_o,
-
-    // Logic Analyzer Signals
-    input  [127:0] la_data_in,
-    output [127:0] la_data_out,
-    input  [127:0] la_oen,
-
-    // IOs
-    input  [`MPRJ_IO_PADS-1:0] io_in,
-    output [`MPRJ_IO_PADS-1:0] io_out,
-    output [`MPRJ_IO_PADS-1:0] io_oeb,
-
-    // Analog (direct connection to GPIO pad---use with caution)
-    // Note that analog I/O is not available on the 7 lowest-numbered
-    // GPIO pads, and so the analog_io indexing is offset from the
-    // GPIO indexing by 7.
-    inout [`MPRJ_IO_PADS-8:0] analog_io,
-
-    // Independent clock (on independent integer divider)
-    input   user_clock2
-);
-
-    /*
-        Caravel IO   | N5           |  Mode  
-        
-        io[13:0]     | GPIO         | Bi-directional
-        io[17:14]    | flash        | Bi-directional
-        io[18]       | flash clk    | Output
-        io[19]       | flash enable | Output
-
-        io[20]       | UART0 RX      | Input
-        io[21]       | UART0 TX      | Output
-
-        io[22]       | UART1 RX      | Input
-        io[23]       | UART1 TX      | Output
-
-        io[24]       | SPI0 I       | Input
-        io[25]       | SPI0 O       | Output
-        io[26]       | SPI0 SSn     | Output
-        io[27]       | SPI0 CLK     | Output
-
-        io[28]       | SPI1 I       | Input
-        io[29]       | SPI1 O       | Output
-        io[30]       | SPI1 SSn     | Output
-        io[31]       | SPI1 CLK     | Output
-
-        io[32]       | I2C0 IO      | Bi-directional
-        io[33]       | I2C0 IO      | Bi-directional
-
-        io[34]       | I2C1 IO      | Bi-directional
-        io[35]       | I2C1 IO      | Bi-directional
-
-        io[36]       |  pwm0        | Output
-        io[37]       |  pwm1        | Output
-    */
-
-    assign io_oeb[18] = 1'b0; 
-    assign io_oeb[19] = 1'b0; 
-
-    assign io_oeb[20] = 1'b1; 
-    assign io_oeb[21] = 1'b0; 
-    assign io_oeb[22] = 1'b1; 
-    assign io_oeb[23] = 1'b0; 
-
-    assign io_oeb[24] = 1'b1; 
-    assign io_oeb[25] = 1'b0; 
-    assign io_oeb[26] = 1'b0; 
-    assign io_oeb[27] = 1'b0; 
-
-    assign io_oeb[28] = 1'b1; 
-    assign io_oeb[29] = 1'b0; 
-    assign io_oeb[30] = 1'b0; 
-    assign io_oeb[31] = 1'b0; 
-
-    assign io_oeb[30] = 1'b0; 
-    assign io_oeb[31] = 1'b0; 
-
-    // check csb pin -- io[3]
-    wire fdoeb;
-    
-    assign io_oeb[17:14] = {4{~fdoeb}};
-
-    soc_core core(
-    `ifdef USE_POWER_PINS
-        .VPWR(vccd1),
-        .VGND(vssd1)
-    `endif
-
-        .HCLK(wb_clk_i), 
-	    .HRESETn(~wb_rst_i),
-	    
-        .NMI(la_data_in[8]),
-	    .SYSTICKCLKDIV(la_data_in[7:0]),
-
-        .GPIOIN_Sys0_S2(io_in[13:0]),
-        .GPIOOUT_Sys0_S2(io_out[13:0]),
-	    .GPIOPU_Sys0_S2(),
-	    .GPIOPD_Sys0_S2(),
-	    .GPIOOEN_Sys0_S2(io_oeb[13:0]),
-
-	    .fdi_Sys0_S0(io_in[17:14]),
-	    .fdo_Sys0_S0(io_out[17:14]),
-		.fdoe_Sys0_S0(fdoeb),
-        .fsclk_Sys0_S0(io_out[18]),
-	    .fcen_Sys0_S0(io_out[19]),
-		
-	    .RsRx_Sys0_SS0_S0(io_in[20]),
-        .RsTx_Sys0_SS0_S0(io_out[21]),
-
-        .RsRx_Sys0_SS0_S1(io_in[22]),
-        .RsTx_Sys0_SS0_S1(io_out[23]),
-
-        .MSI_Sys0_SS0_S2(io_in[24]),
-        .MSO_Sys0_SS0_S2(io_out[25]),
-        .SSn_Sys0_SS0_S2(io_out[26]),
-        .SCLK_Sys0_SS0_S2(io_out[27]),
-
-        .MSI_Sys0_SS0_S3(io_in[28]),
-        .MSO_Sys0_SS0_S3(io_out[29]),
-        .SSn_Sys0_SS0_S3(io_out[30]),
-        .SCLK_Sys0_SS0_S3(io_out[31]),
-
-        .scl_i_Sys0_SS0_S4(io_in[32]),
-        .scl_o_Sys0_SS0_S4(io_out[32]),
-        .scl_oen_o_Sys0_SS0_S4(io_oeb[32]),
-        .sda_i_Sys0_SS0_S4(io_in[33]),
-        .sda_o_Sys0_SS0_S4(io_out[33]),
-        .sda_oen_o_Sys0_SS0_S4(io_oeb[33]),
-
-        .scl_i_Sys0_SS0_S5(io_in[34]),
-        .scl_o_Sys0_SS0_S5(io_out[34]),
-        .scl_oen_o_Sys0_SS0_S5(io_oeb[34]),
-        .sda_i_Sys0_SS0_S5(io_in[35]),
-        .sda_o_Sys0_SS0_S5(io_out[35]),
-        .sda_oen_o_Sys0_SS0_S5(io_oeb[35]),
-
-        .pwm_Sys0_SS0_S6(io_out[36]),
-        .pwm_Sys0_SS0_S7(io_out[37])
-    );
-   
-
-endmodule	// user_project_wrapper
-`default_nettype wire

diff --git a/verilog/rtl/user_project/soc_core.v b/verilog/rtl/user_project/soc_core.v
index 115fc2c..a750994 100644
--- a/verilog/rtl/user_project/soc_core.v
+++ b/verilog/rtl/user_project/soc_core.v

@@ -3,6 +3,10 @@
 `timescale 1ns/1ns
 
 module soc_core (
+`ifdef USE_POWER_PINS
+	input VPWR,
+	input VGND,
+`endif
 	input HCLK, 
 	input HRESETn,
 	
@@ -180,8 +184,11 @@
 
 	);
 
-
 	RAM_3Kx32 RAM (
+	`ifdef USE_POWER_PINS
+		.VPWR(VPWR),
+		.VGND(VGND),
+	`endif
 		.CLK(HCLK),
 		.WE(SRAMWEN_Sys0_S1),
 		.EN(SRAMCS0_Sys0_S1),