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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-021 / 3e968450d5f49805454fa8f29e99f4c668a5830c / . / verilog / rtl / fwpayload / fwrisc / ve / fwrisc_rv32imc / sim / tests
tree: e1b69c29df829cf657a272c7b2e1df32ec461f30 [path history] [tgz]
  1. fwrisc_instr_tests_arith_add.f
  2. fwrisc_instr_tests_arith_addi.f
  3. fwrisc_instr_tests_arith_addi_neg.f
  4. fwrisc_instr_tests_arith_and.f
  5. fwrisc_instr_tests_arith_andi.f
  6. fwrisc_instr_tests_arith_or.f
  7. fwrisc_instr_tests_arith_ori.f
  8. fwrisc_instr_tests_arith_sll.f
  9. fwrisc_instr_tests_arith_slli.f
  10. fwrisc_instr_tests_arith_slt_f.f
  11. fwrisc_instr_tests_arith_slt_t_neg.f
  12. fwrisc_instr_tests_arith_slt_t_pos.f
  13. fwrisc_instr_tests_arith_slti_f.f
  14. fwrisc_instr_tests_arith_slti_t.f
  15. fwrisc_instr_tests_arith_sltu_t.f
  16. fwrisc_instr_tests_arith_sra.f
  17. fwrisc_instr_tests_arith_srai.f
  18. fwrisc_instr_tests_arith_srl.f
  19. fwrisc_instr_tests_arith_srli.f
  20. fwrisc_instr_tests_arith_sub.f
  21. fwrisc_instr_tests_arith_xor.f
  22. fwrisc_instr_tests_arith_xori.f
  23. fwrisc_instr_tests_branch_beq_f_back.f
  24. fwrisc_instr_tests_branch_beq_f_fwd.f
  25. fwrisc_instr_tests_branch_beq_t_back.f
  26. fwrisc_instr_tests_branch_beq_t_fwd.f
  27. fwrisc_instr_tests_branch_bge_eq_t_neg.f
  28. fwrisc_instr_tests_branch_bge_eq_t_pos.f
  29. fwrisc_instr_tests_branch_bge_gt_t_neg.f
  30. fwrisc_instr_tests_branch_bge_gt_t_pos.f
  31. fwrisc_instr_tests_branch_blt_t_neg.f
  32. fwrisc_instr_tests_branch_blt_t_pos.f
  33. fwrisc_instr_tests_branch_bltu_t_neg.f
  34. fwrisc_instr_tests_branch_bltu_t_pos.f
  35. fwrisc_instr_tests_branch_bne_f_back.f
  36. fwrisc_instr_tests_branch_bne_f_fwd.f
  37. fwrisc_instr_tests_branch_bne_t_back.f
  38. fwrisc_instr_tests_branch_bne_t_fwd.f
  39. fwrisc_instr_tests_counters_cycle.f
  40. fwrisc_instr_tests_exception_bne.f
  41. fwrisc_instr_tests_exception_dep_x.f
  42. fwrisc_instr_tests_exception_j.f
  43. fwrisc_instr_tests_exception_jalr.f
  44. fwrisc_instr_tests_exception_lw.f
  45. fwrisc_instr_tests_jump_j.f
  46. fwrisc_instr_tests_jump_jal.f
  47. fwrisc_instr_tests_jump_jalr.f
  48. fwrisc_instr_tests_jump_jalr_off_neg.f
  49. fwrisc_instr_tests_jump_jalr_off_pos.f
  50. fwrisc_instr_tests_ldst_lb.f
  51. fwrisc_instr_tests_ldst_lb_s.f
  52. fwrisc_instr_tests_ldst_lb_u.f
  53. fwrisc_instr_tests_ldst_lbu_s.f
  54. fwrisc_instr_tests_ldst_lh_s.f
  55. fwrisc_instr_tests_ldst_lh_u.f
  56. fwrisc_instr_tests_ldst_lhu_s.f
  57. fwrisc_instr_tests_ldst_lw.f
  58. fwrisc_instr_tests_ldst_sb_lw.f
  59. fwrisc_instr_tests_ldst_sh_lw.f
  60. fwrisc_instr_tests_ldst_sw_lw.f
  61. fwrisc_instr_tests_long_loop.f
  62. fwrisc_instr_tests_lui.f
  63. fwrisc_instr_tests_system_csrc.f
  64. fwrisc_instr_tests_system_csrr.f
  65. fwrisc_instr_tests_system_csrs.f
  66. fwrisc_instr_tests_system_csrsi.f
  67. fwrisc_instr_tests_system_csrw.f
  68. fwrisc_instr_tests_system_csrw_csrr.f
  69. fwrisc_instr_tests_system_ecall.f
  70. fwrisc_instr_tests_system_eret.f
  71. fwrisc_ripe_1.f
  72. fwrisc_ripe_2.f
  73. fwrisc_ripe_3.f
  74. fwrisc_ripe_4.f
  75. fwrisc_ripe_5.f
  76. fwrisc_riscv_compliance_rv32i_I-ADD-01.f
  77. fwrisc_riscv_compliance_rv32i_I-ADDI-01.f
  78. fwrisc_riscv_compliance_rv32i_I-AND-01.f
  79. fwrisc_riscv_compliance_rv32i_I-ANDI-01.f
  80. fwrisc_riscv_compliance_rv32i_I-AUIPC-01.f
  81. fwrisc_riscv_compliance_rv32i_I-BEQ-01.f
  82. fwrisc_riscv_compliance_rv32i_I-BGE-01.f
  83. fwrisc_riscv_compliance_rv32i_I-BGEU-01.f
  84. fwrisc_riscv_compliance_rv32i_I-BLT-01.f
  85. fwrisc_riscv_compliance_rv32i_I-BLTU-01.f
  86. fwrisc_riscv_compliance_rv32i_I-BNE-01.f
  87. fwrisc_riscv_compliance_rv32i_I-CSRRC-01.f
  88. fwrisc_riscv_compliance_rv32i_I-CSRRCI-01.f
  89. fwrisc_riscv_compliance_rv32i_I-CSRRS-01.f
  90. fwrisc_riscv_compliance_rv32i_I-CSRRSI-01.f
  91. fwrisc_riscv_compliance_rv32i_I-CSRRW-01.f
  92. fwrisc_riscv_compliance_rv32i_I-CSRRWI-01.f
  93. fwrisc_riscv_compliance_rv32i_I-DELAY_SLOTS-01.f
  94. fwrisc_riscv_compliance_rv32i_I-EBREAK-01.f
  95. fwrisc_riscv_compliance_rv32i_I-ECALL-01.f
  96. fwrisc_riscv_compliance_rv32i_I-ENDIANESS-01.f
  97. fwrisc_riscv_compliance_rv32i_I-FENCE.f
  98. fwrisc_riscv_compliance_rv32i_I-IO.f
  99. fwrisc_riscv_compliance_rv32i_I-JAL-01.f
  100. fwrisc_riscv_compliance_rv32i_I-JALR-01.f
  101. fwrisc_riscv_compliance_rv32i_I-LB-01.f
  102. fwrisc_riscv_compliance_rv32i_I-LBU-01.f
  103. fwrisc_riscv_compliance_rv32i_I-LH-01.f
  104. fwrisc_riscv_compliance_rv32i_I-LHU-01.f
  105. fwrisc_riscv_compliance_rv32i_I-LUI-01.f
  106. fwrisc_riscv_compliance_rv32i_I-LW-01.f
  107. fwrisc_riscv_compliance_rv32i_I-MISALIGN_JMP-01.f
  108. fwrisc_riscv_compliance_rv32i_I-MISALIGN_LDST-01.f
  109. fwrisc_riscv_compliance_rv32i_I-NOP-01.f
  110. fwrisc_riscv_compliance_rv32i_I-OR-01.f
  111. fwrisc_riscv_compliance_rv32i_I-ORI-01.f
  112. fwrisc_riscv_compliance_rv32i_I-RF_size-01.f
  113. fwrisc_riscv_compliance_rv32i_I-RF_width-01.f
  114. fwrisc_riscv_compliance_rv32i_I-RF_x0-01.f
  115. fwrisc_riscv_compliance_rv32i_I-SB-01.f
  116. fwrisc_riscv_compliance_rv32i_I-SH-01.f
  117. fwrisc_riscv_compliance_rv32i_I-SLL-01.f
  118. fwrisc_riscv_compliance_rv32i_I-SLLI-01.f
  119. fwrisc_riscv_compliance_rv32i_I-SLT-01.f
  120. fwrisc_riscv_compliance_rv32i_I-SLTI-01.f
  121. fwrisc_riscv_compliance_rv32i_I-SLTIU-01.f
  122. fwrisc_riscv_compliance_rv32i_I-SLTU-01.f
  123. fwrisc_riscv_compliance_rv32i_I-SRA-01.f
  124. fwrisc_riscv_compliance_rv32i_I-SRAI-01.f
  125. fwrisc_riscv_compliance_rv32i_I-SRL-01.f
  126. fwrisc_riscv_compliance_rv32i_I-SRLI-01.f
  127. fwrisc_riscv_compliance_rv32i_I-SUB-01.f
  128. fwrisc_riscv_compliance_rv32i_I-SW-01.f
  129. fwrisc_riscv_compliance_rv32i_I-XOR-01.f
  130. fwrisc_riscv_compliance_rv32i_I-XORI-01.f
  131. fwrisc_zephyr_dhrystone.f
  132. fwrisc_zephyr_hello_world.f
  133. fwrisc_zephyr_philosophers.f
  134. fwrisc_zephyr_synchronization.f