verilog/rtl/fwpayload/fwrisc/ve/fwrisc_rv32imc/sim/tests/fwrisc_riscv_compliance_rv32i_I-AND-01.f

+SW_IMAGE=${BUILD_DIR}/esw/I-AND-01.elf
+REF_FILE=${PACKAGES_DIR}/riscv-compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output
+gtest-filter=riscv_compliance_tests.runtest
+hpi.entry=fwrisc_tests.riscv_compliance_main