- f8268c9 Revised the user_id_programming layout to have contact areas over by Tim Edwards · 4 years, 3 months ago
- 9074da5 Move simple_por views to the correct locations by Ahmed Ghazy · 4 years, 4 months ago
- 8e13c5a Removed the original test padframe with redistribution layer tests; by Tim Edwards · 4 years, 4 months ago
- bc7f531 Minor updates to simple_por layout after checking DRC against Calibre. by Tim Edwards · 4 years, 4 months ago
- 6aea300 Update user_project_wrapper_empty by Ahmed Ghazy · 4 years, 4 months ago
- 740defb [DATA] WIP mgmt_core rehardening by agorararmard · 4 years, 4 months ago
- 8b742b8 [DATA] reharden DFFRAM with the updated RTL by agorararmard · 4 years, 4 months ago
- 48f1adb [DATA] reharden digital pll by agorararmard · 4 years, 4 months ago
- 4ff45b1 Corrected the simple_por layout to avoid overlapping the capacitor by Tim Edwards · 4 years, 4 months ago
- 499896a [DATA] Update signal-routed version of caravel by Ahmed Ghazy · 4 years, 4 months ago
- a4367b3 Update wrapper, add obstructed version by Ahmed Ghazy · 4 years, 4 months ago
- fc7bd3c Update wrapper with power rings & obstructions by Ahmed Ghazy · 4 years, 4 months ago
- 365f5d7 Add a final user_id_programming by Ahmed Ghazy · 4 years, 4 months ago
- bd9efb0 Merge branch 'master' into develop by Ahmed Ghazy · 4 years, 4 months ago
- 5b3db63 Merge pull request #8 from ax3ghazy/new_dimensions by ax3ghazy · 4 years, 4 months ago
- 678b0dd [DATA] re-compress data using the latest Makefile by Ahmed Ghazy · 4 years, 4 months ago
- 0252f54 Update Makefile again to use the GDSes directly by Ahmed Ghazy · 4 years, 4 months ago
- 923a4fe [DATA] LVS clean chip_io & messy routed caravel by Ahmed Ghazy · 4 years, 4 months ago
- 1feaa10 Finished implementation of the simple_por Power-on-reset circuit. Completed DRC and LVS, by Tim Edwards · 4 years, 4 months ago
- 963a343 Revised the POR layout, which includes making use of the updated parameterized by Tim Edwards · 4 years, 4 months ago
- 4f6036f Did most of the floorplanning work on the POR circuit; only needs routing. by Tim Edwards · 4 years, 4 months ago
- 581068f Corrected the mess caused by introducing default_nettype none into the design by Tim Edwards · 4 years, 4 months ago
- efdc529 Add default target to "load" user design on caravel by Ahmed Ghazy · 4 years, 4 months ago
- 10b5b0c [DATA] Push updated views as per the latest pad frame dimensions by Ahmed Ghazy · 4 years, 4 months ago
- 2fa4b03 Add caravel floorplan with a preliminary seal ring by Ahmed Ghazy · 4 years, 4 months ago
- d4cc669 [DATA] Add full runs of almost all blocks by Ahmed Ghazy · 4 years, 4 months ago
- 72e52c6 Added what can be pushed of chip_io by Ahmed Ghazy · 4 years, 5 months ago
- 6b6803f Add a sample user project wrapper by Ahmed Ghazy · 4 years, 5 months ago
- 7be29a2 Made a number of modifications to the counter-timer to correctly pipeline by Tim Edwards · 4 years, 5 months ago
- 60aeb5f Added a placeholder padframe layout, and added an almost-complete by Tim Edwards · 4 years, 5 months ago
- b86fc84 (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 5 months ago
- 65a3487 delete not nedded files by shalan · 4 years, 7 months ago
- 33de054 populated the project with data subfolders. by mkk · 4 years, 7 months ago
