| commit | 7be29a266da74341620f61e18fad447dae7b0547 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Sun Oct 25 21:50:19 2020 -0400 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Wed Oct 28 22:58:29 2020 +0200 |
| tree | b3522b9c13a0ce0c747f0ae3b8538568ede7a06c | |
| parent | 14d35ac952caec3f6ff1a06b25a22cbef70d526d [diff] |
Made a number of modifications to the counter-timer to correctly pipeline the 64-bit counter, including synchronizing the enables. There are still two issues, one of which causes the testbench to fail, which have not been solved.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)
This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
