| commit | d4cc669e6b40d8f170c2674fe18ae0f43093f0c3 | [log] [tgz] |
|---|---|---|
| author | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Fri Nov 13 22:34:42 2020 +0200 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Fri Nov 13 22:34:42 2020 +0200 |
| tree | 1c9ff4bffdb735ba07406dd99f9daa339647560f | |
| parent | 5898e4ab3b990eb9909f0311770b605159c10f34 [diff] |
[DATA] Add full runs of almost all blocks - Blocks that are to be hand-designed currently have a dummy layout (a box with pins) - This should be sufficient to reproduce/access the current chip floorplan. Top-level routing is a work-in-progress.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)
This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
