small cleanup and generate vcd file for test005
diff --git a/ol_templates/Makefile b/ol_templates/Makefile
index 2b5cb01..a6af696 100644
--- a/ol_templates/Makefile
+++ b/ol_templates/Makefile
@@ -31,7 +31,7 @@
@echo
@echo " overwritting user_proj_example with 16x16 block"
@echo
- cp config_block.tcl ../openlane/user_proj_example/config.tcl
+ cp config_block_flat.tcl ../openlane/user_proj_example/config.tcl
cp pin_order.cfg ../openlane/user_proj_example/pin_order.cfg
.PHONY: init_block_cells
@@ -43,8 +43,8 @@
@echo
@echo " overwritting user_proj_example with 16x16 block using black box cells"
@echo
- cp config_block2.tcl ../openlane/user_proj_example/config.tcl
- cp pdn.tcl ../openlane/user_proj_example/pdn.tcl
+ cp config_block_cells.tcl ../openlane/user_proj_example/config.tcl
+ cp pdn_cells.tcl ../openlane/user_proj_example/pdn.tcl
cp pin_order.cfg ../openlane/user_proj_example/pin_order.cfg
@echo
@echo " creating new macro_placement.cfg file"
diff --git a/ol_templates/config_block2.tcl b/ol_templates/config_block_cells.tcl
similarity index 99%
rename from ol_templates/config_block2.tcl
rename to ol_templates/config_block_cells.tcl
index 93ff8f3..71e84d1 100644
--- a/ol_templates/config_block2.tcl
+++ b/ol_templates/config_block_cells.tcl
@@ -30,7 +30,6 @@
#set ::env(FP_PDN_HPITCH) "153.18"
set ::env(FP_PDN_HPITCH) "76.59"
-
set ::env(FP_IO_VTHICKNESS_MULT) 4
set ::env(FP_IO_HTHICKNESS_MULT) 4
diff --git a/ol_templates/config_block.tcl b/ol_templates/config_block_flat.tcl
similarity index 100%
rename from ol_templates/config_block.tcl
rename to ol_templates/config_block_flat.tcl
diff --git a/ol_templates/pdn.tcl b/ol_templates/pdn_cells.tcl
similarity index 100%
rename from ol_templates/pdn.tcl
rename to ol_templates/pdn_cells.tcl
diff --git a/verilog/morphle/ycell.v b/verilog/morphle/ycell.v
index d81f5d2..420482b 100644
--- a/verilog/morphle/ycell.v
+++ b/verilog/morphle/ycell.v
@@ -45,8 +45,9 @@
wire inval =| in; // in != `Vempty;
wire lmatchval =| lmatch; // lmatch != `Vempty;
wire matchval =| match; // match != `Vempty;
-
- wire clear = reset | (lmempty & linval & ~inval);
+
+ wire clear;
+ assign #1 clear = reset | (lmempty & linval & ~inval);
wire [1:0] clear2 = {clear,clear};
// two bit latches
diff --git a/verilog/mtests/test001ycfsm.v b/verilog/mtests/test001ycfsm.v
index c689dba..454550f 100644
--- a/verilog/mtests/test001ycfsm.v
+++ b/verilog/mtests/test001ycfsm.v
@@ -57,7 +57,7 @@
in,DUT.lin,DUT.nlin,DUT.inval,DUT.linval,,
match,DUT.lmatch,DUT.nlmatch,DUT.matchval,DUT.lmatchval,,
DUT.clear2,DUT.lmempty,DUT.nlmempty);
- $dumpfile("test.vcd");
+ $dumpfile("test001.vcd");
$dumpvars;
end
diff --git a/verilog/mtests/test005upblock.v b/verilog/mtests/test005upblock.v
index f627a56..0bcc561 100644
--- a/verilog/mtests/test005upblock.v
+++ b/verilog/mtests/test005upblock.v
@@ -111,9 +111,15 @@
.io_out(io_out),
.io_oeb(io_oeb)
);
+
+ wire reset = la_data_in[113];
+
+ wire [2:0] cfg [0:15][0:15];
initial
begin
+ $dumpfile("test005.vcd");
+ $dumpvars;
$readmemh("test005.tv", testvectors); // Read vectors
vectornum= 0; errors = 0; // Initialize
end
@@ -127,12 +133,9 @@
$display("%d tests completed with %d errors", vectornum-1, errors);
$finish; // End simulation
end
- end
-
- wire reset = la_data_in[113];
+ end
- wire [2:0] cfg [0:15][0:15];
-
+ //outside generate row and col must be constant, so this handles that limitation
genvar row, col;
generate
for (row = 0; row < 16; row = row + 1) begin : vertical
