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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-007 / e6eda804fa840f8ccb66a5af2188044e5c23731b / . / verilog / dv / caravel / defs.h
blob: 20a426c69aa5fe53c10f47ad4076cfcd1ce17193 [file] [log] [blame]
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]1#ifndef _STRIVE_H_
2#define _STRIVE_H_
3
4#include <stdint.h>
5#include <stdbool.h>
6
7// a pointer to this is a null pointer, but the compiler does not
8// know that because "sram" is a linker symbol from sections.lds.
9extern uint32_t sram;
10
11// Pointer to firmware flash routines
12extern uint32_t flashio_worker_begin;
13extern uint32_t flashio_worker_end;
14
Manar14d35ac2020-10-21 22:47:15 +0200[diff] [blame]15// SYNTH_MEM (0x0100_0000)
16#define reg_synth_mem (*(volatile uint32_t*)0x01000000)
17
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]18// UART (0x2000_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]19#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
20#define reg_uart_data (*(volatile uint32_t*)0x20000004)
Tim Edwardsca2f3182020-10-06 10:05:11 -0400[diff] [blame]21#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]22
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]23// GPIO (0x2100_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]24#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
25#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
26#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
27#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
28
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]29// Logic Analyzer (0x2200_0000)
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]30#define reg_la0_data (*(volatile uint32_t*)0x25000000)
31#define reg_la1_data (*(volatile uint32_t*)0x25000004)
32#define reg_la2_data (*(volatile uint32_t*)0x25000008)
33#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]34
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]35#define reg_la0_ena (*(volatile uint32_t*)0x25000010)
36#define reg_la1_ena (*(volatile uint32_t*)0x25000014)
37#define reg_la2_ena (*(volatile uint32_t*)0x25000018)
38#define reg_la3_ena (*(volatile uint32_t*)0x2500001c)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]39
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]40// Mega Project Control (0x2300_0000)
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]41#define reg_mprj_datal (*(volatile uint32_t*)0x26000000)
42#define reg_mprj_datah (*(volatile uint32_t*)0x26000004)
43#define reg_mprj_xfer (*(volatile uint32_t*)0x26000008)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]44
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]45#define reg_mprj_io_0 (*(volatile uint32_t*)0x2600000c)
46#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000010)
47#define reg_mprj_io_2 (*(volatile uint32_t*)0x26000014)
48#define reg_mprj_io_3 (*(volatile uint32_t*)0x26000018)
49#define reg_mprj_io_4 (*(volatile uint32_t*)0x2600001c)
50#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000020)
51#define reg_mprj_io_6 (*(volatile uint32_t*)0x26000024)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]52
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]53#define reg_mprj_io_7 (*(volatile uint32_t*)0x26000028)
54#define reg_mprj_io_8 (*(volatile uint32_t*)0x2600002c)
55#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000030)
56#define reg_mprj_io_10 (*(volatile uint32_t*)0x26000034)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]57
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]58#define reg_mprj_io_11 (*(volatile uint32_t*)0x26000038)
59#define reg_mprj_io_12 (*(volatile uint32_t*)0x2600003c)
60#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000040)
61#define reg_mprj_io_14 (*(volatile uint32_t*)0x26000044)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]62
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]63#define reg_mprj_io_15 (*(volatile uint32_t*)0x26000048)
64#define reg_mprj_io_16 (*(volatile uint32_t*)0x2600004c)
65#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000050)
66#define reg_mprj_io_18 (*(volatile uint32_t*)0x26000054)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]67
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]68#define reg_mprj_io_19 (*(volatile uint32_t*)0x26000058)
69#define reg_mprj_io_20 (*(volatile uint32_t*)0x2600005c)
70#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000060)
71#define reg_mprj_io_22 (*(volatile uint32_t*)0x26000064)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]72
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]73#define reg_mprj_io_23 (*(volatile uint32_t*)0x26000068)
74#define reg_mprj_io_24 (*(volatile uint32_t*)0x2600006c)
75#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000070)
76#define reg_mprj_io_26 (*(volatile uint32_t*)0x26000074)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]77
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]78#define reg_mprj_io_27 (*(volatile uint32_t*)0x26000078)
79#define reg_mprj_io_28 (*(volatile uint32_t*)0x2600007c)
80#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000080)
81#define reg_mprj_io_30 (*(volatile uint32_t*)0x26000084)
82#define reg_mprj_io_31 (*(volatile uint32_t*)0x26000088)
83
84#define reg_mprj_io_32 (*(volatile uint32_t*)0x2600008c)
85#define reg_mprj_io_33 (*(volatile uint32_t*)0x26000090)
86#define reg_mprj_io_34 (*(volatile uint32_t*)0x26000094)
87#define reg_mprj_io_35 (*(volatile uint32_t*)0x26000098)
88#define reg_mprj_io_36 (*(volatile uint32_t*)0x2600009c)
Tim Edwardsb6dd1522020-10-19 15:58:25 -0400[diff] [blame]89#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000a0)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]90
91// Mega Project Slaves (0x3000_0000)
92#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
93
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]94// Flash Control SPI Configuration (2D00_0000)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]95#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]96
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]97// Counter-Timer 0 Configuration
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]98#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
99#define reg_timer0_value (*(volatile uint32_t*)0x22000004)
100#define reg_timer0_data (*(volatile uint32_t*)0x22000008)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]101
102// Counter-Timer 1 Configuration
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]103#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
104#define reg_timer1_value (*(volatile uint32_t*)0x23000004)
105#define reg_timer1_data (*(volatile uint32_t*)0x23000008)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]106
107// SPI Master Configuration
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]108#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
109#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]110
111// System Area (0x2F00_0000)
Tim Edwards32d05422020-10-19 19:43:52 -0400[diff] [blame]112#define reg_clk1_out_dest (*(volatile uint32_t*)0x2F000000)
113#define reg_clk2_out_dest (*(volatile uint32_t*)0x2F000004)
114#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
115#define reg_irq7_source (*(volatile uint32_t*)0x2F00000C)
116#define reg_irq8_source (*(volatile uint32_t*)0x2F000010)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]117
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]118// Crossbar Slave Addresses (0x8000_0000 - 0xB000_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]119#define qspi_ctrl_slave (*(volatile uint32_t*)0x80000000)
120#define storage_area_slave (*(volatile uint32_t*)0x90000000)
121#define mega_any_slave1 (*(volatile uint32_t*)0xA0000000)
122#define mega_any_slave2 (*(volatile uint32_t*)0xB0000000)
123
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]124// Useful GPIO mode values
125#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
126#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
127#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
Tim Edwardsf51dd082020-10-05 16:30:24 -0400[diff] [blame]128#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]129
130#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
131#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
132#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
Tim Edwardsf51dd082020-10-05 16:30:24 -0400[diff] [blame]133#define GPIO_MODE_USER_STD_OUTPUT 0x1808
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]134
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]135// --------------------------------------------------------
136#endif