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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / 1a6ece5b30050a7f50e605dfcee80c0a01363672 / . / sky130 / magic / sky130.tech
blob: 0458e9ef376102ad1477172660395ea6a5bcc54a [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]25 description "SkyWater SKY130: Open Source rules and DRC"
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]26 requires magic-8.3.111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]34# Status 1/3/21: Taking out of beta and declaring an official release.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]35#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]36
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]37#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]38# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]39#------------------------------------------------------------------------
40# device name magic ID layer description
41#------------------------------------------------------------------------
42# sky130_fd_pr__nfet_01v8 nfet standard nFET
43# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]44# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
45# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]46# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]47# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]48# sky130_fd_pr__pfet_01v8 pfet standard pFET
49# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]50# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]51# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
52# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
53# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
54# sky130_fd_pr__nfet_03v3_nvt --- native nFET
55# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
56# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
57# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
60# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]61# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
62# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]63# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
64# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]65# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]66# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]67# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]68# sky130_fd_pr__pnp_05v0 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]69# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
70# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
71# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]72# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]75# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
76# sky130_fd_pr__res_generic_po npres n+ poly resistor
77# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
78# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
79# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
80# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
81# sky130_fd_pr__cap_var mvvaractor thickox varactor
82# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]83# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
84# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]85#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]86# (*) Note that ppres may extract into some generic type called
87# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
88# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]89#
90# (**) nFET and pFET in standard cells are the same as devices
91# outside of the standard cell except for the DRC rule for
92# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
93#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]94#-------------------------------------------------------------
95# The following devices are not extracted but are represented
96# only by script-generated subcells in the PDK.
97#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]98# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]100# sky130_fd_pr__special_nfet_pass_flash flash nFET device
101# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
102# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
103# sky130_fd_pr__cap_vpp_* Vpp cap
104# sky130_fd_pr__ind_* inductor
105# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]106#--------------------------------------------------------------
107
108#-----------------------------------------------------
109# Tile planes
110#-----------------------------------------------------
111
112planes
113 dwell,dw
114 well,w
115 active,a
116 locali,li1,li
117 metal1,m1
118 metal2,m2
119 metal3,m3
120#ifdef METAL5
121#ifdef MIM
122 cap1,c1
123#endif (MIM)
124 metal4,m4
125#ifdef MIM
126 cap2,c2
127#endif (MIM)
128 metal5,m5
129#endif (METAL5)
130#ifdef REDISTRIBUTION
131 metali,mi
132#endif
133 block,b
134 comment,c
135end
136
137#-----------------------------------------------------
138# Tile types
139#-----------------------------------------------------
140
141types
142# Deep nwell
143 dwell dnwell,dnw
144
145# Wells
146 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]147 well pwell,pw
148 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]149 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]150 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]151 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]152
153# Transistors
154 active nmos,ntransistor,nfet
155 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]156 -active npd,npdfet,sramnfet
157 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]158 active pmos,ptransistor,pfet
159 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]160 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]161 -active ppu,ppufet,srampfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]162 active nnmos,nntransistor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]163 active mvnmos,mvntransistor,mvnfet
164 active mvpmos,mvptransistor,mvpfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]165 active mvnnmos,mvnntransistor,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]166 -active mvnmosesd,mvntransistoresd,mvnfetesd
167 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]168 active varactor,varact,var
169 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]170
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]171 active pmoslvt,pfetlvt
172 active pmosmvt,pfetmvt
173 active pmoshvt,pfethvt
174 active nmoslvt,nfetlvt
175 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]176 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]177 -active sramnvar,corenvar,corenvaractor
178 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]179
180# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]181 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]182 active ndiff,ndiffusion,ndif
183 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]184 active mvndiff,mvndiffusion,mvndif
185 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]186 active ndiffc,ndcontact,ndc
187 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]188 active mvndiffc,mvndcontact,mvndc
189 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]190 active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
191 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
192 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
193 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
194 active psubdiffcont,psubstratepcontact,psc,ptapc
195 active nsubdiffcont,nsubstratencontact,nsc,ntapc
196 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
197 active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]198 -active obsactive
199 -active mvobsactive
200
201# Poly
202 active poly,p,polysilicon
203 active polycont,pc,pcontact,polycut,polyc
204 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]205 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]206
207# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]208 active npolyres,npres,mrp1
209 active ppolyres,ppres,xhrpoly
210 active xpolyres,xpres,xres,uhrpoly
211 active ndiffres,rnd,rdn,rndiff
212 active pdiffres,rpd,rdp,rpdiff
213 active mvndiffres,mvrnd,mvrdn,mvrndiff
214 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
215 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]216
217# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]218 active pdiode,pdi
219 active ndiode,ndi
220 active nndiode,nndi
221 active pdiodec,pdic
222 active ndiodec,ndic
223 active nndiodec,nndic
224 active mvpdiode,mvpdi
225 active mvndiode,mvndi
226 active mvpdiodec,mvpdic
227 active mvndiodec,mvndic
228 active pdiodelvt,pdilvt
229 active pdiodehvt,pdihvt
230 active ndiodelvt,ndilvt
231 active pdiodelvtc,pdilvtc
232 active pdiodehvtc,pdihvtc
233 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]234
235# Local Interconnect
236 locali locali,li1,li
237 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]238 locali rlocali,rli1,rli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]239 locali viali,vial,mcon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]240 -locali obsli1,obsli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]241 -locali obsli1c,obsmcon
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]242 -locali lifill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]243
244# Metal 1
245 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]246 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]247 metal1 via1,m2contact,m2cut,m2c,via,v,v1
248 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]249 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]250 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]251
252# Metal 2
253 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]254 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]255 metal2 via2,m3contact,m3cut,m3c,v2
256 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]257 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]258
259# Metal 3
260 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]261 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]262 -metal3 obsm3
263#ifdef METAL5
264 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]265 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]266
267#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]268 cap1 mimcap,mim,capm
269 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]270#endif
271
272# Metal 4
273 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]274 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]275 -metal4 obsm4
276 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]277 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]278
279#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]280 cap2 mimcap2,mim2,capm2
281 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]282#endif
283
284# Metal 5
285 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]286 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]287 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]288 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]289#endif (METAL5)
290
291#ifdef REDISTRIBUTION
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]292 metal5 mrdlcontact,mrdlc
293 metali metalrdl,mrdl,metrdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]294 -metali obsmrdl
295#endif (REDISTRIBUTION)
296
297# Miscellaneous
298 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]299 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]300 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]301 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]302# fixed resistor width identifiers
303 -comment res0p35
304 -comment res0p69
305 -comment res1p41
306 -comment res2p85
307 -comment res5p73
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]308
309end
310
311#-----------------------------------------------------
312# Magic contact types
313#-----------------------------------------------------
314
315contact
316 pc poly locali
317 ndc ndiff locali
318 pdc pdiff locali
319 nsc nsd locali
320 psc psd locali
321 ndic ndiode locali
322 ndilvtc ndiodelvt locali
323 nndic nndiode locali
324 pdic pdiode locali
325 pdilvtc pdiodelvt locali
326 pdihvtc pdiodehvt locali
327 xpc xpc locali
328
329 mvndc mvndiff locali
330 mvpdc mvpdiff locali
331 mvnsc mvnsd locali
332 mvpsc mvpsd locali
333 mvndic mvndiode locali
334 mvpdic mvpdiode locali
335
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]336 mcon locali metal1
337 obsmcon obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]338
339 via1 metal1 metal2
340 via2 metal2 metal3
341#ifdef METAL5
342 via3 metal3 metal4
343 via4 metal4 metal5
344#endif (METAL5)
345 stackable
346
347#ifdef METAL5
348#ifdef MIM
349 # MiM cap contacts are not stackable!
350 mimcc mimcap metal4
351 mim2cc mimcap2 metal5
352#endif (MIM)
353
354 padl m1 m2 m3 m4 m5 glass
355#else
356 padl m1 m2 m3 glass
357#endif (!METAL5)
358
359#ifdef REDISTRIBUTION
360 mrdlc metal5 mrdl
361#endif (REDISTRIBUTION)
362end
363
364#-----------------------------------------------------
365# Layer aliases
366#-----------------------------------------------------
367
368aliases
369
370 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]371 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]372
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]373 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nfetlvt,nsonos
374 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]375 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]376 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]377 allfetsspecial scnfet,scpfet,scpfethvt
378 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]379 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]380
381 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
382 allnactive allnactivenonfet,allnfets
383 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]384 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]385
386 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
387 allpactive allpactivenonfet,allpfets
388 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]389 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]390
391 allactivenonfet allnactivenonfet,allpactivenonfet
392 allactive allactivenonfet,allfets
393
394 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
395
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]396 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]397 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]398 alldifflv allndifflv,allpdifflv
399 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
400 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
401 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
402
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]403 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet
404 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]405 alldiffmv allndiffmv,allpdiffmv
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]406 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet
407 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]408 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
409 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
410 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
411 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
412
413 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]414 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]415
416 allpolyres mrp1,xhrpoly,uhrpoly,rmp
417 allpolynonfet *poly,allpolyres,xpc
418 allpolynonres *poly,allfets,xpc
419
420 allpoly allpolynonfet,allfets
421 allpolynoncap *poly,xpc,allfets,allpolyres
422
423 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
424 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
425 allndiffcontmv mvndc,mvnsc,mvndic
426 allpdiffcontmv mvpdc,mvpsc,mvpdic
427 allndiffcont allndiffcontlv,allndiffcontmv
428 allpdiffcont allpdiffcontlv,allpdiffcontmv
429 alldiffcontlv allndiffcontlv,allpdiffcontlv
430 alldiffcontmv allndiffcontmv,allpdiffcontmv
431 alldiffcont alldiffcontlv,alldiffcontmv
432
433 allcont alldiffcont,pc
434
435 allres allpolyres,allactiveres
436
437 allli *locali,coreli,rli
438 allm1 *m1,rm1
439 allm2 *m2,rm2
440 allm3 *m3,rm3
441#ifdef METAL5
442 allm4 *m4,rm4
443 allm5 *m5,rm5
444#endif (METAL5)
445
446 allpad padl
447
448 psub pwell
449
450end
451
452#-----------------------------------------------------
453# Layer drawing styles
454#-----------------------------------------------------
455
456styles
457 styletype mos
458 dnwell cwell
459 nwell nwell
460 pwell pwell
461 rpwell pwell ptransistor_stripes
462 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]463 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]464 pdiff pdiffusion
465 nsd ndiff_in_nwell
466 psd pdiff_in_pwell
467 nfet ntransistor ntransistor_stripes
468 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]469 npass ntransistor ntransistor_stripes
470 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]471 pfet ptransistor ptransistor_stripes
472 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]473 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]474 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]475 var polysilicon ndiff_in_nwell
476 ndc ndiffusion metal1 contact_X'es
477 pdc pdiffusion metal1 contact_X'es
478 nsc ndiff_in_nwell metal1 contact_X'es
479 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]480 corenvar polysilicon ndiff_in_nwell
481 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]482
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]483 pnp nwell ntransistor_stripes
484 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]485
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]486 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]487 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]488 pfethvt ptransistor ptransistor_stripes implant2
489 nfetlvt ntransistor ntransistor_stripes implant1
490 nsonos ntransistor implant3
491 varhvt polysilicon ndiff_in_nwell implant2
492
493 mvndiff ndiffusion hvndiff_mask
494 mvpdiff pdiffusion hvpdiff_mask
495 mvnsd ndiff_in_nwell hvndiff_mask
496 mvpsd pdiff_in_pwell hvpdiff_mask
497 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]498 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]499 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
500 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]501 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]502 mvvar polysilicon ndiff_in_nwell hvndiff_mask
503 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
504 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
505 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
506 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
507
508 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]509 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]510 pc polysilicon metal1 contact_X'es
511 npolyres polysilicon silicide_block nselect2
512 ppolyres polysilicon silicide_block pselect2
513 xpc polysilicon pselect2 metal1 contact_X'es
514 rmp polysilicon poly_resist_stripes
515
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]516 res0p35 implant1
517 res0p69 implant1
518 res1p41 implant1
519 res2p85 implant1
520 res5p73 implant1
521
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]522 pdiode pdiffusion pselect2
523 ndiode ndiffusion nselect2
524 pdiodec pdiffusion pselect2 metal1 contact_X'es
525 ndiodec ndiffusion nselect2 metal1 contact_X'es
526
527 nndiode ndiffusion nselect2 implant3
528 ndiodelvt ndiffusion nselect2 implant1
529 pdiodelvt pdiffusion pselect2 implant1
530 pdiodehvt pdiffusion pselect2 implant2
531 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
532 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
533 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
534
535 mvpdiode pdiffusion pselect2 hvpdiff_mask
536 mvndiode ndiffusion nselect2 hvndiff_mask
537 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
538 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
539 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
540
541 locali metal1
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]542 lifill metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]543 coreli metal1
544 rli metal1 poly_resist_stripes
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]545 mcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]546 obsli metal1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]547 obsmcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]548
549 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]550 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]551 rm1 metal2 poly_resist_stripes
552 obsm1 metal2
553 m2c metal2 metal3 via2arrow
554 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]555 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]556 rm2 metal3 poly_resist_stripes
557 obsm2 metal3
558 m3c metal3 metal4 via3alt
559 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]560 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]561 rm3 metal4 poly_resist_stripes
562 obsm3 metal4
563#ifdef METAL5
564#ifdef MIM
565 mimcap metal3 mems
566 mimcc metal3 contact_X'es mems
567 mimcap2 metal4 mems
568 mim2cc metal4 contact_X'es mems
569#endif (MIM)
570 via3 metal4 metal5 via4
571 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]572 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]573 rm4 metal5 poly_resist_stripes
574 obsm4 metal5
575 via4 metal5 metal6 via5
576 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]577 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]578 rm5 metal6 poly_resist_stripes
579 obsm5 metal6
580#endif (METAL5)
581#ifdef REDISTRIBUTION
582 mrdlc metal6 metal7 via6
583 metalrdl metal7
584 obsmrdl metal7
585#endif (REDISTRIBUTION)
586
587 glass overglass
588 mrp1 poly_resist poly_resist_stripes
589 xhrpoly poly_resist silicide_block
590 uhrpoly poly_resist
591 ndiffres ndiffusion ndop_stripes
592 pdiffres pdiffusion pdop_stripes
593 mvndiffres ndiffusion hvndiff_mask ndop_stripes
594 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
595 comment comment
596 error_p error_waffle
597 error_s error_waffle
598 error_ps error_waffle
599 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]600 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]601
602 obswell cwell
603 obsactive implant4
604
605#ifndef METAL5
606 padl metal4 via4 overglass
607#else
608 padl metal6 via6 overglass
609#endif
610
611 magnet substrate_field_implant
612 rotate via3alt
613 fence via5
614end
615
616#-----------------------------------------------------
617# Special paint/erase rules
618#-----------------------------------------------------
619
620compose
621 compose nfet poly ndiff
622 compose pfet poly pdiff
623 compose var poly nsd
624
625 compose mvnfet poly mvndiff
626 compose mvpfet poly mvpdiff
627 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]628
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]629 paint obsmcon locali via1
630 paint obsmcon obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]631
632 paint ndc nwell pdc
633 paint nfet nwell pfet
634 paint scnfet nwell scpfet
635 paint ndiff nwell pdiff
636 paint psd nwell nsd
637 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]638 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]639
640 paint pdc pwell ndc
641 paint pfet pwell nfet
642 paint scpfet pwell scnfet
643 paint pdiff pwell ndiff
644 paint nsd pwell psd
645 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]646 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]647
648 paint pdc coreli pdc
649 paint ndc coreli ndc
650 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]651 paint nsc coreli nsc
652 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]653 paint viali coreli viali
654
655 paint coreli pdc pdc
656 paint coreli ndc ndc
657 paint coreli pc pc
658 paint coreli nsc nsc
659 paint coreli psc psc
660 paint coreli viali viali
661
662#ifdef METAL5
663 paint m4 obsm4 m4
664 paint m5 obsm5 m5
665#endif (METAL5)
666end
667
668#-----------------------------------------------------
669# Electrical connectivity
670#-----------------------------------------------------
671
672connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]673 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
674 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]675 *li,coreli,lifill *li,coreli,lifill
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]676 *m1,m1fill,obsmcon *m1,m1fill,obsmcon
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]677 *m2,m2fill *m2,m2fill
678 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]679#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]680 *m4,m4fill *m4,m4fill
681 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]682#ifdef MIM
683 *mimcap *mimcap
684 *mimcap2 *mimcap2
685#endif (MIM)
686#endif (METAL5)
687 allnactivenonfet allnactivenonfet
688 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]689 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]690#ifdef REDISTRIBUTION
691 # RDL connects to m5 (i.e., padl) through glass cut
692 *mrdl *mrdl
693 glass metrdl
694#endif (REDISTRIBUTION)
695end
696
697#-----------------------------------------------------
698# CIF/GDS output layer definitions
699#-----------------------------------------------------
700# NOTE: All values in this section MUST be multiples of 25
701# or else magic will scale below the allowed layout grid size
702
703cifoutput
704
705#----------------------------------------------------------------
706style gdsii
707# NOTE: This section is used for actual GDS output
708#----------------------------------------------------------------
709 scalefactor 10 nanometers
710 options calma-permissive-labels
711 gridlimit 5
712
713#----------------------------------------------------------------
714# Create a temp layer from the cell bounding box for use in
715# generating ID layers. Note that "boundary", unlike "bbox",
716# requires the FIXED_BBOX property (abutment box) in the cell.
717#----------------------------------------------------------------
718 templayer CELLBOUND
719 boundary
720
721#----------------------------------------------------------------
722# BOUND
723#----------------------------------------------------------------
724 layer BOUND CELLBOUND
725 calma 235 4
726
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]727#----------------------------------------------------------------
728# DNWELL
729#----------------------------------------------------------------
730
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]731 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]732 calma 64 18
733
734 layer PWRES rpw
735 and dnwell
736 calma 64 13
737
738#----------------------------------------------------------------
739# NWELL
740#----------------------------------------------------------------
741
742 layer NWELL allnwell
743 bloat-all rpw dnwell
744 and-not rpw,pwell
745 calma 64 20
746
747 layer WELLTXT
748 labels allnwell noport
749 calma 64 16
750
751 layer WELLPIN
752 labels allnwell port
753 calma 64 5
754
755#----------------------------------------------------------------
756# SUB (text/port only)
757#----------------------------------------------------------------
758
759 layer SUBTXT
760 labels pwell noport
761 calma 122 16
762
763 layer SUBPIN
764 labels pwell port
765 calma 64 59
766
767#----------------------------------------------------------------
768# DIFF
769#----------------------------------------------------------------
770
771 layer DIFF allnactivenontap,allpactivenontap,allactiveres
772 labels allnactivenontap,allpactivenontap
773 calma 65 20
774
775#----------------------------------------------------------------
776# TAP
777#----------------------------------------------------------------
778
779 layer TAP allnactivetap,allpactivetap
780 labels allnactivetap,allpactivetap
781 calma 65 44
782
783#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]784# FOM
785#----------------------------------------------------------------
786
787 layer FOMFILL fomfill
788 labels fomfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]789 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]790
791#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]792# PSDM, NSDM (PPLUS, NPLUS implants)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]793#----------------------------------------------------------------
794
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]795 templayer basePSDM pdiffres,mvpdiffres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]796 grow 15
797 or xhrpoly,uhrpoly,xpc
798 grow 110
799 bloat-or allpactivetap * 125 allnactivenontap 0
800 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]801
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]802 templayer baseNSDM ndiffres,mvndiffres
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]803 grow 125
804 bloat-or allnactivetap * 125 allpactivenontap 0
805 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]806
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]807 templayer extendPSDM basePSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]808 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]809 and-not baseNSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]810
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]811 layer PSDM basePSDM,extendPSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]812 grow 185
813 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]814 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]815 mask-hints PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]816 calma 94 20
817
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]818 templayer extendNSDM baseNSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]819 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]820 and-not basePSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]821
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]822 layer NSDM baseNSDM,extendNSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]823 grow 185
824 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]825 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]826 mask-hints NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]827 calma 93 44
828
829#----------------------------------------------------------------
830# LVTN
831#----------------------------------------------------------------
832
833 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
834 grow 180
835 bridge 380 380
836 grow 185
837 shrink 185
838 close 265000
839 calma 125 44
840
841#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]842# HVTR
843#----------------------------------------------------------------
844
845 layer HVTR pfetmvt
846 grow 180
847 bridge 380 380
848 grow 185
849 shrink 185
850 close 265000
851 calma 18 20
852
853#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]854# HVTP
855#----------------------------------------------------------------
856
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]857 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]858 grow 180
859 bridge 380 380
860 grow 185
861 shrink 185
862 close 265000
863 calma 78 44
864
865#----------------------------------------------------------------
866# SONOS
867#----------------------------------------------------------------
868
869 layer SONOS nsonos
870 grow 100
871 grow-min 410
872 bridge 500 410
873 grow 250
874 shrink 250
875 calma 80 20
876
877#----------------------------------------------------------------
878# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]879# coreli layer indicates a cell needing COREID. Also, devices
880# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]881#----------------------------------------------------------------
882
883 layer COREID
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]884 bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]885 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]886 calma 81 2
887
888#----------------------------------------------------------------
889# STDCELL applies to all cells containing scnfet or scpfet.
890#----------------------------------------------------------------
891
892 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]893 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]894 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]895 calma 81 4
896
897#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]898# ESDID is a marker layer for ESD devices in the padframe I/O.
899#----------------------------------------------------------------
900
901 layer ESDID
902 bloat-all mvnfetesd *mvndiff,*poly
903 bloat-all mvpfetesd *mvpdiff,*poly
904 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]905 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]906 calma 81 19
907
908#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]909# NPNID and PNPID apply to bipolar transistors
910#----------------------------------------------------------------
911
912 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]913 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]914 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]915 calma 82 20
916
917 templayer pnparea pnp
918 grow 400
919
920 layer PNPID
921 bloat-all pnparea *psd
922 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]923 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]924 calma 82 44
925
926#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]927# RPM
928#----------------------------------------------------------------
929
930 layer RPM
931 bloat-all xhrpoly xpc
932 grow 200
933 grow-min 1270
934 grow 420
935 shrink 420
936 calma 86 20
937
938#----------------------------------------------------------------
939# URPM (2kOhms/sq. poly implant)
940#----------------------------------------------------------------
941
942 layer URPM
943 bloat-all uhrpoly xpc
944 grow 200
945 grow-min 1270
946 grow 420
947 shrink 420
948 calma 79 20
949
950#----------------------------------------------------------------
951# LDNTM (Tip implant for SONOS FETs)
952#----------------------------------------------------------------
953
954 layer LDNTM
955 bloat-all nsonos *ndiff
956 grow 185
957 grow 345
958 shrink 345
959 calma 11 44
960
961#----------------------------------------------------------------
962# HVNTM (Tip implant for MV ndiff devices)
963#----------------------------------------------------------------
964
965 templayer hvntm_block *mvpsd
966 grow 185
967
968 layer HVNTM
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]969 bloat-all mvnfet,mvnfetesd,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]970 bloat-all mvvaractor *mvnsd
971 and-not hvntm_block
972 grow 185
973 grow 345
974 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]975 and-not hvntm_block
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]976 calma 125 20
977
978#----------------------------------------------------------------
979# POLY
980#----------------------------------------------------------------
981
982 layer POLY allpoly
983 calma 66 20
984
985 layer POLYTXT
986 labels allpoly noport
987 calma 66 16
988
989 layer POLYPIN
990 labels allpoly port
991 calma 66 5
992
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]993 layer POLYFILL polyfill
994 labels polyfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]995 calma 28 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]996
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]997#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]998# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]999#----------------------------------------------------------------
1000
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1001 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1002 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1003 bloat-all alldiffmv nwell
1004 grow 345
1005 shrink 345
1006
1007 templayer large_ptap_mv thkox_area
1008 shrink 420
1009 grow 420
1010
1011 templayer small_ptap_mv thkox_area
1012 and-not large_ptap_mv
1013 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1014 grow-min 840
1015
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]1016 layer HVI thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1017 bridge 700 600
1018 grow 345
1019 shrink 345
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1020 mask-hints HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1021 calma 75 20
1022
1023#----------------------------------------------------------------
1024# CONT (LICON)
1025#----------------------------------------------------------------
1026
1027 layer CONT allcont
1028 squares-grid 0 170 170
1029 calma 66 44
1030
1031 # Contact for pres is different than other LICON contacts
1032 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1033 templayer xpc_horiz xpc
1034 shrink 1007
1035 grow 1007
1036
1037 layer CONT xpc
1038 and-not xpc_horiz
1039 # Force long edge vertical for contacts narrower than 2um
1040 # Minimum space is 350 but 520 satisfies no. of contacts rule
1041 slots 80 190 520 80 2000 350
1042 calma 66 44
1043
1044 layer CONT xpc
1045 and xpc_horiz
1046 # Force long edge vertical for contacts wider than 2um
1047 # Minimum space is 350 but 520 satisfies no. of contacts rule
1048 slots 80 2000 350 80 190 520
1049 calma 66 44
1050
1051#----------------------------------------------------------------
1052# NPC (Nitride poly cut)
1053# surrounds CONT (LICON) on poly only (i.e., pc)
1054#----------------------------------------------------------------
1055
1056 layer NPC pc
1057 squares-grid 0 170 170
1058 grow 100
1059 bridge 270 270
1060 grow 130
1061 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1062 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1063 calma 95 20
1064
1065 # NPC is also generated on xhrpoly and uhrpoly resistors
1066
1067 layer NPC xpc,xhrpoly,uhrpoly
1068 # xpc surrounds precision_resistor by 0.095um
1069 grow 95
1070 grow 130
1071 shrink 130
1072 calma 95 20
1073
1074#----------------------------------------------------------------
1075# Device markers
1076#----------------------------------------------------------------
1077
1078 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1079 calma 65 13
1080
1081 layer POLYRES mrp1
1082 calma 66 13
1083
1084 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1085 layer POLYSHORT rmp
1086 calma 66 15
1087
1088 # POLYRES extends to edge of contact cut
1089 layer POLYRES xhrpoly,uhrpoly
1090 grow 60
1091 and xpc
1092 or xhrpoly,uhrpoly
1093 calma 66 13
1094
1095 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1096 # To be done: Expand to include anode, cathode, and guard ring
1097 calma 81 23
1098
1099#----------------------------------------------------------------
1100# LI
1101#----------------------------------------------------------------
1102 layer LI allli
1103 calma 67 20
1104
1105 layer LITXT
1106 labels *locali,coreli noport
1107 calma 67 16
1108
1109 layer LIPIN
1110 labels *locali,coreli port
1111 calma 67 5
1112
1113 layer LIRES rli
1114 labels rli
1115 calma 67 13
1116
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1117 layer LIFILL lifill
1118 labels lifill
1119 calma 56 28
1120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1121#----------------------------------------------------------------
1122# MCON
1123#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1124 layer MCON mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1125 squares-grid 0 170 190
1126 calma 67 44
1127
1128#----------------------------------------------------------------
1129# MET1
1130#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1131 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1132 calma 68 20
1133
1134 layer MET1TXT
1135 labels allm1 noport
1136 calma 68 16
1137
1138 layer MET1PIN
1139 labels allm1 port
1140 calma 68 5
1141
1142 layer MET1RES rm1
1143 labels rm1
1144 calma 68 13
1145
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1146 layer MET1FILL m1fill
1147 labels m1fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1148 calma 36 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1149
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1150#----------------------------------------------------------------
1151# VIA1
1152#----------------------------------------------------------------
1153 layer VIA1 via1
1154 squares-grid 55 150 170
1155 calma 68 44
1156
1157#----------------------------------------------------------------
1158# MET2
1159#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1160 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1161 calma 69 20
1162
1163 layer MET2TXT
1164 labels allm2 noport
1165 calma 69 16
1166
1167 layer MET2PIN
1168 labels allm2 port
1169 calma 69 5
1170
1171 layer MET2RES rm2
1172 labels rm2
1173 calma 69 13
1174
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1175 layer MET2FILL m2fill
1176 labels m2fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1177 calma 41 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1178
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1179#----------------------------------------------------------------
1180# VIA2
1181#----------------------------------------------------------------
1182 layer VIA2 via2
1183 squares-grid 40 200 200
1184 calma 69 44
1185
1186#----------------------------------------------------------------
1187# MET3
1188#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1189 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1190 calma 70 20
1191
1192 layer MET3TXT
1193 labels allm3 noport
1194 calma 70 16
1195
1196 layer MET3PIN
1197 labels allm3 port
1198 calma 70 5
1199
1200 layer MET3RES rm3
1201 labels rm3
1202 calma 70 13
1203
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1204 layer MET3FILL m3fill
1205 labels m3fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1206 calma 34 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1207
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1208#ifdef METAL5
1209#----------------------------------------------------------------
1210# VIA3
1211#----------------------------------------------------------------
1212 layer VIA3 via3
1213#ifdef MIM
1214 or mimcc
1215#endif (MIM)
1216 squares-grid 60 200 200
1217 calma 70 44
1218
1219#----------------------------------------------------------------
1220# MET4
1221#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1222 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1223 calma 71 20
1224
1225 layer MET4TXT
1226 labels allm4 noport
1227 calma 71 16
1228
1229 layer MET4PIN
1230 labels allm4 port
1231 calma 71 5
1232
1233 layer MET4RES rm4
1234 labels rm4
1235 calma 71 13
1236
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1237 layer MET4FILL m4fill
1238 labels m4fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1239 calma 51 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1240
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1241#----------------------------------------------------------------
1242# VIA4
1243#----------------------------------------------------------------
1244 layer VIA4 via4
1245#ifdef MIM
1246 or mim2cc
1247#endif (MIM)
1248 squares-grid 190 800 800
1249 calma 71 44
1250
1251#----------------------------------------------------------------
1252# MET5
1253#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1254 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1255 calma 72 20
1256
1257 layer MET5TXT
1258 labels allm5 noport
1259 calma 72 16
1260
1261 layer MET5PIN
1262 labels allm5 port
1263 calma 72 5
1264
1265 layer MET5RES rm5
1266 labels rm5
1267 calma 72 13
1268
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1269 layer MET5FILL m5fill
1270 labels m5fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1271 calma 59 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1272
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1273#endif (METAL5)
1274
1275#ifdef REDISTRIBUTION
1276#----------------------------------------------------------------
1277# RDL
1278#----------------------------------------------------------------
1279 layer RDL *metrdl
1280 calma 74 20
1281
1282 layer RDLTXT
1283 labels *metrdl noport
1284 calma 74 16
1285
1286 layer RDLPIN
1287 labels *metrdl port
1288 calma 74 5
1289
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1290 layer PI1 *metrdl
1291 and padl,glass
1292 # Test only---needs GDS layer number
1293
1294 layer UBM *metrdl
1295 shrink 50000
1296 grow 40000
1297 # Test only---needs GDS layer number
1298
1299 layer PI2 *metrdl
1300 shrink 50000
1301 grow 25000
1302 # Test only---needs GDS layer number
1303
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1304#endif REDISTRIBUTION
1305
1306#----------------------------------------------------------------
1307# GLASS
1308#----------------------------------------------------------------
1309 layer GLASS glass
1310 calma 76 20
1311
1312#ifdef MIM
1313#----------------------------------------------------------------
1314# CAPM
1315#----------------------------------------------------------------
1316 layer CAPM *mimcap
1317 labels mimcap
1318 calma 89 44
1319
1320 layer CAPM2 *mimcap2
1321 labels mimcap2
1322 calma 97 44
1323#endif (MIM)
1324
1325#----------------------------------------------------------------
1326# Chip top level marker for DRC latchup rules to check 15um
1327# distance to taps (otherwise 6um is used)
1328#----------------------------------------------------------------
1329
1330 layer LOWTAPDENSITY
1331 bbox top
1332 # Clear 200um for pads + 50um for required high tap density
1333 # in critical area.
1334 shrink 250000
1335 calma 81 14
1336
1337#----------------------------------------------------------------
1338# FILLBLOCK
1339#----------------------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1340 layer FILLOBSFOM obsactive
1341 calma 22 24
1342
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1343 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1344 calma 62 24
1345
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1346 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1347 calma 105 52
1348
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1349 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1350 calma 107 24
1351
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1352 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1353 calma 112 4
1354
1355 render DNWELL cwell -0.1 0.1
1356 render NWELL nwell 0.0 0.2062
1357 render DIFF ndiffusion 0.2062 0.12
1358 render TAP pdiffusion 0.2062 0.12
1359 render POLY polysilicon 0.3262 0.18
1360 render CONT via 0.5062 0.43
1361 render LI metal1 0.9361 0.10
1362 render MCON via 1.0361 0.34
1363 render MET1 metal2 1.3761 0.36
1364 render VIA1 via 1.7361 0.27
1365 render MET2 metal3 2.0061 0.36
1366 render VIA2 via 2.3661 0.42
1367 render MET3 metal4 2.7861 0.845
1368#ifdef METAL5
1369 render VIA3 via 3.6311 0.39
1370 render MET4 metal5 4.0211 0.845
1371 render VIA4 via 4.8661 0.505
1372 render MET5 metal6 5.3711 1.26
1373 render CAPM metal8 2.4661 0.2
1374 render CAPM2 metal9 3.7311 0.2
1375#ifdef REDISTRIBUTION
1376 render RDL metal7 11.8834 4.0
1377#endif (!REDISTRIBUTION)
1378#endif (!METAL5)
1379
1380#----------------------------------------------------------------
1381style drc
1382#----------------------------------------------------------------
1383# NOTE: This style is used for DRC only, not for GDS output
1384#----------------------------------------------------------------
1385 scalefactor 10 nanometers
1386 options calma-permissive-labels
1387
1388 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1389 templayer dnwell_shrink dnwell
1390 shrink 1030
1391
1392 templayer nwell_missing dnwell
1393 grow 400
1394 and-not dnwell_shrink
1395 and-not nwell
1396
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1397 templayer pwell_in_dnwell dnwell
1398 and-not nwell
1399
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1400 # SONOS nFET devices must be in deep nwell
1401 templayer dnwell_missing nsonos
1402 and-not dnwell
1403
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1404 # SONOS nFET devices must be in cell with abutment box
1405 templayer abutment_box
1406 boundary
1407
1408 templayer bbox_missing nsonos
1409 and-not abutment_box
1410
1411 # Make sure nwell covers varactor poly
1412 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1413 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1414 grow 150
1415 and-not nwell
1416
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1417 # Define MiM cap bottom plate for spacing rule
1418 templayer mim_bottom
1419 bloat-all *mimcap *metal3
1420
1421 # Define MiM2 cap bottom plate for spacing rule
1422 templayer mim2_bottom
1423 bloat-all *mimcap2 *metal4
1424
1425 # Note that metal fill is performed by the foundry and so is not
1426 # an option for a cifoutput style.
1427
1428 # Check latchup rule (15um minimum from tap LICON center to any
1429 # non-tap diffusion. Note that to count as a tap, the diffusion
1430 # must be contacted to LI
1431
1432 templayer ptap_reach psc,mvpsc
1433 and-not dnwell
1434 # grow total is 15um. grow in 0.84um increments to ensure that
1435 # no nwell ring is crossed
1436 grow 840
1437 and-not nwell,dnwell
1438 grow 840
1439 and-not nwell,dnwell
1440 grow 840
1441 and-not nwell,dnwell
1442 grow 840
1443 and-not nwell,dnwell
1444 grow 840
1445 and-not nwell,dnwell
1446 grow 840
1447 and-not nwell,dnwell
1448 grow 840
1449 and-not nwell,dnwell
1450 grow 840
1451 and-not nwell,dnwell
1452 grow 840
1453 and-not nwell,dnwell
1454 grow 840
1455 and-not nwell,dnwell
1456 grow 840
1457 and-not nwell,dnwell
1458 grow 840
1459 and-not nwell,dnwell
1460 grow 840
1461 and-not nwell,dnwell
1462 grow 840
1463 and-not nwell,dnwell
1464 grow 840
1465 and-not nwell,dnwell
1466 grow 840
1467 and-not nwell,dnwell
1468 grow 840
1469 and-not nwell,dnwell
1470 grow 635
1471 and-not nwell,dnwell
1472
1473 templayer ptap_missing *ndiff,*mvndiff
1474 and-not dnwell
1475 and-not ptap_reach
1476
1477 templayer ntap_reach nsc,mvnsc
1478 # grow total is 15um. grow in 1.27um increments to ensure that
1479 # no nwell ring is crossed. There is no difference between
1480 # ntaps in and out of deep nwell.
1481 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1482 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1483 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1484 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1485 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1486 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1487 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1488 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1489 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1490 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1491 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1492 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1493 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1494 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1495 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1496 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1497 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1498 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1499 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1500 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1501 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1502 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1503 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1504 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1505
1506 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1507 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1508 and-not ntap_reach
1509
1510 templayer dptap_reach psc,mvpsc
1511 and dnwell
1512 grow 840
1513 and-not nwell
1514 and dnwell
1515 grow 840
1516 and-not nwell
1517 and dnwell
1518 grow 840
1519 and-not nwell
1520 and dnwell
1521 grow 840
1522 and-not nwell
1523 and dnwell
1524 grow 840
1525 and-not nwell
1526 and dnwell
1527 grow 840
1528 and-not nwell
1529 and dnwell
1530 grow 840
1531 and-not nwell
1532 and dnwell
1533 grow 840
1534 and-not nwell
1535 and dnwell
1536 grow 840
1537 and-not nwell
1538 and dnwell
1539 grow 840
1540 and-not nwell
1541 and dnwell
1542 grow 840
1543 and-not nwell
1544 and dnwell
1545 grow 840
1546 and-not nwell
1547 and dnwell
1548 grow 840
1549 and-not nwell
1550 and dnwell
1551 grow 840
1552 and-not nwell
1553 and dnwell
1554 grow 840
1555 and-not nwell
1556 and dnwell
1557 grow 840
1558 and-not nwell
1559 and dnwell
1560 grow 840
1561 and-not nwell
1562 and dnwell
1563 grow 635
1564 and-not nwell
1565 and dnwell
1566
1567 templayer dptap_missing *ndiff,*mvndiff
1568 and dnwell
1569 and-not dptap_reach
1570
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1571 templayer pdiff_crosses_dnwell dnwell
1572 grow 20
1573 and-not dnwell
1574 and allpdifflv,allpdiffmv
1575
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1576 # MV nwell must be 2um from any other nwell
1577 templayer mvnwell
1578 bloat-all alldiffmv nwell
1579 grow-min 840
1580 bridge 700 600
1581
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1582 # Simple spacing checks to lvnwell must use CIF-DRC rule
1583 templayer allmvdiffnowell *mvndiff,*mvpsd
1584
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1585 templayer lvnwell nwell
1586 and-not mvnwell
1587
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1588 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1589 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1590
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1591 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1592 and-not nwell_with_tap
1593
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1594 templayer tap_with_licon
1595 bloat-all psc,mvpsc psd,mvpsd
1596 bloat-all nsc,mvnsc nsd,mvnsd
1597
1598 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
1599 and-not tap_with_licon
1600
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1601 # Make sure varactor nwell contains no P diffusion
1602 templayer pdiff_in_varactor_well
1603 bloat-all varactor,mvvaractor nwell
1604 and allpactive
1605
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1606 # HVNTM spacing requires recreating HVNTM
1607 templayer hvntm_block *mvpsd
1608 grow 185
1609
1610 templayer hvntm_generate
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]1611 bloat-all mvnfet,mvnfetesd,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1612 bloat-all mvvaractor *mvnsd
1613 and-not hvntm_block
1614 grow 185
1615 grow 345
1616 shrink 345
1617 and-not hvntm_block
1618
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1619 templayer m1_small_hole allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1620 close 140000
1621
1622 templayer m1_hole_empty m1_small_hole
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1623 and-not allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1624
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1625 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1626 close 140000
1627
1628 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1629 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1630
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1631 templayer m1_huge allm1
1632 shrink 1500
1633 grow 1500
1634
1635 templayer m1_large_halo m1_huge
1636 grow 280
1637 and-not m1_huge
1638 and allm1
1639
1640 templayer m2_huge allm2
1641 shrink 1500
1642 grow 1500
1643
1644 templayer m2_large_halo m2_huge
1645 grow 280
1646 and-not m2_huge
1647 and allm2
1648
1649 templayer m3_huge allm3
1650 shrink 1500
1651 grow 1500
1652
1653 templayer m3_large_halo m3_huge
1654 grow 400
1655 and-not m3_huge
1656 and allm3
1657
1658 templayer m4_huge allm4
1659 shrink 1500
1660 grow 1500
1661
1662 templayer m4_large_halo m4_huge
1663 grow 400
1664 and-not m4_huge
1665 and allm4
1666
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1667#ifdef EXPERIMENTAL
1668#----------------------------------------------------------------
1669style paint
1670#----------------------------------------------------------------
1671# NOTE: This style is used for database manipulations only via
1672# the "cif paint" command.
1673#----------------------------------------------------------------
1674
1675 scalefactor 10 nanometers
1676
1677 templayer m1grow *m1
1678 grow 290
1679
1680 # layer listrap: Use the following set of commands to strap local
1681 # interconnect wires with metal1 (inside the cursor box) to satisfy
1682 # the maximum aspect ratio rule for local interconnect:
1683 #
1684 # tech unlock *
1685 # cif ostyle paint
1686 # cif paint m1strap comment
1687 # cif paint m1strap m1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1688 # cif paint listrap viali
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1689 # erase comment
1690
1691 templayer m1strap *li
1692 and-not m1grow
1693 grow 30
1694
1695 templayer listrap comment
1696 slots 30 170 170 60
1697
1698#endif (EXPERIMENTAL)
1699
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1700#----------------------------------------------------------------
Tim Edwards9ff76c52021-01-11 22:12:22 -0500[diff] [blame]1701style density
1702#----------------------------------------------------------------
1703# Style used by scripts to check for fill density
1704#----------------------------------------------------------------
1705 scalefactor 10 nanometers
1706 options calma-permissive-labels
1707 gridlimit 5
1708
1709 templayer fom_all alldiff,fomfill
1710
1711 templayer poly_all allpoly,polyfill
1712
1713 templayer li_all allli,lifill
1714
1715 templayer m1_all allm1,m1fill
1716
1717 templayer m2_all allm2,m2fill
1718
1719 templayer m3_all allm3,m3fill
1720
1721 templayer m4_all allm4,m4fill
1722
1723 templayer m5_all allm5,m5fill
1724
1725#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1726style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1727#----------------------------------------------------------------
1728# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1729# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1730#----------------------------------------------------------------
1731 scalefactor 10 nanometers
1732 options calma-permissive-labels
1733 gridlimit 5
1734
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1735#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1736# Generate and retain a layer representing the bounding box.
1737#
1738# For variant ():
1739# The bounding box is the full extent of geometry on the top level
1740# cell.
1741#
1742# For variant (tiled):
1743# Use with a script that breaks layout into flattened tiles and runs
1744# fill individually on each. The tiles should be larger than the
1745# step size, and each should draw a layer "comment" the size of the
1746# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1747#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1748
1749 variants ()
1750 templayer topbox
1751 bbox top
1752
1753 variants (tiled)
1754 templayer topbox comment
1755 # Each tile imposes the full keepout distance rule of
1756 # 3um on all sides.
1757 shrink 1500
1758
1759 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1760
1761#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1762# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1763# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1764# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1765# Enclosure by nwell = Diff/Tap 8 = 0.18um
1766#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1767
1768 templayer mvnwell
1769 bloat-all alldiffmv nwell
1770
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1771 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1772 and-not mvnwell
1773
1774 templayer well_shrink mvnwell
1775 shrink 250
1776 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1777 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1778 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1779 grow 340
1780 and-not well_shrink
1781
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1782#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1783# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1784#---------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1785 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1786 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1787 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1788 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1789
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1790 templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1791 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1792 grow 1000
1793
1794#---------------------------------------------------
1795# FOM and POLY fill
1796#---------------------------------------------------
1797 templayer fomfill_pass1 topbox
1798 slots 0 4080 1320 0 4080 1320 1360 0
1799 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1800 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1801 shrink 2035
1802 grow 2035
1803
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1804#---------------------------------------------------
1805
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1806 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1807 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1808 or obstruct_poly
1809 templayer polyfill_pass1 topbox
1810 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1811 and-not obstruct_poly_pass1
1812 and topbox
1813 shrink 355
1814 grow 355
1815
1816#---------------------------------------------------
1817
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1818 templayer obstruct_fom_pass2 fomfill_pass1
1819 grow 1290
1820 or polyfill_pass1
1821 grow 300
1822 or obstruct_fom
1823 templayer fomfill_pass2 topbox
1824 slots 0 2500 1320 0 2500 1320 1360 0
1825 and-not obstruct_fom_pass2
1826 and topbox
1827 shrink 1245
1828 grow 1245
1829
1830#---------------------------------------------------
1831
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1832 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1833 grow 60
1834 or fomfill_pass1,fomfill_pass2
1835 grow 300
1836 or obstruct_poly
1837 templayer polyfill_coarse topbox
1838 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1839 and-not obstruct_poly_coarse
1840 and topbox
1841 shrink 355
1842 grow 355
1843
1844#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1845 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1846 grow 60
1847 or fomfill_pass1,fomfill_pass2
1848 grow 300
1849 or obstruct_poly
1850 templayer polyfill_medium topbox
1851 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1852 and-not obstruct_poly_medium
1853 and topbox
1854 shrink 265
1855 grow 265
1856
1857#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1858 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1859 grow 60
1860 or fomfill_pass1,fomfill_pass2
1861 grow 300
1862 or obstruct_poly
1863 templayer polyfill_fine topbox
1864 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1865 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1866 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1867 shrink 235
1868 grow 235
1869
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1870#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1871
1872 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1873 grow 1290
1874 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1875 grow 300
1876 or obstruct_fom
1877 templayer fomfill_coarse topbox
1878 slots 0 1500 1320 0 1500 1320 1360 0
1879 and-not obstruct_fom_coarse
1880 and topbox
1881 shrink 745
1882 grow 745
1883
1884#---------------------------------------------------
1885
1886 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1887 grow 1290
1888 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1889 grow 300
1890 or obstruct_fom
1891 templayer fomfill_fine topbox
1892 slots 0 500 400 0 500 400 160 0
1893 and-not obstruct_fom_fine
1894 and topbox
1895 shrink 245
1896 grow 245
1897
1898#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1899 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1900 or fomfill_pass2
1901 or fomfill_coarse
1902 or fomfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1903 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1904
1905 layer POLYFILL polyfill_pass1
1906 or polyfill_coarse
1907 or polyfill_medium
1908 or polyfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1909 calma 28 28
1910
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1911#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1912# LI fill
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1913# Note requirement that LI fill may not overlap (non-fill)
1914# diff or poly.
1915#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1916
1917 templayer obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1918 grow 2800
1919 or alldiff,allpoly
1920 grow 200
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1921 templayer lifill_coarse topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1922 slots 0 3000 500 0 3000 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1923 and-not obstruct_li_coarse
1924 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1925 shrink 1495
1926 grow 1495
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1927
1928 templayer obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1929 grow 2500
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1930 or lifill_coarse
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1931 grow 300
1932 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1933 grow 200
1934 templayer lifill_medium topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1935 slots 0 1500 500 0 1500 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1936 and-not obstruct_li_medium
1937 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1938 shrink 745
1939 grow 745
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1940
1941 templayer obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1942 or lifill_coarse,lifill_medium
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1943 grow 300
1944 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1945 grow 200
1946 templayer lifill_fine topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1947 slots 0 580 500 0 580 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1948 and-not obstruct_li_fine
1949 and topbox
1950 shrink 285
1951 grow 285
1952
1953 layer LIFILL lifill_coarse
1954 or lifill_medium
1955 or lifill_fine
1956 calma 56 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1957
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1958#---------------------------------------------------
1959# MET1 fill
1960#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1961
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1962 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1963 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1964 templayer met1fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]1965 # slots 0 2000 200 0 2000 200 700 0
1966 slots 0 2000 350 0 2000 350 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1967 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1968 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1969 shrink 995
1970 grow 995
1971
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1972 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1973 grow 2800
1974 or met1fill_coarse
1975 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1976 templayer met1fill_medium topbox
1977 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1978 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1979 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1980 shrink 495
1981 grow 495
1982
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1983 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1984 grow 300
1985 or met1fill_coarse,met1fill_medium
1986 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1987 templayer met1fill_fine topbox
1988 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1989 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1990 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1991 shrink 285
1992 grow 285
1993
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1994 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1995 grow 100
1996 or met1fill_coarse,met1fill_medium,met1fill_fine
1997 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1998 templayer met1fill_veryfine topbox
1999 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2000 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2001 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2002 shrink 145
2003 grow 145
2004
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2005 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2006 or met1fill_medium
2007 or met1fill_fine
2008 or met1fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2009 calma 36 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2010
2011#---------------------------------------------------
2012# MET2 fill
2013#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2014 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2015 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2016 templayer met2fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2017 # slots 0 2000 200 0 2000 200 700 350
2018 slots 0 2000 350 0 2000 350 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2019 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2020 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2021 shrink 995
2022 grow 995
2023
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2024 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2025 grow 2800
2026 or met2fill_coarse
2027 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2028 templayer met2fill_medium topbox
2029 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2030 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2031 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2032 shrink 495
2033 grow 495
2034
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2035 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2036 grow 300
2037 or met2fill_coarse,met2fill_medium
2038 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2039 templayer met2fill_fine topbox
2040 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2041 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2042 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2043 shrink 285
2044 grow 285
2045
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2046 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2047 grow 100
2048 or met2fill_coarse,met2fill_medium,met2fill_fine
2049 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2050 templayer met2fill_veryfine topbox
2051 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2052 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2053 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2054 shrink 145
2055 grow 145
2056
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2057 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2058 or met2fill_medium
2059 or met2fill_fine
2060 or met2fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2061 calma 41 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2062
2063#---------------------------------------------------
2064# MET3 fill
2065#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2066 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2067 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2068 templayer met3fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2069 # slots 0 2000 300 0 2000 300 700 700
2070 slots 0 2000 350 0 2000 350 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2071 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2072 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2073 shrink 995
2074 grow 995
2075
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2076 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2077 grow 2700
2078 or met3fill_coarse
2079 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2080 templayer met3fill_medium topbox
2081 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2082 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2083 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2084 shrink 495
2085 grow 495
2086
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2087 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2088 grow 200
2089 or met3fill_coarse,met3fill_medium
2090 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2091 templayer met3fill_fine topbox
2092 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2093 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2094 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2095 shrink 285
2096 grow 285
2097
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2098 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2099 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2100 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2101 or met3fill_coarse,met3fill_medium,met3fill_fine
2102 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2103 templayer met3fill_veryfine topbox
2104 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2105 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2106 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2107 shrink 195
2108 grow 195
2109
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2110 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2111 or met3fill_medium
2112 or met3fill_fine
2113 or met3fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2114 calma 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2115
2116#ifdef METAL5
2117#---------------------------------------------------
2118# MET4 fill
2119#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2120 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2121 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2122 templayer met4fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2123 # slots 0 2000 300 0 2000 300 700 1050
2124 slots 0 2000 350 0 2000 350 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2125 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2126 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2127 shrink 995
2128 grow 995
2129
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2130 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2131 grow 2700
2132 or met4fill_coarse
2133 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2134 templayer met4fill_medium topbox
2135 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2136 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]2137 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2138 shrink 495
2139 grow 495
2140
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2141 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2142 grow 200
2143 or met4fill_coarse,met4fill_medium
2144 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2145 templayer met4fill_fine topbox
2146 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2147 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2148 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2149 shrink 285
2150 grow 285
2151
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2152 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2153 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2154 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2155 or met4fill_coarse,met4fill_medium,met4fill_fine
2156 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2157 templayer met4fill_veryfine topbox
2158 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2159 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2160 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2161 shrink 195
2162 grow 195
2163
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2164 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2165 or met4fill_medium
2166 or met4fill_fine
2167 or met4fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2168 calma 51 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2169
2170#---------------------------------------------------
2171# MET5 fill
2172#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2173 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2174 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2175 templayer met5fill_gen topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2176 # slots 0 3000 1600 0 3000 1600 1000 100
2177 slots 0 5000 1600 0 5000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2178 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2179 and topbox
Tim Edwards7324f652021-01-12 10:20:16 -0500[diff] [blame]2180 # shrink 1495
2181 # grow 1495
2182 shrink 2495
2183 grow 2495
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2184
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2185 layer MET5FILL met5fill_gen
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2186 calma 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2187#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2188
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2189end
2190
2191#-----------------------------------------------------------------------
2192cifinput
2193#-----------------------------------------------------------------------
2194# NOTE: All values in this section MUST be multiples of 25
2195# or else magic will scale below the allowed layout grid size
2196#-----------------------------------------------------------------------
2197
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2198style sky130 variants (),(vendor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2199 scalefactor 10 nanometers
2200 gridlimit 5
2201
2202 options ignore-unknown-layer-labels no-reconnect-labels
2203
2204#ifndef MIM
2205 ignore CAPM
2206 ignore CAPM2
2207#endif (!MIM)
2208#ifndef METAL5
2209 ignore MET4,VIA3
2210 ignore MET5,VIA4
2211#endif
2212 ignore NPC
2213 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2214 ignore CAPID
2215 ignore LDNTM
2216 ignore HVNTM
2217 ignore POLYMOD
2218 ignore LOWTAPDENSITY
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]2219 ignore FILLOBSPOLY
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2220
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2221 layer pnp NWELL,WELLTXT,WELLPIN
2222 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2223 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2224 variants (vendor)
2225 labels WELLTXT port
2226 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2227 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2228 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2229 labels WELLPIN port
2230
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2231 layer nwell NWELL,WELLTXT,WELLPIN
2232 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2233 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2234 variants (vendor)
2235 labels WELLTXT port
2236 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2237 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2238 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2239 labels WELLPIN port
2240
2241 layer pwell SUBTXT,SUBPIN
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2242 variants (vendor)
2243 labels SUBTXT port
2244 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2245 labels SUBTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2246 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2247 labels SUBPIN port
2248
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2249 # Always draw pwell under p-tap
2250 layer pwell TAP
2251 and-not NWELL
2252
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2253 layer dnwell DNWELL
2254 labels DNWELL
2255
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2256 layer npn DNWELL
2257 and-not NWELL
2258 and NPNID
2259
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2260 layer rpw PWRES
2261 and DNWELL
2262 labels PWRES
2263
2264 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
2265 and-not POLY
2266 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2267 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2268 and-not DIODE
2269 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2270 and-not HVI
2271 and NSDM
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2272 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2273 copyup ndifcheck
2274 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2275 variants (vendor)
2276 labels DIFFTXT port
2277 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2278 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2279 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2280 labels DIFFPIN port
2281 labels TAPPIN port
2282
2283 layer ndiff ndiffarea
2284
2285 # Copy ndiff areas up for contact checks
2286 templayer xndifcheck ndifcheck
2287 copyup ndifcheck
2288
2289 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
2290 and-not POLY
2291 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2292 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2293 and-not DIODE
2294 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2295 and HVI
2296 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2297 copyup ndifcheck
2298 labels DIFF
2299 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2300 variants (vendor)
2301 labels DIFFTXT port
2302 variants ()
2303 labels DIFFTXT text
2304 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2305 labels DIFFPIN port
2306
2307 layer mvndiff mvndiffarea
2308
2309 # Copy ndiff areas up for contact checks
2310 templayer mvxndifcheck mvndifcheck
2311 copyup mvndifcheck
2312
2313 layer ndiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2314 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2315 and DIODE
2316 and-not NWELL
2317 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2318 and-not PSDM
2319 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2320 and-not LVTN
2321 labels DIFF
2322
2323 layer ndiodelvt DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2324 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2325 and DIODE
2326 and-not NWELL
2327 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2328 and-not PSDM
2329 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2330 and LVTN
2331 labels DIFF
2332
2333 templayer ndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2334 and NSDM
2335 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2336 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2337 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2338
2339 layer ndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2340 and NSDM
2341 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2342 labels DIFF
2343
2344 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
2345 and-not POLY
2346 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2347 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2348 and-not DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2349 and-not HVI
2350 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2351 copyup pdifcheck
2352 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2353 variants (vendor)
2354 labels DIFFTXT port
2355 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2356 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2357 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2358 labels DIFFPIN port
2359
2360 layer pdiff pdiffarea
2361
2362 layer mvndiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2363 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2364 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2365 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2366 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2367 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2368 and-not LVTN
2369 labels DIFF
2370
2371 layer nndiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2372 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2373 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2374 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2375 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2376 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2377 and LVTN
2378 labels DIFF
2379
2380 templayer mvndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2381 and NSDM
2382 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2383 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2384 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2385
2386 layer mvndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2387 and NSDM
2388 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2389 labels DIFF
2390
2391 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
2392 and-not POLY
2393 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2394 and-not NSDM
2395 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2396 and-not DIODE
2397 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2398 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2399 copyup mvpdifcheck
2400 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2401 variants (vendor)
2402 labels DIFFTXT port
2403 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2404 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2405 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2406 labels DIFFPIN port
2407
2408 layer mvpdiff mvpdiffarea
2409
2410 # Copy pdiff areas up for contact checks
2411 templayer xpdifcheck pdifcheck
2412 copyup pdifcheck
2413
2414 layer pdiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2415 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2416 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2417 and-not NSDM
2418 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2419 and-not LVTN
2420 and-not HVTP
2421 and DIODE
2422 labels DIFF
2423
2424 layer pdiodelvt DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2425 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2426 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2427 and-not NSDM
2428 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2429 and LVTN
2430 and-not HVTP
2431 and DIODE
2432 labels DIFF
2433
2434 layer pdiodehvt DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2435 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2436 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2437 and-not NSDM
2438 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2439 and-not LVTN
2440 and HVTP
2441 and DIODE
2442 labels DIFF
2443
2444 templayer pdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2445 and PSDM
2446 and-not HVI
2447 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2448
2449 # Define pfet areas as known pdiff, regardless of the presence of a well.
2450
2451 templayer pfetarea DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2452 and-not NSDM
2453 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2454 and POLY
2455
2456 layer pfet pfetarea
2457 and-not LVTN
2458 and-not HVTP
2459 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2460 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2461 labels DIFF
2462
2463 layer scpfet pfetarea
2464 and-not LVTN
2465 and-not HVTP
2466 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2467 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2468 labels DIFF
2469
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2470 layer scpfethvt pfetarea
2471 and-not LVTN
2472 and HVTP
2473 and STDCELL
2474 labels DIFF
2475
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2476 layer ppu pfetarea
2477 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2478 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2479 and COREID
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2480 # Shrink-grow operation eliminates the smaller ppass device
2481 shrink 70
2482 grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2483 labels DIFF
2484
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2485 layer pfetlvt pfetarea
2486 and LVTN
2487 labels DIFF
2488
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2489 layer pfetmvt pfetarea
2490 and HVTR
2491 labels DIFF
2492
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2493 layer pfethvt pfetarea
2494 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2495 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2496 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2497 labels DIFF
2498
2499 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2500 layer nwell pfetarea
2501 grow 180
2502
2503 # Copy mvpdiff areas up for contact checks
2504 templayer mvxpdifcheck mvpdifcheck
2505 copyup mvpdifcheck
2506
2507 layer mvpdiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2508 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2509 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2510 and-not NSDM
2511 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2512 and DIODE
2513 labels DIFF
2514
2515 templayer mvpdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2516 and PSDM
2517 and HVI
2518 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2519
2520 # Define pfet areas as known pdiff,
2521 # regardless of the presence of a
2522 # well.
2523
2524 templayer mvpfetarea DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2525 and-not NSDM
2526 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2527 and POLY
2528
2529 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2530 and-not ESDID
2531 labels DIFF
2532
2533 layer mvpfetesd mvpfetarea
2534 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2535 labels DIFF
2536
2537 layer pdiff DIFF,DIFFTXT,DIFFPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2538 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2539 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2540 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2541 and-not DIODE
2542 and-not DIFFRES
2543 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2544 variants (vendor)
2545 labels DIFFTXT port
2546 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2547 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2548 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2549 labels DIFFPIN port
2550
2551 layer pdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2552 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2553 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2554 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2555 labels DIFF
2556
2557 layer nfet DIFF
2558 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2559 and-not PSDM
2560 and NSDM
2561 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2562 and-not LVTN
2563 and-not SONOS
2564 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2565 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2566 labels DIFF
2567
2568 layer scnfet DIFF
2569 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2570 and-not PSDM
2571 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2572 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2573 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2574 and-not LVTN
2575 and-not SONOS
2576 and STDCELL
2577 labels DIFF
2578
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2579 layer npass DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2580 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2581 and-not PSDM
2582 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2583 and-not NWELL
2584 and COREID
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2585 # Shrink-grow operation eliminates the smaller npass device
2586 shrink 70
2587 grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2588 labels DIFF
2589
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2590 layer npd DIFF
2591 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2592 and-not PSDM
2593 and NSDM
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2594 and-not NWELL
2595 and COREID
2596 # Shrink-grow operation eliminates the smaller npass device
2597 shrink 70
2598 grow 70
2599 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2600
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2601 layer nfetlvt DIFF
2602 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2603 and-not PSDM
2604 and NSDM
2605 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2606 and LVTN
2607 and-not SONOS
2608 labels DIFF
2609
2610 layer nsonos DIFF
2611 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2612 and-not PSDM
2613 and NSDM
2614 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2615 and LVTN
2616 and SONOS
2617 labels DIFF
2618
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2619 templayer nsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2620 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2621 and NWELL
2622 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2623 and-not PSDM
2624 and-not HVI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2625 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2626 copyup nsubcheck
2627
2628 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2629 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2630
2631 layer nsd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2632 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2633 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2634 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2635 labels TAP
2636 labels TAPPIN port
2637
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2638 layer corenvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2639 and NSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2640 and POLY
2641 and COREID
2642 labels TAP
2643
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2644 templayer nsdexpand nsdarea
2645 grow 500
2646
2647 # Copy nsub areas up for contact checks
2648 templayer xnsubcheck nsubcheck
2649 copyup nsubcheck
2650
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2651 templayer psdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2652 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2653 and-not NWELL
2654 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2655 and-not NSDM
2656 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2657 and-not pfetexpand
2658 copyup psubcheck
2659
2660 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2661 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2662
2663 layer psd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2664 and PSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2665 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2666 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2667 labels TAP
2668 labels TAPPIN port
2669
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2670 layer corepvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2671 and PSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2672 and POLY
2673 and COREID
2674 labels TAP
2675
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2676 templayer psdexpand psdarea
2677 grow 500
2678
2679 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2680 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2681 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2682 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2683 and mvpfetexpand
2684 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2685 variants (vendor)
2686 labels DIFFTXT port
2687 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2688 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2689 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2690 labels DIFFPIN port
2691
2692 layer mvpdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2693 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2694 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2695 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2696 and-not mvrdpioedge
2697 labels DIFF
2698
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2699 templayer mvnfetarea DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2700 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2701 and-not PSDM
2702 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2703 and-not LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2704 and HVI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2705 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2706
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2707 templayer mvnnfetarea DIFF,TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2708 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2709 and-not PSDM
2710 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2711 and LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2712 and HVI
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2713 and-not mvnfetarea
2714
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2715 layer mvnfetesd DIFF
2716 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2717 and-not PSDM
2718 and NSDM
2719 and HVI
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2720 and ESDID
2721 and-not mvnnfetarea
2722 labels DIFF
2723
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2724 layer mvnfet DIFF
2725 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2726 and-not PSDM
2727 and NSDM
2728 and HVI
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2729 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2730 and-not mvnnfetarea
2731 labels DIFF
2732
2733 layer mvnnfet mvnnfetarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2734 labels DIFF
2735
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2736 templayer mvnsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2737 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2738 and NWELL
2739 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2740 and-not PSDM
2741 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2742 copyup mvnsubcheck
2743
2744 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2745 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2746
2747 layer mvnsd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2748 and NSDM
2749 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2750 labels TAP
2751 labels TAPPIN port
2752
2753 templayer mvnsdexpand mvnsdarea
2754 grow 500
2755
2756 # Copy nsub areas up for contact checks
2757 templayer mvxnsubcheck mvnsubcheck
2758 copyup mvnsubcheck
2759
2760 templayer mvpsdarea DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2761 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2762 and-not NWELL
2763 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2764 and-not NSDM
2765 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2766 and-not mvpfetexpand
2767 copyup mvpsubcheck
2768
2769 layer mvpsd mvpsdarea
2770 labels DIFF
2771
2772 layer mvpsd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2773 and PSDM
2774 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2775 labels TAP
2776 labels TAPPIN port
2777
2778 templayer mvpsdexpand mvpsdarea
2779 grow 500
2780
2781 # Copy psub areas up for contact checks
2782 templayer xpsubcheck psubcheck
2783 copyup psubcheck
2784
2785 templayer mvxpsubcheck mvpsubcheck
2786 copyup mvpsubcheck
2787
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2788 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2789 and-not PSDM
2790 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2791 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2792 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2793 and-not pfetexpand
2794 and psdexpand
2795
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2796 layer nsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2797 and-not PSDM
2798 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2799 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2800 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2801 and nsdexpand
2802
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2803 layer mvpsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2804 and-not PSDM
2805 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2806 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2807 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2808 and-not mvpfetexpand
2809 and mvpsdexpand
2810
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2811 layer mvnsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2812 and-not PSDM
2813 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2814 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2815 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2816 and mvnsdexpand
2817
2818 templayer hresarea POLY
2819 and RPM
2820 grow 3000
2821
2822 templayer uresarea POLY
2823 and URPM
2824 grow 3000
2825
2826 templayer diffresarea DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2827 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2828 grow 3000
2829
2830 templayer mvdiffresarea DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2831 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2832 grow 3000
2833
2834 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2835
2836 layer pfet POLY
2837 and DIFF
2838 and diffresarea
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2839 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2840 and-not STDCELL
2841
2842 layer scpfet POLY
2843 and DIFF
2844 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2845 and-not HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2846 and-not NSDM
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2847 and STDCELL
2848
2849 layer scpfethvt POLY
2850 and DIFF
2851 and diffresarea
2852 and HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2853 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2854 and STDCELL
2855
2856 templayer xpolyterm RPM,URPM
2857 and POLY
2858 and-not POLYRES
2859 # add back the 0.06um contact surround in the direction of the resistor
2860 grow 60
2861 and POLY
2862
2863 layer xpc xpolyterm
2864
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2865 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2866 and-not POLYRES
2867 and-not POLYSHORT
2868 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2869 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2870 and-not RPM
2871 and-not URPM
2872 copyup polycheck
2873
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2874 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2875 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2876 variants (vendor)
2877 labels POLYTXT port
2878 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2879 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2880 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2881 labels POLYPIN port
2882
2883 # Copy (non-resistor) poly areas up for contact checks
2884 templayer xpolycheck polycheck
2885 copyup polycheck
2886
2887 layer mrp1 POLY
2888 and POLYRES
2889 and-not RPM
2890 and-not URPM
2891 labels POLY
2892
2893 layer rmp POLY
2894 and POLYSHORT
2895 labels POLY
2896
2897 layer xhrpoly POLY
2898 and POLYRES
2899 and RPM
2900 and-not URPM
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2901 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2902 and NPC
2903 and-not xpolyterm
2904 labels POLY
2905
2906 layer uhrpoly POLY
2907 and POLYRES
2908 and URPM
2909 and-not RPM
2910 and NPC
2911 and-not xpolyterm
2912 labels POLY
2913
2914 templayer ndcbase CONT
2915 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2916 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2917 and-not NWELL
2918 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2919 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2920
2921 layer ndc ndcbase
2922 grow 85
2923 shrink 85
2924 shrink 85
2925 grow 85
2926 or ndcbase
2927 labels CONT
2928
2929 templayer nscbase CONT
2930 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2931 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2932 and NWELL
2933 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2934 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2935
2936 layer nsc nscbase
2937 grow 85
2938 shrink 85
2939 shrink 85
2940 grow 85
2941 or nscbase
2942 labels CONT
2943
2944 templayer pdcbase CONT
2945 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2946 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2947 and NWELL
2948 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2949 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2950
2951 layer pdc pdcbase
2952 grow 85
2953 shrink 85
2954 shrink 85
2955 grow 85
2956 or pdcbase
2957 labels CONT
2958
2959 templayer pdcnowell CONT
2960 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2961 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2962 and pfetexpand
2963 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2964 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2965
2966 layer pdc pdcnowell
2967 grow 85
2968 shrink 85
2969 shrink 85
2970 grow 85
2971 or pdcnowell
2972 labels CONT
2973
2974 templayer pscbase CONT
2975 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2976 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2977 and-not NWELL
2978 and-not pfetexpand
2979 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2980 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2981
2982 layer psc pscbase
2983 grow 85
2984 shrink 85
2985 shrink 85
2986 grow 85
2987 or pscbase
2988 labels CONT
2989
2990 templayer pcbase CONT
2991 and POLY
2992 and-not DIFF
2993 and-not RPM,URPM
2994 and LI
2995
2996 layer pc pcbase
2997 grow 85
2998 shrink 85
2999 shrink 85
3000 grow 85
3001 or pcbase
3002 labels CONT
3003
3004 templayer ndicbase CONT
3005 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3006 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3007 and DIODE
3008 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3009 and-not PSDM
3010 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3011 and-not LVTN
3012
3013 layer ndic ndicbase
3014 grow 85
3015 shrink 85
3016 shrink 85
3017 grow 85
3018 or ndicbase
3019 labels CONT
3020
3021 templayer ndilvtcbase CONT
3022 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3023 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3024 and DIODE
3025 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3026 and-not PSDM
3027 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3028 and LVTN
3029
3030 layer ndilvtc ndilvtcbase
3031 grow 85
3032 shrink 85
3033 shrink 85
3034 grow 85
3035 or ndilvtcbase
3036 labels CONT
3037
3038 templayer pdicbase CONT
3039 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3040 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3041 and DIODE
3042 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3043 and-not NSDM
3044 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3045 and-not LVTN
3046 and-not HVTP
3047
3048 layer pdic pdicbase
3049 grow 85
3050 shrink 85
3051 shrink 85
3052 grow 85
3053 or pdicbase
3054 labels CONT
3055
3056 templayer pdilvtcbase CONT
3057 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3058 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3059 and DIODE
3060 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3061 and-not NSDM
3062 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3063 and LVTN
3064 and-not HVTP
3065
3066 layer pdilvtc pdilvtcbase
3067 grow 85
3068 shrink 85
3069 shrink 85
3070 grow 85
3071 or pdilvtcbase
3072 labels CONT
3073
3074 templayer pdihvtcbase CONT
3075 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3076 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3077 and DIODE
3078 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3079 and-not NSDM
3080 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3081 and-not LVTN
3082 and HVTP
3083
3084 layer pdihvtc pdihvtcbase
3085 grow 85
3086 shrink 85
3087 shrink 85
3088 grow 85
3089 or pdihvtcbase
3090 labels CONT
3091
3092 templayer mvndcbase CONT
3093 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3094 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3095 and-not NWELL
3096 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3097 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3098
3099 layer mvndc mvndcbase
3100 grow 85
3101 shrink 85
3102 shrink 85
3103 grow 85
3104 or mvndcbase
3105 labels CONT
3106
3107 templayer mvnscbase CONT
3108 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3109 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3110 and NWELL
3111 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3112 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3113
3114 layer mvnsc mvnscbase
3115 grow 85
3116 shrink 85
3117 shrink 85
3118 grow 85
3119 or mvnscbase
3120 labels CONT
3121
3122 templayer mvpdcbase CONT
3123 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3124 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3125 and NWELL
3126 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3127 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3128
3129 layer mvpdc mvpdcbase
3130 grow 85
3131 shrink 85
3132 shrink 85
3133 grow 85
3134 or mvpdcbase
3135 labels CONT
3136
3137 templayer mvpdcnowell CONT
3138 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3139 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3140 and mvpfetexpand
3141 and MET1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3142 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3143
3144 layer mvpdc mvpdcnowell
3145 grow 85
3146 shrink 85
3147 shrink 85
3148 grow 85
3149 or mvpdcnowell
3150 labels CONT
3151
3152 templayer mvpscbase CONT
3153 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3154 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3155 and-not NWELL
3156 and-not mvpfetexpand
3157 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3158 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3159
3160 layer mvpsc mvpscbase
3161 grow 85
3162 shrink 85
3163 shrink 85
3164 grow 85
3165 or mvpscbase
3166 labels CONT
3167
3168 templayer mvndicbase CONT
3169 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3170 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3171 and DIODE
3172 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3173 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3174 and-not LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3175 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3176
3177 layer mvndic mvndicbase
3178 grow 85
3179 shrink 85
3180 shrink 85
3181 grow 85
3182 or mvndicbase
3183 labels CONT
3184
3185 templayer nndicbase CONT
3186 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3187 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3188 and DIODE
3189 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3190 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3191 and LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3192 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3193
3194 layer nndic nndicbase
3195 grow 85
3196 shrink 85
3197 shrink 85
3198 grow 85
3199 or nndicbase
3200 labels CONT
3201
3202 templayer mvpdicbase CONT
3203 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3204 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3205 and DIODE
3206 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3207 and-not NSDM
3208 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3209
3210 layer mvpdic mvpdicbase
3211 grow 85
3212 shrink 85
3213 shrink 85
3214 grow 85
3215 or mvpdicbase
3216 labels CONT
3217
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3218 layer fomfill FOMFILL
3219 labels FOMFILL
3220
3221 layer polyfill POLYFILL
3222 labels POLYFILL
3223
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3224 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3225 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3226 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3227 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3228 variants (vendor)
3229 labels LITXT port
3230 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3231 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3232 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3233 labels LIPIN port
3234
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3235 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3236 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3237 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3238 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3239 variants (vendor)
3240 labels LITXT port
3241 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3242 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3243 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3244 labels LIPIN port
3245
3246 layer rli LI
3247 and LIRES,LISHORT
3248 labels LIRES,LISHORT
3249
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3250 layer lifill LIFILL
3251 labels LIFILL
3252
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3253 layer mcon MCON
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3254 grow 95
3255 shrink 95
3256 shrink 85
3257 grow 85
3258 or MCON
3259 labels MCON
3260
3261 layer m1 MET1,MET1TXT,MET1PIN
3262 and-not MET1RES,MET1SHORT
3263 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3264 variants (vendor)
3265 labels MET1TXT port
3266 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3267 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3268 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3269 labels MET1PIN port
3270
3271 layer rm1 MET1
3272 and MET1RES,MET1SHORT
3273 labels MET1RES,MET1SHORT
3274
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3275 layer m1fill MET1FILL
3276 labels MET1FILL
3277
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3278#ifdef MIM
3279 layer mimcap MET3
3280 and CAPM
3281 labels CAPM
3282
3283 layer mimcc VIA3
3284 and CAPM
3285 grow 60
3286 grow 40
3287 shrink 40
3288 labels CAPM
3289
3290 layer mimcap2 MET4
3291 and CAPM2
3292 labels CAPM2
3293
3294 layer mim2cc VIA4
3295 and CAPM2
3296 grow 190
3297 grow 210
3298 shrink 210
3299 labels CAPM2
3300
3301#endif (MIM)
3302
3303 templayer m2cbase VIA1
3304 grow 55
3305
3306 layer m2c m2cbase
3307 grow 30
3308 shrink 30
3309 shrink 130
3310 grow 130
3311 or m2cbase
3312
3313 layer m2 MET2,MET2TXT,MET2PIN
3314 and-not MET2RES,MET2SHORT
3315 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3316 variants (vendor)
3317 labels MET2TXT port
3318 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3319 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3320 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3321 labels MET2PIN port
3322
3323 layer rm2 MET2
3324 and MET2RES,MET2SHORT
3325 labels MET2RES,MET2SHORT
3326
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3327 layer m2fill MET2FILL
3328 labels MET2FILL
3329
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3330 templayer m3cbase VIA2
3331 grow 40
3332
3333 layer m3c m3cbase
3334 grow 60
3335 shrink 60
3336 shrink 140
3337 grow 140
3338 or m3cbase
3339
3340 layer m3 MET3,MET3TXT,MET3PIN
3341 and-not MET3RES,MET3SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3342 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3343 variants (vendor)
3344 labels MET3TXT port
3345 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3346 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3347 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3348 labels MET3PIN port
3349
3350 layer rm3 MET3
3351 and MET3RES,MET3SHORT
3352 labels MET3RES,MET3SHORT
3353
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3354 layer m3fill MET3FILL
3355 labels MET3FILL
3356
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3357#ifdef (METAL5)
3358
3359 templayer via3base VIA3
3360#ifdef MIM
3361 and-not CAPM
3362#endif (MIM)
3363 grow 60
3364
3365 layer via3 via3base
3366 grow 40
3367 shrink 40
3368 shrink 160
3369 grow 160
3370 or via3base
3371
3372 layer m4 MET4,MET4TXT,MET4PIN
3373 and-not MET4RES,MET4SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3374 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3375 variants (vendor)
3376 labels MET4TXT port
3377 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3378 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3379 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3380 labels MET4PIN port
3381
3382 layer rm4 MET4
3383 and MET4RES,MET4SHORT
3384 labels MET4RES,MET4SHORT
3385
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3386 layer m4fill MET4FILL
3387 labels MET4FILL
3388
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3389 layer m5 MET5,MET5TXT,MET5PIN
3390 and-not MET5RES,MET5SHORT
3391 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3392 variants (vendor)
3393 labels MET5TXT port
3394 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3395 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3396 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3397 labels MET5PIN port
3398
3399 layer rm5 MET5
3400 and MET5RES,MET5SHORT
3401 labels MET5RES,MET5SHORT
3402
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3403 layer m5fill MET5FILL
3404 labels MET5FILL
3405
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3406 templayer via4base VIA4
3407#ifdef MIM
3408 and-not CAPM2
3409#endif (MIM)
3410 grow 190
3411
3412 layer via4 via4base
3413 grow 210
3414 shrink 210
3415 shrink 590
3416 grow 590
3417 or via4base
3418#endif (METAL5)
3419
3420#ifdef REDISTRIBUTION
3421 layer metrdl RDL,RDLTXT,RDLPIN
3422 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3423 variants (vendor)
3424 labels RDLTXT port
3425 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3426 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3427 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3428 labels RDLPIN port
3429#endif
3430
3431 # Find diffusion not covered in
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3432 # NSDM or PSDM and pull it into
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3433 # the next layer up
3434
3435 templayer gentrans DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3436 and-not PSDM
3437 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3438 and POLY
3439 copyup DIFF,POLY
3440
3441 templayer gendiff DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3442 and-not PSDM
3443 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3444 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3445 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3446 copyup DIFF
3447
3448 # Handle contacts found by copyup
3449
3450 templayer ndiccopy CONT
3451 and LI
3452 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3453 and NSDM
3454 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3455
3456 layer ndic ndiccopy
3457 grow 85
3458 shrink 85
3459 shrink 85
3460 grow 85
3461 or ndiccopy
3462 labels CONT
3463
3464 templayer mvndiccopy CONT
3465 and LI
3466 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3467 and NSDM
3468 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3469
3470 layer mvndic mvndiccopy
3471 grow 85
3472 shrink 85
3473 shrink 85
3474 grow 85
3475 or mvndiccopy
3476 labels CONT
3477
3478 templayer pdiccopy CONT
3479 and LI
3480 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3481 and PSDM
3482 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3483
3484 layer pdic pdiccopy
3485 grow 85
3486 shrink 85
3487 shrink 85
3488 grow 85
3489 or pdiccopy
3490 labels CONT
3491
3492 templayer mvpdiccopy CONT
3493 and LI
3494 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3495 and PSDM
3496 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3497
3498 layer mvpdic mvpdiccopy
3499 grow 85
3500 shrink 85
3501 shrink 85
3502 grow 85
3503 or mvpdiccopy
3504 labels CONT
3505
3506 templayer ndccopy CONT
3507 and ndifcheck
3508
3509 layer ndc ndccopy
3510 grow 85
3511 shrink 85
3512 shrink 85
3513 grow 85
3514 or ndccopy
3515 labels CONT
3516
3517 templayer mvndccopy CONT
3518 and mvndifcheck
3519
3520 layer mvndc mvndccopy
3521 grow 85
3522 shrink 85
3523 shrink 85
3524 grow 85
3525 or mvndccopy
3526 labels CONT
3527
3528 templayer pdccopy CONT
3529 and pdifcheck
3530
3531 layer pdc pdccopy
3532 grow 85
3533 shrink 85
3534 shrink 85
3535 grow 85
3536 or pdccopy
3537 labels CONT
3538
3539 templayer mvpdccopy CONT
3540 and mvpdifcheck
3541
3542 layer mvpdc mvpdccopy
3543 grow 85
3544 shrink 85
3545 shrink 85
3546 grow 85
3547 or mvpdccopy
3548 labels CONT
3549
3550 templayer pccopy CONT
3551 and polycheck
3552
3553 layer pc pccopy
3554 grow 85
3555 shrink 85
3556 shrink 85
3557 grow 85
3558 or pccopy
3559 labels CONT
3560
3561 templayer nsccopy CONT
3562 and nsubcheck
3563
3564 layer nsc nsccopy
3565 grow 85
3566 shrink 85
3567 shrink 85
3568 grow 85
3569 or nsccopy
3570 labels CONT
3571
3572 templayer mvnsccopy CONT
3573 and mvnsubcheck
3574
3575 layer mvnsc mvnsccopy
3576 grow 85
3577 shrink 85
3578 shrink 85
3579 grow 85
3580 or mvnsccopy
3581 labels CONT
3582
3583 templayer psccopy CONT
3584 and psubcheck
3585
3586 layer psc psccopy
3587 grow 85
3588 shrink 85
3589 shrink 85
3590 grow 85
3591 or psccopy
3592 labels CONT
3593
3594 templayer mvpsccopy CONT
3595 and mvpsubcheck
3596
3597 layer mvpsc mvpsccopy
3598 grow 85
3599 shrink 85
3600 shrink 85
3601 grow 85
3602 or mvpsccopy
3603 labels CONT
3604
3605 # Find contacts not covered in
3606 # metal and pull them into the
3607 # next layer up
3608
3609 templayer gencont CONT
3610 and LI
3611 and-not DIFF,TAP
3612 and-not POLY
3613 and-not DIODE
3614 and-not nsubcheck
3615 and-not psubcheck
3616 and-not mvnsubcheck
3617 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3618 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3619 copyup CONT,LI
3620
3621 templayer barecont CONT
3622 and-not LI
3623 and-not nsubcheck
3624 and-not psubcheck
3625 and-not mvnsubcheck
3626 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3627 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3628 copyup CONT
3629
3630 layer glass GLASS,PADTXT,PADPIN
3631 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3632 variants (vendor)
3633 labels PADTXT port
3634 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3635 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3636 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3637 labels PADPIN port
3638
3639 templayer boundary BOUND,STDCELL,PADCELL
3640 boundary
3641
3642 layer comment LVSTEXT
3643 labels LVSTEXT text
3644
3645 layer comment TTEXT
3646 labels TTEXT text
3647
3648 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3649 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3650
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3651 layer obsactive FILLOBSFOM
3652
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3653# MOS Varactor
3654
3655 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3656 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3657 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3658 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3659 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3660 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3661 # NOTE: Else forms a varactor that is not in the vendor netlist.
3662 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3663 labels POLY
3664
3665 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3666 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3667 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3668 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3669 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3670 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3671 labels POLY
3672
3673 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3674 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3675 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3676 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3677 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3678 labels POLY
3679
3680 calma NWELL 64 20
3681 calma DIFF 65 20
3682 calma DNWELL 64 18
3683 calma PWRES 64 13
3684 calma TAP 65 44
3685 # LVTN
3686 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3687 # HVTR
3688 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3689 # HVTP
3690 calma HVTP 78 44
3691 # SONOS (TUNM)
3692 calma SONOS 80 20
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3693 # NSDM (NPLUS)
3694 calma NSDM 93 44
3695 # PSDM (PPLUS)
3696 calma PSDM 94 20
3697 # HVI (THKOX)
3698 calma HVI 75 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3699 # NPC
3700 calma NPC 95 20
3701 # P+ POLY MASK
3702 calma RPM 86 20
3703 calma URPM 79 20
3704 calma LDNTM 11 44
3705 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3706 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3707 calma POLYRES 66 13
3708 # Diffusion resistor ID mark
3709 calma DIFFRES 65 13
3710 calma POLY 66 20
3711 calma POLYMOD 66 83
3712 # Diode ID mark
3713 calma DIODE 81 23
3714 # Bipolar NPN mark
3715 calma NPNID 82 20
3716 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3717 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3718 # Capacitor ID
3719 calma CAPID 82 64
3720 # Core area ID mark
3721 calma COREID 81 2
3722 # Standard cell ID mark
3723 calma STDCELL 81 4
3724 # Padframe cell ID mark
3725 calma PADCELL 81 3
3726 # Seal ring ID mark
3727 calma SEALID 81 1
3728 # Low tap density ID mark
3729 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3730 # ESD area ID
3731 calma ESDID 81 19
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3732
3733 # LICON
3734 calma CONT 66 44
3735 calma LI 67 20
3736 calma MCON 67 44
3737
3738 calma MET1 68 20
3739 calma VIA1 68 44
3740 calma MET2 69 20
3741 calma VIA2 69 44
3742 calma MET3 70 20
3743#ifdef METAL5
3744 calma VIA3 70 44
3745 calma MET4 71 20
3746 calma VIA4 71 44
3747 calma MET5 72 20
3748#endif
3749#ifdef REDISTRIBUTION
3750 calma RDL 74 20
3751#endif
3752 calma GLASS 76 20
3753
3754 calma SUBPIN 64 59
3755 calma PADPIN 76 5
3756 calma DIFFPIN 65 6
3757 calma TAPPIN 65 5
3758 calma WELLPIN 64 5
3759 calma LIPIN 67 5
3760 calma POLYPIN 66 5
3761 calma MET1PIN 68 5
3762 calma MET2PIN 69 5
3763 calma MET3PIN 70 5
3764#ifdef METAL5
3765 calma MET4PIN 71 5
3766 calma MET5PIN 72 5
3767#endif
3768#ifdef REDISTRIBUTION
3769 calma RDLPIN 74 5
3770#endif
3771
3772 calma LIRES 67 13
3773 calma MET1RES 68 13
3774 calma MET2RES 69 13
3775 calma MET3RES 70 13
3776#ifdef METAL5
3777 calma MET4RES 71 13
3778 calma MET5RES 72 13
3779#endif
3780
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3781 calma LIFILL 56 28
3782 calma MET1FILL 36 28
3783 calma MET2FILL 41 28
3784 calma MET3FILL 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3785#ifdef METAL5
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3786 calma MET4FILL 51 28
3787 calma MET5FILL 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3788#endif
3789
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3790 calma POLYSHORT 66 15
3791 calma LISHORT 67 15
3792 calma MET1SHORT 68 15
3793 calma MET2SHORT 69 15
3794 calma MET3SHORT 70 15
3795#ifdef METAL5
3796 calma MET4SHORT 71 15
3797 calma MET5SHORT 72 15
3798#endif
3799
3800 calma SUBTXT 122 16
3801 calma PADTXT 76 16
3802 calma DIFFTXT 65 16
3803 calma POLYTXT 66 16
3804 calma WELLTXT 64 16
3805 calma LITXT 67 16
3806 calma MET1TXT 68 16
3807 calma MET2TXT 69 16
3808 calma MET3TXT 70 16
3809#ifdef METAL5
3810 calma MET4TXT 71 16
3811 calma MET5TXT 72 16
3812#endif
3813#ifdef REDISTRIBUTION
3814 calma RDLPIN 74 16
3815#endif
3816
3817 calma BOUND 235 4
3818
3819 calma LVSTEXT 83 44
3820
3821#ifdef (MIM)
3822 calma CAPM 89 44
3823 calma CAPM2 97 44
3824#endif (MIM)
3825
3826 calma FILLOBSM1 62 24
3827 calma FILLOBSM2 105 52
3828 calma FILLOBSM3 107 24
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3829 calma FILLOBSM4 112 4
3830 calma FILLOBSFOM 22 24
3831 calma FILLOBSPOLY 33 24
3832
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3833 calma FOMFILL 23 28
3834 calma POLYFILL 28 28
3835 calma LIFILL 56 28
3836 calma MET1FILL 36 28
3837 calma MET2FILL 41 28
3838 calma MET3FILL 34 28
3839 calma MET4FILL 51 28
3840 calma MET5FILL 59 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3841
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3842#-----------------------------------------------------------------------
3843
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3844style rdlimport
3845 # This style is for reading shapes generated with the RDL layers
3846
3847 scalefactor 10 nanometers
3848 gridlimit 5
3849
3850 options ignore-unknown-layer-labels no-reconnect-labels
3851
3852 layer mrdl RDL
3853 layer mrdlc RDLC
3854
3855 calma RDL 10 0
3856 calma RDLC 20 0
3857
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3858end
3859
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3860#-----------------------------------------------------
3861# Digital flow maze router cost parameters
3862#-----------------------------------------------------
3863
3864mzrouter
3865end
3866
3867#-----------------------------------------------------
3868# Vendor DRC rules
3869#-----------------------------------------------------
3870
3871drc
3872
3873 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3874 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3875 cifstyle drc
3876
3877 variants (fast),(full)
3878
3879#-----------------------------
3880# DNWELL
3881#-----------------------------
3882
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3883 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
3884 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3885 spacing dnwell allnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3886 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3887
3888 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3889 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3890 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3891 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3892 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3893
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3894 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
3895 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3896 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3897
3898#-----------------------------
3899# NWELL
3900#-----------------------------
3901
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3902 width allnwell 840 "N-well width < %d (nwell.1)"
3903 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3904
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3905 variants (full)
3906 cifmaxwidth nwell_missing_tap 0 bend_illegal \
3907 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]3908
3909 cifspacing mvnwell lvnwell 2000 touching_illegal \
3910 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
3911 cifspacing mvnwell mvnwell 2000 touching_ok \
3912 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3913 variants (fast),(full)
3914
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3915#-----------------------------
3916# DIFF
3917#-----------------------------
3918
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3919 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3920 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3921 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3922 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3923
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3924 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
3925 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
3926 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
3927 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
3928 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
3929 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3930 spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3931 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3932 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3933 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3934 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3935 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3936 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3937 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3938 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3939 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3940 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3941 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3942 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3943 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3944 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3945 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3946 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3947 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3948 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3949 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3950 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3951 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3952 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3953 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3954 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3955 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3956 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3957 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3958 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3959 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]3960
3961variants (full)
3962 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
3963 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
3964variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3965
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3966 spacing allnfets allpactivenonfet 270 touching_illegal \
3967 "nFET cannot abut P-diffusion (diff/tap.3)"
3968 spacing allpfets allnactivenonfet 270 touching_illegal \
3969 "pFET cannot abut N-diffusion (diff/tap.3)"
3970
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3971 # Butting junction rules
3972 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3973 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3974 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3975 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3976 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3977 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3978 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3979 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3980
3981 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3982 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3983 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3984 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3985 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3986 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3987 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3988 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
3989
3990 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]3991 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
3992 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
3993
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]3994 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
3995 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
3996
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]3997 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3998
3999 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4000 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4001
4002 # Latchup rules
4003 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4004 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4005 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4006 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4007 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4008 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4009
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4010 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4011
4012#-----------------------------
4013# POLY
4014#-----------------------------
4015
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4016 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
4017 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4018
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4019 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]4020 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4021 75 corner_ok allfets \
4022 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4023 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4024 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4025 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4026 overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4027 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4028 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4029 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4030 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
4031 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4032 rect_only allfets "No bends in transistors (poly.11)"
4033 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4034 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4035 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4036 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4037 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4038
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4039 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \
4040 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
4041 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
4042 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
4043 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \
4044 "Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)"
4045
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4046 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4047
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4048#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4049# HVTP
4050#--------------------------------------------------------------------
4051
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4052 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4053 360 touching_illegal \
4054 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
4055
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4056 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4057 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
4058
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4059#--------------------------------------------------------------------
4060# LVTN
4061#--------------------------------------------------------------------
4062
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4063 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
4064 allfetsnolvt 360 touching_illegal \
4065 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4066
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4067 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4068 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4069 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4070
4071 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4072 edge4way allfetsnolvt allactivenonfet 415 \
4073 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
4074 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4075
4076#--------------------------------------------------------------------
4077# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4078#--------------------------------------------------------------------
4079
4080# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4081
4082#--------------------------------------------------------------------
4083# CONT (LICON, contact between poly/diff and LI)
4084#--------------------------------------------------------------------
4085
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4086 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4087 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4088 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4089 width psc/li 170 "P-tap contact width < %d (licon.1)"
4090 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4091 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4092 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4093
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4094 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4095 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4096 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4097
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4098 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4099 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4100 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4101 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4102 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4103 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4104
4105 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4106 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4107 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4108 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4109 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4110 "Diffusion contact spacing < %d (licon.2)"
4111 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4112
4113 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4114 "poly contact spacing to diffusion < %d (licon.14)"
4115 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4116 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4117
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4118 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4119 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4120 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4121 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4122 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4123 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4124 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4125 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4126 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4127 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4128 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4129 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4130
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4131 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4132 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4133 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4134 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4135 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4136 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4137 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4138 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4139 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4140
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4141 spacing psc/a allnactivenontap 60 touching_illegal \
4142 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4143 spacing nsc/a allpactivenontap 60 touching_illegal \
4144 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4145
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4146 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4147 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4148 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4149 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4150 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4151 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4152 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4153 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4154 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4155
4156 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4157 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4158 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4159 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4160
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4161 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4162 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4163 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4164 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4165 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4166 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4167 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4168 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4169
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4170 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4171 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4172 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4173 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4174
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4175 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4176 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4177 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4178 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4179 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4180 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4181 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4182 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4183
4184 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4185 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4186 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4187 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4188
4189 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4190 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4191 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4192 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4193
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4194 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4195
4196#-------------------------------------------------------------
4197# LI - Local interconnect layer
4198#-------------------------------------------------------------
4199
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4200variants *
4201
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4202 width *li 170 "Local interconnect width < %d (li.1)"
4203 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4204
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4205 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4206 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4207
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4208 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4209 # no special layers for the contacts in core cells, so they must be included
4210 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4211 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4212 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4213
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4214 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4215 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4216
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4217 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4218 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4219
4220 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4221 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4222 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4223
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4224 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4225
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4226 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4227 angles coreli 45 \
4228 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4229
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4230#-------------------------------------------------------------
4231# MCON - Contact between local interconnect and metal1
4232#-------------------------------------------------------------
4233
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4234 width mcon/m1 170 "mcon.width < %d (mcon.1)"
4235 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4236
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4237 exact_overlap mcon/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4238
4239#-------------------------------------------------------------
4240# METAL1 -
4241#-------------------------------------------------------------
4242
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4243 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4244 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4245 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4246
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4247 surround mcon/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4248 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4249 surround mcon/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4250 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4251
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4252 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4253
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4254variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4255 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4256 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4257 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4258 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4259
4260variants (full)
4261 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4262 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4263
4264 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4265 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4266variants *
4267
4268#--------------------------------------------------
4269# VIA1
4270#--------------------------------------------------
4271
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4272 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4273 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4274 surround v1/m1 *m1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4275 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4276 surround v1/m2 *m2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4277 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4278
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4279 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4280
4281#--------------------------------------------------
4282# METAL2 -
4283#--------------------------------------------------
4284
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4285 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4286 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4287 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4288
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4289 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4290
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4291variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4292 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4293 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4294 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4295 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4296
4297variants (full)
4298 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4299 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4300
4301 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4302 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4303variants *
4304
4305#--------------------------------------------------
4306# VIA2
4307#--------------------------------------------------
4308
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4309 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4310
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4311 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4312
4313 surround v2/m2 *m2 45 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4314 "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
4315 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4316
4317 exact_overlap v2/m2
4318
4319#--------------------------------------------------
4320# METAL3 -
4321#--------------------------------------------------
4322
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4323 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4324 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4325 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4326
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4327 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4328
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4329variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4330 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4331 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4332 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4333 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4334variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4335 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4336 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4337variants *
4338
4339
4340#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4341#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4342#--------------------------------------------------
4343# VIA3 - Requires METAL5 Module
4344#--------------------------------------------------
4345
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4346 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
4347 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4348 surround v3/m3 *m3 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4349 "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]4350 surround v3/m4 *m4 5 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4351 "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4352
4353 exact_overlap v3/m3
4354
4355#-----------------------------
4356# METAL4 - METAL4 Module
4357#-----------------------------
4358
4359variants *
4360
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4361 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4362 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4363 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4364
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4365 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4366
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4367variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4368 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4369 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4370 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4371 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4372variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4373 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4374 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4375variants *
4376
4377#--------------------------------------------------
4378# VIA4 - Requires METAL5 Module
4379#--------------------------------------------------
4380
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4381 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
4382 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4383 surround v4/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4384 "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4385
4386 exact_overlap v4/m4
4387
4388#-----------------------------
4389# METAL5 - METAL5 Module
4390#-----------------------------
4391
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4392 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4393 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4394 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4395
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4396 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4397
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4398#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4399#endif (METAL5)
4400
4401#ifdef REDISTRIBUTION
4402
4403variants (full)
4404
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4405 width metrdl 10000 "RDL width < %d (rdl.1)"
4406 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4407 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
4408 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4409
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4410variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4411
4412#endif (REDISTRIBUTION)
4413
4414#--------------------------------------------------
4415# NMOS, PMOS
4416#--------------------------------------------------
4417
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4418 edge4way *poly allfetsstd 420 allfets 0 0 \
4419 "Transistor width < %d (diff/tap.2)"
4420 edge4way *poly allfetsspecial 360 allfets 0 0 \
4421 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4422 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4423 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4424 edge4way *poly ppu 140 allfets 0 0 \
4425 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4426
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4427 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4428 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4429
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4430 spacing allpolynonfet,polyfill *nsd 55 corner_ok varactor \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4431 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4432 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvaractor \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4433 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4434
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4435 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4436 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4437 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4438 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4439 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4440 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4441 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4442 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4443
4444 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4445 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4446 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4447
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4448 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4449 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4450
4451 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4452 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4453 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4454
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4455 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4456 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4457
4458 # Minimum length of MV FETs. Note that this is larger than the minimum
4459 # width (0.29um), so an edge rule is required
4460
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4461 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4462 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4463
4464 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4465 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4466
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4467 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4468 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4469
4470#--------------------------------------------------
4471# mrp1 (N+ poly resistor)
4472#--------------------------------------------------
4473
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4474 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4475
4476#--------------------------------------------------
4477# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4478# uhrpoly (P+ poly resistor, 2kOhm/sq)
4479#--------------------------------------------------
4480
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4481 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4482 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4483 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4484
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4485 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4486 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4487
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4488 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4489 "Poly resistor spacing to poly < %d (poly.9)"
4490
4491 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4492 "Poly resistor spacing to poly < %d (poly.9)"
4493
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4494 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4495 "Poly resistor spacing to poly < %d (poly.9)"
4496
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4497 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4498 "Poly resistor spacing to diffusion < %d (poly.9)"
4499
4500#------------------------------------
4501# nsonos
4502#------------------------------------
4503
4504variants (full)
4505 cifmaxwidth bbox_missing 0 bend_illegal \
4506 "SONOS transistor must be in cell with abutment box (tunm.8)"
4507variants (fast),(full)
4508
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4509#------------------------------------
4510# MOS Varactor device rules
4511#------------------------------------
4512
4513 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4514 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4515
4516 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4517 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4518
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4519 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4520 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4521
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4522variants (full)
4523 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4524 "N-well overlap of varactor poly < 0.15um (varac.5)"
4525
4526 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4527 "Varactor N-well must not contain P+ diffusion (varac.7)"
4528variants (fast),(full)
4529
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4530#ifdef MIM
4531#-----------------------------------------------------------
4532# MiM CAP (CAPM) -
4533#-----------------------------------------------------------
4534
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4535 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4536 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4537 spacing *mimcap via3/m3 80 touching_illegal \
4538 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4539 surround *mimcc *mimcap 80 absence_illegal \
4540 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4541 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4542
4543 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4544 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4545 spacing via2 *mimcap 100 touching_illegal \
4546 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4547 spacing *mimcap *metal3/m3 500 surround_ok \
4548 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4549
4550variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4551 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4552 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4553variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4554
4555 # MiM cap contact rules (VIA3)
4556
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4557 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4558 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4559 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4560 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4561 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4562
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4563 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4564 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4565 spacing *mimcap2 via4/m4 10 touching_illegal \
4566 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4567 surround *mim2cc *mimcap2 10 absence_illegal \
4568 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4569 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4570
4571 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4572 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards5ad4eb42020-11-27 10:58:22 -0500[diff] [blame]4573 spacing via3,mimcc *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4574 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4575 spacing *mimcap2 *metal4/m4 500 surround_ok \
4576 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4577
4578variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4579 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4580 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4581variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4582
4583 # MiM cap contact rules (VIA4)
4584
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4585 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4586 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4587 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4588 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4589 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4590 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4591
4592#endif (MIM)
4593
4594#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4595# HVNTM
4596#----------------------------
4597variants (full)
4598 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4599 "HVNTM spacing < %d (hvntm.2)"
4600variants (fast),(full)
4601
4602#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4603# End DRC style
4604#----------------------------
4605
4606end
4607
4608#----------------------------
4609# LEF format definitions
4610#----------------------------
4611
4612lef
4613
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4614 masterslice pwell pwell PWELL substrate
4615 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4616
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4617 routing li li1 LI1 LI li
4618
4619 routing m1 met1 MET1 m1
4620 routing m2 met2 MET2 m2
4621 routing m3 met3 MET3 m3
4622#ifdef METAL5
4623 routing m4 met4 MET4 m4
4624 routing m5 met5 MET5 m5
4625#endif (METAL5)
4626#ifdef REDISTRIBUTION
4627 routing mrdl met6 MET6 m6 MRDL METRDL
4628#endif
4629
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4630 cut mcon mcon MCON Mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4631 cut m2c via via1 VIA VIA1 cont2 via12
4632 cut m3c via2 VIA2 cont3 via23
4633#ifdef METAL5
4634 cut via3 via3 VIA3 cont4 via34
4635 cut via4 via4 VIA4 cont5 via45
4636#endif (METAL5)
4637
4638 obs obsli li1
4639 obs obsm1 met1
4640 obs obsm2 met2
4641 obs obsm3 met3
4642
4643#ifdef METAL5
4644 obs obsm4 met4
4645 obs obsm5 met5
4646#endif (METAL5)
4647#ifdef REDISTRIBUTION
4648 obs obsmrdl met6
4649#endif
4650
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4651 # NOTE: obsmcon only used with li1, not obsli.
4652 obs obsmcon mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4653
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]4654 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
4655 obs obsm1 via
4656 obs obsm2 via2
4657#ifdef METAL5
4658 obs obsm3 via3
4659 obs obsm4 via4
4660#endif (METAL5)
4661
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4662end
4663
4664#-----------------------------------------------------
4665# Device and Parasitic extraction
4666#-----------------------------------------------------
4667
4668
4669extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4670 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4671 cscale 1
4672 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
4673 # dimensions must be in units of microns in the extract file.
4674 # Use extract style "ngspice(si)" to override this and produce
4675 # a file with SI units for length/area.
4676
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4677 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4678 lambda 1E6
4679 variants (si)
4680 lambda 1.0
4681 variants *
4682
4683 units microns
4684 step 7
4685 sidehalo 2
4686
4687 # NOTE: MiM cap layers have been purposely put out of order,
4688 # may want to reconsider.
4689
4690 planeorder dwell 0
4691 planeorder well 1
4692 planeorder active 2
4693 planeorder locali 3
4694 planeorder metal1 4
4695 planeorder metal2 5
4696 planeorder metal3 6
4697#ifdef METAL5
4698 planeorder metal4 7
4699 planeorder metal5 8
4700#ifdef REDISTRIBUTION
4701 planeorder metali 9
4702 planeorder block 10
4703 planeorder comment 11
4704 planeorder cap1 12
4705 planeorder cap2 13
4706#else (!REDISTRIBUTION)
4707 planeorder block 9
4708 planeorder comment 10
4709 planeorder cap1 11
4710 planeorder cap2 12
4711#endif (!REDISTRIBUTION)
4712#else (!METAL5)
4713#ifdef REDISTRIBUTION
4714 planeorder metali 7
4715 planeorder block 8
4716 planeorder comment 9
4717 planeorder cap1 10
4718 planeorder cap2 11
4719#else (!REDISTRIBUTION)
4720 planeorder block 7
4721 planeorder comment 8
4722 planeorder cap1 9
4723 planeorder cap2 10
4724#endif (!REDISTRIBUTION)
4725#endif (!METAL5)
4726
4727 height dnwell -0.1 0.1
4728 height nwell,pwell 0.0 0.2062
4729 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4730 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4731 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4732 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4733 height alldiffcont 0.3262 0.61
4734 height pc 0.5062 0.43
4735 height allli 0.9361 0.10
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4736 height mcon 1.0361 0.34
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4737 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4738 height m1fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4739 height v1 1.7361 0.27
4740 height allm2 2.0061 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4741 height m2fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4742 height v2 2.3661 0.42
4743 height allm3 2.7861 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4744 height m3fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4745#ifdef METAL5
4746 height v3 3.6311 0.39
4747 height allm4 4.0211 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4748 height m4fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4749 height v4 4.8661 0.505
4750 height allm5 5.3711 1.26
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4751 height m5fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4752 height mimcap 2.4661 0.2
4753 height mimcap2 3.7311 0.2
4754 height mimcc 2.6661 0.12
4755 height mim2cc 3.9311 0.09
4756#ifdef REDISTRIBUTION
4757 height mrdlc 6.6311 5.2523
4758 height mrdl 11.8834 4.0
4759#endif (!REDISTRIBUTION)
4760#endif (!METAL5)
4761
4762 # Antenna check parameters
4763 # Note that checks w/diode diffusion are not modeled
4764 model partial
4765 antenna poly sidewall 50 none
4766 antenna allcont surface 3 none
4767 antenna li sidewall 75 0 450
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4768 antenna mcon surface 3 0 18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4769 antenna m1,m2,m3 sidewall 400 2600 400
4770 antenna v1 surface 3 0 18
4771 antenna v2 surface 6 0 36
4772#ifdef METAL5
4773 antenna m4,m5 sidewall 400 2600 400
4774 antenna v3,v4 surface 6 0 36
4775#endif (METAL5)
4776
4777 tiedown alldiffnonfet
4778
4779 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
4780
4781# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
4782
4783# Resistances are in milliohms per square
4784# Optional 3rd argument is the corner adjustment fraction
4785# Device values come from trtc.cor (typical corner)
4786 resist (dnwell)/dwell 2200000
4787 resist (pwell)/well 3050000
4788 resist (nwell)/well 1700000
4789 resist (rpw)/well 3050000 0.5
4790 resist (*ndiff,nsd)/active 120000
4791 resist (*pdiff,*psd)/active 197000
4792 resist (*mvndiff,mvnsd)/active 114000
4793 resist (*mvpdiff,*mvpsd)/active 191000
4794
4795 resist ndiffres/active 120000 0.5
4796 resist pdiffres/active 197000 0.5
4797 resist mvndiffres/active 114000 0.5
4798 resist mvpdiffres/active 191000 0.5
4799 resist mrp1/active 48200 0.5
4800 resist xhrpoly/active 319800 0.5
4801 resist uhrpoly/active 2000000 0.5
4802
4803 resist (allpolynonres)/active 48200
4804 resist rmp/active 48200
4805
4806 resist (allli)/locali 12200
4807 resist (allm1)/metal1 125
4808 resist (allm2)/metal2 125
4809 resist (allm3)/metal3 47
4810#ifdef METAL5
4811 resist (allm4)/metal4 47
4812 resist (allm5)/metal5 29
4813#endif (METAL5)
4814#ifdef REDISTRIBUTION
4815 resist mrdl/metali 5
4816#endif (REDISTRIBUTION)
4817
4818 contact ndc,nsc 15000
4819 contact pdc,psc 15000
4820 contact mvndc,mvnsc 15000
4821 contact mvpdc,mvpsc 15000
4822 contact pc 15000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4823 contact mcon 152000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4824 contact m2c 4500
4825 contact m3c 3410
4826#ifdef METAL5
4827#ifdef MIM
4828 contact mimcc 4500
4829 contact mim2cc 3410
4830#endif (MIM)
4831 contact via3 3410
4832 contact via4 380
4833#endif (METAL5)
4834#ifdef REDISTRIBUTION
4835 contact mrdlc 6
4836#endif (REDISTRIBUTION)
4837
4838#-------------------------------------------------------------------------
4839# Parasitic capacitance values: Use document (...)
4840#-------------------------------------------------------------------------
4841# This uses the new "default" definitions that determine the intervening
4842# planes from the planeorder stack, take care of the reflexive sideoverlap
4843# definitions, and generally clean up the section and make it more readable.
4844#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4845# Also uses "units microns" statement. All values are taken from the
4846# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
4847# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4848#-------------------------------------------------------------------------
4849# Remember that device capacitances to substrate are taken care of by the
4850# models. Thus, active and poly definitions ignore all "fet" types.
4851# fet types are excluded when computing parasitic capacitance to
4852# active from layers above them because poly is a shield; fet types are
4853# included for parasitics from layers above to poly. Resistor types
4854# should be removed from all parasitic capacitance calculations, or else
4855# they just create floating caps. Technically, the capacitance probably
4856# should be split between the two terminals. Unsure of the correct model.
4857#-------------------------------------------------------------------------
4858
4859#n-well
4860# NOTE: This value not found in PEX files
4861defaultareacap nwell well 120
4862
4863#n-active
4864# Rely on device models to capture *ndiff area cap
4865# Do not extract parasitics from resistors
4866# defaultareacap allnactivenonfet active 790
4867# defaultperimeter allnactivenonfet active 280
4868
4869#p-active
4870# Rely on device models to capture *pdiff area cap
4871# Do not extract parasitics from resistors
4872# defaultareacap allpactivenonfet active 810
4873# defaultperimeter allpactivenonfet active 300
4874
4875#poly
4876# Do not extract parasitics from resistors
4877# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4878# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4879# defaultperimeter allpolynonfet active 57
4880
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4881 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4882 defaultareacap *poly active nwell,obswell,pwell well 106
4883 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4884
4885#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4886 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4887 defaultareacap allli locali nwell,obswell,pwell well 37
4888 defaultperimeter allli locali nwell,obswell,pwell well 55
4889 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4890
4891#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4892 defaultoverlap allli locali allactivenonfet active 37
4893 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4894
4895#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4896 defaultoverlap allli locali allpolynonres active 94
4897 defaultsideoverlap allli locali allpolynonres active 52
4898 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4899
4900#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4901 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4902 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
4903 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4904 defaultoverlap allm1 metal1 nwell well 26
4905
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4906#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4907 defaultoverlap allm1 metal1 allactivenonfet active 26
4908 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4909
4910#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4911 defaultoverlap allm1 metal1 allpolynonres active 45
4912 defaultsideoverlap allm1 metal1 allpolynonres active 47
4913 defaultsideoverlap *poly active allm1 metal1 17
4914
4915#metal1->locali
4916 defaultoverlap allm1 metal1 allli locali 114
4917 defaultsideoverlap allm1 metal1 allli locali 59
4918 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4919
4920#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4921 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4922 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
4923 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
4924 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4925
4926#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4927 defaultoverlap allm2 metal2 allactivenonfet active 17
4928 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4929
4930#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4931 defaultoverlap allm2 metal2 allpolynonres active 24
4932 defaultsideoverlap allm2 metal2 allpolynonres active 41
4933 defaultsideoverlap *poly active allm2 metal2 11
4934
4935#metal2->locali
4936 defaultoverlap allm2 metal2 allli locali 38
4937 defaultsideoverlap allm2 metal2 allli locali 46
4938 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4939
4940#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4941 defaultoverlap allm2 metal2 allm1 metal1 134
4942 defaultsideoverlap allm2 metal2 allm1 metal1 67
4943 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4944
4945#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4946 defaultsidewall allm3 metal3 63
4947 defaultoverlap allm3 metal3 nwell well 12
4948 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
4949 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4950
4951#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4952 defaultoverlap allm3 metal3 allactive active 12
4953 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4954
4955#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4956 defaultoverlap allm3 metal3 allpolynonres active 16
4957 defaultsideoverlap allm3 metal3 allpolynonres active 44
4958 defaultsideoverlap *poly active allm3 metal3 9
4959
4960#metal3->locali
4961 defaultoverlap allm3 metal3 allli locali 21
4962 defaultsideoverlap allm3 metal3 allli locali 47
4963 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4964
4965#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4966 defaultoverlap allm3 metal3 allm1 metal1 35
4967 defaultsideoverlap allm3 metal3 allm1 metal1 55
4968 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4969
4970#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4971 defaultoverlap allm3 metal3 allm2 metal2 86
4972 defaultsideoverlap allm3 metal3 allm2 metal2 70
4973 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4974
4975#ifdef METAL5
4976#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4977 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4978# defaultareacap alltopm metal4 well 6
4979 areacap allm4/m4 8
4980 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4981 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4982
4983#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4984 defaultoverlap allm4 metal4 allactivenonfet active 8
4985 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4986
4987#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4988 defaultoverlap allm4 metal4 allpolynonres active 10
4989 defaultsideoverlap allm4 metal4 allpolynonres active 38
4990 defaultsideoverlap *poly active allm4 metal4 6
4991
4992#metal4->locali
4993 defaultoverlap allm4 metal4 allli locali 12
4994 defaultsideoverlap allm4 metal4 allli locali 40
4995 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4996
4997#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4998 defaultoverlap allm4 metal4 allm1 metal1 15
4999 defaultsideoverlap allm4 metal4 allm1 metal1 43
5000 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5001
5002#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5003 defaultoverlap allm4 metal4 allm2 metal2 20
5004 defaultsideoverlap allm4 metal4 allm2 metal2 46
5005 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5006
5007#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5008 defaultoverlap allm4 metal4 allm3 metal3 84
5009 defaultsideoverlap allm4 metal4 allm3 metal3 71
5010 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5011
5012#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5013 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5014# defaultareacap allm5 metal5 well 6
5015 areacap allm5/m5 6
5016 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5017 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5018
5019#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5020 defaultoverlap allm5 metal5 allactivenonfet active 6
5021 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5022
5023#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5024 defaultoverlap allm5 metal5 allpolynonres active 7
5025 defaultsideoverlap allm5 metal5 allpolynonres active 40
5026 defaultsideoverlap *poly active allm5 metal5 6
5027
5028#metal5->locali
5029 defaultoverlap allm5 metal5 allli locali 8
5030 defaultsideoverlap allm5 metal5 allli locali 41
5031 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5032
5033#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5034 defaultoverlap allm5 metal5 allm1 metal1 9
5035 defaultsideoverlap allm5 metal5 allm1 metal1 43
5036 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5037
5038#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5039 defaultoverlap allm5 metal5 allm2 metal2 11
5040 defaultsideoverlap allm5 metal5 allm2 metal2 46
5041 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5042
5043#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5044 defaultoverlap allm5 metal5 allm3 metal3 20
5045 defaultsideoverlap allm5 metal5 allm3 metal3 54
5046 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5047
5048#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5049 defaultoverlap allm5 metal5 allm4 metal4 68
5050 defaultsideoverlap allm5 metal5 allm4 metal4 83
5051 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5052#endif (METAL5)
5053
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5054#ifdef REDISTRIBUTION
5055#endif (REDISTRIBUTION)
5056
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5057# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5058
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5059variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5060
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5061 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5062 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5063 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5064 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5065 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5066 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5067 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5068 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5069 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5070 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5071 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5072 a1=as p1=ps a2=ad p2=pd
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5073 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5074 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5075 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5076
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5077 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5078 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5079 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5080 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5081 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5082 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5083 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5084 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5085 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5086 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5087 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5088 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5089 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5090 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5091 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5092 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5093 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5094 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5095 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5096 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5097 *mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5098
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5099 # Bipolars
5100 device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
5101 device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
5102 device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
5103
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5104 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5105 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5106 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5107 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5108
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5109 # Extended drain devices (must appear before the regular devices)
5110 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5111 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5112 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5113 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5114 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5115 pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5116
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5117 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5118 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5119 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5120 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5121 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5122 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5123 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5124 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5125 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5126 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5127 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5128 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5129 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5130 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5131 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5132
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5133 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5134 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5135 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5136 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5137#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5138 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5139 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5140#endif (METAL5)
5141
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5142 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5143 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5144 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5145 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5146 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5147 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5148 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5149 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5150 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5151 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5152 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5153 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5154 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5155 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5156 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5157 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5158 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5159 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5160 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5161 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5162 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5163 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5164 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5165 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5166
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5167 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5168 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5169 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5170 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5171 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5172 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5173 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5174 *mvndiff pwell,space/w error l=l w=w
5175 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5176 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5177
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5178 device resistor sky130_fd_pr__res_generic_po rmp *poly
5179 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5180
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5181 device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5182 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5183 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
5184 nwell a=area
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5185 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5186 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5187 device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5188 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5189
5190 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
5191 pwell,space/w a=area
5192 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
5193 pwell,space/w a=area
5194 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
5195 pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5196 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5197 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5198
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5199
5200#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5201 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5202 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5203#endif (MIM)
5204
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5205 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5206
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5207 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5208 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5209 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5210 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5211 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5212 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5213 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5214 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5215 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5216 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5217 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5218 pwell,space/w
5219
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5220 # Note that corenvar, corepvar are not considered devices, and extract as
5221 # parasitic capacitance instead (but cap values need to be added).
5222
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5223 # Extended drain devices (must appear before the regular devices)
5224 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5225 dnwell pwell,space/w error
5226 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5227 dnwell pwell,space/w error
5228 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5229 pwell,space/w nwell error
5230
5231 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5232 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5233 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5234 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5235 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5236
5237 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5238 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5239 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5240 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5241
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5242 device resistor sky130_fd_pr__res_generic_po rmp *poly
5243 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5244 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5245 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5246 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5247#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5248 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5249 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5250#endif (METAL5)
5251
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5252 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5253 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5254 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5255 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5256 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5257 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5258 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5259 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5260 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5261 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5262 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5263 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5264 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5265 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5266 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5267 device resistor mrdn_hv mvndiffres *mvndiff
5268 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5269 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5270
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5271 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5272 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5273 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5274 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5275
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5276 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5277 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5278 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5279 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5280
Tim Edwards1021f552020-09-11 17:37:51 -0400[diff] [blame]5281 device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
5282 device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5283 device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5284
5285#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5286 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5287 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5288#endif (MIM)
5289
5290end
5291
5292#-----------------------------------------------------
5293# Wiring tool definitions
5294#-----------------------------------------------------
5295
5296wiring
5297 # All wiring values are in nanometers
5298 scalefactor 10
5299
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5300 contact mcon 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5301 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5302 contact v2 280 m2 0 45 m3 25 0
5303#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5304 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5305 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5306#endif (METAL5)
5307
5308 contact pc 170 poly 50 80 li 0 80
5309 contact pdc 170 pdiff 40 60 li 0 80
5310 contact ndc 170 ndiff 40 60 li 0 80
5311 contact psc 170 psd 40 60 li 0 80
5312 contact nsc 170 nsd 40 60 li 0 80
5313
5314end
5315
5316#-----------------------------------------------------
5317# Plain old router. . .
5318#-----------------------------------------------------
5319
5320router
5321end
5322
5323#------------------------------------------------------------
5324# Plowing (restored in magic 8.2, need to fill this section)
5325#------------------------------------------------------------
5326
5327plowing
5328end
5329
5330#-----------------------------------------------------------------
5331# No special plot layers defined (use default PNM color choices)
5332#-----------------------------------------------------------------
5333
5334plot
5335 style pnm
5336 default
5337 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5338 draw fillblock4 no_color_at_all
5339 draw fomfill no_color_at_all
5340 draw polyfill no_color_at_all
5341 draw m1fill no_color_at_all
5342 draw m2fill no_color_at_all
5343 draw m3fill no_color_at_all
5344 draw m4fill no_color_at_all
5345 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5346 draw nwell cwell
5347end
5348