Fixing the `power_gating_pin`.
Updating sky130_fd_sc_hvl 0.0.1.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_085C_5v50.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_085C_5v50.lib.json
index 4d4043b..da5f3f6 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_085C_5v50.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_085C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_100C_5v50.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_100C_5v50.lib.json
index 77f5337..a4af37f 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_100C_5v50.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_100C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_150C_5v50.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_150C_5v50.lib.json
index 6130f54..c5bcc6e 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_150C_5v50.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_4v40.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_4v40.lib.json
index 46c6c00..7d5d7f3 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_4v40.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_4v95.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_4v95.lib.json
index fd75efe..15cadee 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_4v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_5v50_ccsnoise.lib.json
index 09fd392..388e4af 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_1v65.lib.json
index 850b017..86be40b 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_1v95.lib.json
index 3dd4225..622f9e4 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_3v00.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_3v00.lib.json
index 4b3d52a..8a54c98 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_3v00.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_150C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_150C_1v65.lib.json
index fa921df..b607f74 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_150C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v32.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v32.lib.json
index 43cb180..d7752e3 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v32.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v32.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v49.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v49.lib.json
index 6888ada..cd16c59 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v49.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v49.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v65_ccsnoise.lib.json
index 2b07d2c..c380dde 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v95.lib.json
index 73cd45f..fb00233 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__ss_n40C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__tt_025C_3v30.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__tt_025C_3v30.lib.json
index d22dab8..4eb0420 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__tt_025C_3v30.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__tt_025C_3v30.lib.json
@@ -6,18 +6,22 @@
"driver_waveform_rise": "ramp",
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1__tt_100C_3v30.lib.json b/cells/a21o/sky130_fd_sc_hvl__a21o_1__tt_100C_3v30.lib.json
index 0498a91..de4bc44 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1__tt_100C_3v30.lib.json
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_085C_5v50.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_085C_5v50.lib.json
index 4438125..eb128fb 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_085C_5v50.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_085C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_100C_5v50.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_100C_5v50.lib.json
index ba5009b..09ef078 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_100C_5v50.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_100C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_150C_5v50.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_150C_5v50.lib.json
index bbaaf54..6109d6e 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_150C_5v50.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_4v40.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_4v40.lib.json
index 848d375..683a1ff 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_4v40.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_4v95.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_4v95.lib.json
index 21660ff..18849fc 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_4v95.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_5v50_ccsnoise.lib.json
index f74bc12..007a535 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_1v65.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_1v65.lib.json
index 742610b..0e667d4 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_1v65.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_1v95.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_1v95.lib.json
index dabbcba..a5a904f 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_1v95.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_3v00.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_3v00.lib.json
index 3ee8b65..5c4728e 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_3v00.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_150C_1v65.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_150C_1v65.lib.json
index 135d724..994f453 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_150C_1v65.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v32.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v32.lib.json
index a008457..3af515b 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v32.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v32.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v49.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v49.lib.json
index 5c94d2f..77cb227 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v49.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v49.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v65_ccsnoise.lib.json
index dfe5608..15d182e 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v95.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v95.lib.json
index 946aafe..a38c476 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v95.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__ss_n40C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__tt_025C_3v30.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__tt_025C_3v30.lib.json
index c7187d9..038fd8f 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__tt_025C_3v30.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__tt_025C_3v30.lib.json
@@ -6,18 +6,22 @@
"driver_waveform_rise": "ramp",
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__tt_100C_3v30.lib.json b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__tt_100C_3v30.lib.json
index adb259b..a07996c 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__tt_100C_3v30.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_085C_5v50.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_085C_5v50.lib.json
index 3f15bdb..790002a 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_085C_5v50.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_085C_5v50.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_100C_5v50.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_100C_5v50.lib.json
index 7ff031b..7ca301e 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_100C_5v50.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_100C_5v50.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_150C_5v50.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_150C_5v50.lib.json
index 939ede6..0669637 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_150C_5v50.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_4v40.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_4v40.lib.json
index dce29b8..47c3f37 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_4v40.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_4v95.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_4v95.lib.json
index bc8d057..52f0df1 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_4v95.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_5v50_ccsnoise.lib.json
index c07a6e7..172fe58 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_1v65.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_1v65.lib.json
index 191e4cd..fea79fd 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_1v65.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_1v95.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_1v95.lib.json
index b676eba..91c038f 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_1v95.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_1v95.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_3v00.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_3v00.lib.json
index 4d9297c..55b81a1 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_3v00.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_150C_1v65.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_150C_1v65.lib.json
index 3975910..b35a198 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_150C_1v65.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v32.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v32.lib.json
index 3d47203..069a29e 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v32.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v32.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v49.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v49.lib.json
index 8753737..58b3843 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v49.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v49.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v65_ccsnoise.lib.json
index d408d62..0ae9d01 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v95.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v95.lib.json
index 25511cd..74e694f 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v95.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__ss_n40C_1v95.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__tt_025C_3v30.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__tt_025C_3v30.lib.json
index 5694398..27e9e8a 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__tt_025C_3v30.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__tt_025C_3v30.lib.json
@@ -6,18 +6,22 @@
"driver_waveform_rise": "ramp",
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1__tt_100C_3v30.lib.json b/cells/a22o/sky130_fd_sc_hvl__a22o_1__tt_100C_3v30.lib.json
index 37ce896..f58f2bb 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1__tt_100C_3v30.lib.json
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_085C_5v50.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_085C_5v50.lib.json
index fe72835..657f131 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_085C_5v50.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_085C_5v50.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_100C_5v50.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_100C_5v50.lib.json
index 200213b..5fb120a 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_100C_5v50.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_100C_5v50.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_150C_5v50.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_150C_5v50.lib.json
index 8f6e0df..1894ba6 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_150C_5v50.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_4v40.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_4v40.lib.json
index 93b290a..ea186fa 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_4v40.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_4v95.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_4v95.lib.json
index fc3496f..3a4f55d 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_4v95.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_5v50_ccsnoise.lib.json
index 7f91cef..88a6e34 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_1v65.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_1v65.lib.json
index 88bf47f..9e20ebc 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_1v65.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_1v95.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_1v95.lib.json
index b1678cd..7f4250c 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_1v95.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_1v95.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_3v00.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_3v00.lib.json
index a5530b6..5a8b97a 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_3v00.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_150C_1v65.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_150C_1v65.lib.json
index f9a2832..230b1f4 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_150C_1v65.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v32.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v32.lib.json
index 76437a9..9138136 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v32.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v32.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v49.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v49.lib.json
index efd482c..3f10140 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v49.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v49.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v65_ccsnoise.lib.json
index e1b19ea..fd8d1e8 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v95.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v95.lib.json
index dc4b266..510f78c 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v95.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__ss_n40C_1v95.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__tt_025C_3v30.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__tt_025C_3v30.lib.json
index f0ee145..972d0f5 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__tt_025C_3v30.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__tt_025C_3v30.lib.json
@@ -6,18 +6,22 @@
"driver_waveform_rise": "ramp",
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__tt_100C_3v30.lib.json b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__tt_100C_3v30.lib.json
index 943a1dc..ddb2123 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__tt_100C_3v30.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_085C_5v50.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_085C_5v50.lib.json
index 0963f81..dd36b66 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_085C_5v50.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_085C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_100C_5v50.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_100C_5v50.lib.json
index 0887707..753a853 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_100C_5v50.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_100C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_150C_5v50.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_150C_5v50.lib.json
index 40998bd..d0fbbc8 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_150C_5v50.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_4v40.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_4v40.lib.json
index 4b26494..d55f32d 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_4v40.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_4v95.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_4v95.lib.json
index 5aba155..d215c8d 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_4v95.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_5v50_ccsnoise.lib.json
index beb062a..bb318cc 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_1v65.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_1v65.lib.json
index 71060c4..54dee1c 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_1v65.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_1v95.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_1v95.lib.json
index a4b5946..bba5bdc 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_1v95.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_3v00.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_3v00.lib.json
index fd3b9b6..832e26d 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_3v00.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_150C_1v65.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_150C_1v65.lib.json
index 44c7725..f1176d3 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_150C_1v65.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v32.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v32.lib.json
index 00f2f9d..94320dd 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v32.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v32.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v49.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v49.lib.json
index ec6569f..7e446ae 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v49.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v49.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v65_ccsnoise.lib.json
index 2476eb7..8d276b6 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v95.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v95.lib.json
index 101f7db..d0a5120 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v95.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__ss_n40C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__tt_025C_3v30.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__tt_025C_3v30.lib.json
index 51ccb4b..360579b 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__tt_025C_3v30.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__tt_025C_3v30.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1__tt_100C_3v30.lib.json b/cells/and2/sky130_fd_sc_hvl__and2_1__tt_100C_3v30.lib.json
index e1a2e76..8aec43c 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1__tt_100C_3v30.lib.json
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_085C_5v50.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_085C_5v50.lib.json
index eee7d7e..ed73109 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_085C_5v50.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_085C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_100C_5v50.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_100C_5v50.lib.json
index b537430..f845471 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_100C_5v50.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_100C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_150C_5v50.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_150C_5v50.lib.json
index d38c0b9..20773d4 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_150C_5v50.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_4v40.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_4v40.lib.json
index b00056a..523f67b 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_4v40.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_4v95.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_4v95.lib.json
index 8c5e480..d95ab25 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_4v95.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_5v50_ccsnoise.lib.json
index edd9649..87fe397 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_1v65.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_1v65.lib.json
index b5a6163..cc31d82 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_1v65.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_1v95.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_1v95.lib.json
index ecaed9c..7c9f84f 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_1v95.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_3v00.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_3v00.lib.json
index 9603f82..8b93da4 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_3v00.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_150C_1v65.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_150C_1v65.lib.json
index 26fbf66..86c566d 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_150C_1v65.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v32.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v32.lib.json
index 0814ba3..a1c2889 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v32.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v32.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v49.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v49.lib.json
index f532b29..55395f7 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v49.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v49.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v65_ccsnoise.lib.json
index 4be81e9..5c44d25 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v95.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v95.lib.json
index c2d8cb5..2e22d07 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v95.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__ss_n40C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__tt_025C_3v30.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__tt_025C_3v30.lib.json
index 19cb88c..8a947ac 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__tt_025C_3v30.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__tt_025C_3v30.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1__tt_100C_3v30.lib.json b/cells/and3/sky130_fd_sc_hvl__and3_1__tt_100C_3v30.lib.json
index 0de5307..553fd58 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1__tt_100C_3v30.lib.json
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_085C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_085C_5v50.lib.json
index 3572efe..1292b3b 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_085C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_100C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_100C_5v50.lib.json
index ef8cf91..0541023 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_100C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_150C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_150C_5v50.lib.json
index 1836e73..236a5db 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_150C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_4v40.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_4v40.lib.json
index b726dc3..e272ad0 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_4v40.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_4v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_4v95.lib.json
index f1f6c0c..f541b3d 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_4v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_5v50_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_5v50_ccsnoise.lib.json
index 863ba1f..546d961 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_1v65.lib.json
index b73114c..c108bde 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_1v95.lib.json
index 593f3f7..92ca74c 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_3v00.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_3v00.lib.json
index f807aea..8d35ba8 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_3v00.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_150C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_150C_1v65.lib.json
index 7f4fe1d..6dceff9 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_150C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v32.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v32.lib.json
index 591b1ce..bd6bdcf 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v32.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v49.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v49.lib.json
index dc603a1..d92ef0a 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v49.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v65_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v65_ccsnoise.lib.json
index 61946fc..7b01719 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v95.lib.json
index 7bdb09a..3c52f5b 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__tt_025C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__tt_025C_3v30.lib.json
index e77fe85..d7d8135 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__tt_025C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16__tt_100C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_16__tt_100C_3v30.lib.json
index 90d0ccd..c509b42 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16__tt_100C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_085C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_085C_5v50.lib.json
index ec1a902..1e592d1 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_085C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_100C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_100C_5v50.lib.json
index cb5b798..725b1ea 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_100C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_150C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_150C_5v50.lib.json
index 10d2a56..236e14f 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_150C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_4v40.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_4v40.lib.json
index 0599f99..9961c29 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_4v40.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_4v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_4v95.lib.json
index c625bb8..285c1bd 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_4v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_5v50_ccsnoise.lib.json
index 2c7f7ee..13ec2fc 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_1v65.lib.json
index d926c84..b19c74e 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_1v95.lib.json
index 0cbfa46..d97521f 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_3v00.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_3v00.lib.json
index 011e8cc..bac9a9e 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_3v00.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_150C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_150C_1v65.lib.json
index ae5f4ff..cfeb7f8 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_150C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v32.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v32.lib.json
index da5418d..3b981b8 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v32.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v49.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v49.lib.json
index f80478d..333c6c2 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v49.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v65_ccsnoise.lib.json
index 56b8bd1..63c69e5 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v95.lib.json
index 0a07fe9..16e7cce 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__tt_025C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__tt_025C_3v30.lib.json
index 5ec5309..445c270 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__tt_025C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1__tt_100C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_1__tt_100C_3v30.lib.json
index 621ed40..fc32160 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1__tt_100C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_085C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_085C_5v50.lib.json
index ff2881a..a2897a9 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_085C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_100C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_100C_5v50.lib.json
index 958627c..c925c7a 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_100C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_150C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_150C_5v50.lib.json
index dc52df3..37eb267 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_150C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_4v40.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_4v40.lib.json
index dfb0e84..4a640ef 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_4v40.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_4v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_4v95.lib.json
index 486abd0..39d0e6d 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_4v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_5v50_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_5v50_ccsnoise.lib.json
index 1832f85..4eb2301 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_1v65.lib.json
index a204b32..6b1f86b 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_1v95.lib.json
index 67a20d8..50b4902 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_3v00.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_3v00.lib.json
index 1a219ad..6609bf3 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_3v00.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_150C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_150C_1v65.lib.json
index 066635f..a115e60 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_150C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v32.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v32.lib.json
index 547c05a..ac4ada7 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v32.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v49.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v49.lib.json
index c3e5fef..8d910ab 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v49.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v65_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v65_ccsnoise.lib.json
index 0c0caa4..6a29b40 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v95.lib.json
index 7ed6588..caa9ba2 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__tt_025C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__tt_025C_3v30.lib.json
index 74e55ae..e91b7af 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__tt_025C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2__tt_100C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_2__tt_100C_3v30.lib.json
index 1bdf71e..7df1fe9 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2__tt_100C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_085C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_085C_5v50.lib.json
index e4c57ed..218db45 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_085C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_100C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_100C_5v50.lib.json
index 0422d66..96fedaa 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_100C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_150C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_150C_5v50.lib.json
index 64c2552..dc93302 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_150C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_4v40.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_4v40.lib.json
index e79af08..cad846d 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_4v40.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_4v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_4v95.lib.json
index 73f32cb..26d6c1e 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_4v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_5v50_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_5v50_ccsnoise.lib.json
index 44d4ed8..957f95c 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_1v65.lib.json
index 83a8cfd..2780530 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_1v95.lib.json
index 98b3384..580c515 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_3v00.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_3v00.lib.json
index fcb06eb..31e0219 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_3v00.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_150C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_150C_1v65.lib.json
index 9d6e44f..9a5a9c0 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_150C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v32.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v32.lib.json
index 030d98e..63ea984 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v32.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v49.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v49.lib.json
index 629512b..5f19695 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v49.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v65_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v65_ccsnoise.lib.json
index 92582c0..6f2b898 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v95.lib.json
index 326c288..10d9236 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__tt_025C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__tt_025C_3v30.lib.json
index 5cea6ae..9994c5c 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__tt_025C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32__tt_100C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_32__tt_100C_3v30.lib.json
index 7003369..998dbe1 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32__tt_100C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_085C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_085C_5v50.lib.json
index 197b081..bcc3d69 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_085C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_100C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_100C_5v50.lib.json
index 5fd9db2..efcf2b0 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_100C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_150C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_150C_5v50.lib.json
index ca6dda0..5a9d9b5 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_150C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_4v40.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_4v40.lib.json
index d0b19f3..25ada86 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_4v40.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_4v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_4v95.lib.json
index 8dc94d8..b143904 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_4v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_5v50_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_5v50_ccsnoise.lib.json
index 2e6076b..6776341 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_1v65.lib.json
index a0616a4..8c3b77a 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_1v95.lib.json
index 6db1ce3..5c829b2 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_3v00.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_3v00.lib.json
index 85560ca..ad72139 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_3v00.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_150C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_150C_1v65.lib.json
index 4abbcc3..bf87144 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_150C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v32.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v32.lib.json
index 2becb6e..323c97d 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v32.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v49.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v49.lib.json
index 788db42..b79d73a 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v49.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v65_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v65_ccsnoise.lib.json
index da19143..5d52ec7 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v95.lib.json
index c79b0fa..406ab4c 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__tt_025C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__tt_025C_3v30.lib.json
index 1e6697d..a99dfea 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__tt_025C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4__tt_100C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_4__tt_100C_3v30.lib.json
index 85264b8..2742cc4 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4__tt_100C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_085C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_085C_5v50.lib.json
index b2b761a..fec0fe2 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_085C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_100C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_100C_5v50.lib.json
index af56b31..0094eb9 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_100C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_150C_5v50.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_150C_5v50.lib.json
index a0e7012..6c83711 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_150C_5v50.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_4v40.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_4v40.lib.json
index 4b040bc..883f19a 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_4v40.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_4v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_4v95.lib.json
index 2b1f92c..e2ca06f 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_4v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_5v50_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_5v50_ccsnoise.lib.json
index b7ad370..c88d402 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_1v65.lib.json
index 4633ece..530073b 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_1v95.lib.json
index 2321ec0..13c562f 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_3v00.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_3v00.lib.json
index b567001..530534f 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_3v00.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_150C_1v65.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_150C_1v65.lib.json
index eea361e..4af9b77 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_150C_1v65.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v32.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v32.lib.json
index 6d948ac..14e9c96 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v32.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v49.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v49.lib.json
index bf2a7f8..6e1880e 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v49.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v65_ccsnoise.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v65_ccsnoise.lib.json
index fb4aa54..41e02d0 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v95.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v95.lib.json
index b673783..574add9 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v95.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__tt_025C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__tt_025C_3v30.lib.json
index 43a11fc..6354bf9 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__tt_025C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8__tt_100C_3v30.lib.json b/cells/buf/sky130_fd_sc_hvl__buf_8__tt_100C_3v30.lib.json
index 3a4898d..ca1fc42 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8__tt_100C_3v30.lib.json
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_085C_5v50.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_085C_5v50.lib.json
index 438a1bd..cb71fb6 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_085C_5v50.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_085C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.03089393,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_100C_5v50.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_100C_5v50.lib.json
index 8e6db6f..ed02ed2 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_100C_5v50.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_100C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.03347125,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_150C_5v50.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_150C_5v50.lib.json
index ca66452..34daaf8 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_150C_5v50.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_4v40.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_4v40.lib.json
index d485acc..c13a1db 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_4v40.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_4v95.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_4v95.lib.json
index d485acc..c13a1db 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_4v95.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_5v50_ccsnoise.lib.json
index 36b84f1..c5917ca 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_1v65.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_1v65.lib.json
index f621ab4..f047707 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_1v65.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_1v95.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_1v95.lib.json
index 3004ad8..0a5fccc 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_1v95.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_1v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.004944581,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_3v00.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_3v00.lib.json
index f621ab4..f047707 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_3v00.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_150C_1v65.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_150C_1v65.lib.json
index ca66452..34daaf8 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_150C_1v65.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v32.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v32.lib.json
index 644ea59..c7f4aef 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v32.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v32.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0017424,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v49.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v49.lib.json
index 04db752..e7e51d0 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v49.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v49.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0022201,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v65_ccsnoise.lib.json
index 36b84f1..c5917ca 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v95.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v95.lib.json
index 656fb54..7f85280 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v95.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__ss_n40C_1v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0038025,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__tt_025C_3v30.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__tt_025C_3v30.lib.json
index 6a6fc29..ff24c9f 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__tt_025C_3v30.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__tt_025C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 1.19e-05,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1__tt_100C_3v30.lib.json b/cells/conb/sky130_fd_sc_hvl__conb_1__tt_100C_3v30.lib.json
index f621ab4..f047707 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1__tt_100C_3v30.lib.json
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,HI": {
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_085C_5v50.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_085C_5v50.lib.json
index 0a58175..e29d549 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_085C_5v50.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_085C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.03082194,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_100C_5v50.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_100C_5v50.lib.json
index d1bf447..1b49a80 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_100C_5v50.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_100C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.03311112,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_150C_5v50.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_150C_5v50.lib.json
index c6a3772..2786ad2 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_150C_5v50.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_4v40.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_4v40.lib.json
index c6a3772..2786ad2 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_4v40.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_4v95.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_4v95.lib.json
index c6a3772..2786ad2 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_4v95.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_5v50_ccsnoise.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_5v50_ccsnoise.lib.json
index c6a3772..2786ad2 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_1v65.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_1v65.lib.json
index c6a3772..2786ad2 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_1v65.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_1v95.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_1v95.lib.json
index 94a825c..a45ff9a 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_1v95.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_1v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.004816899,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_3v00.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_3v00.lib.json
index c6a3772..2786ad2 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_3v00.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_150C_1v65.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_150C_1v65.lib.json
index c6a3772..2786ad2 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_150C_1v65.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v32.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v32.lib.json
index a449553..f9b170a 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v32.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v32.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0017424,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v49.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v49.lib.json
index a40165a..def0dd6 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v49.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v49.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0022201,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v65_ccsnoise.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v65_ccsnoise.lib.json
index c6a3772..2786ad2 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v95.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v95.lib.json
index a554463..c40359a 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v95.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__ss_n40C_1v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0038025,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__tt_025C_3v30.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__tt_025C_3v30.lib.json
index 4eb1b21..cb1f0c0 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__tt_025C_3v30.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__tt_025C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 1.1e-05,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4__tt_100C_3v30.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_4__tt_100C_3v30.lib.json
index c6a3772..2786ad2 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4__tt_100C_3v30.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_085C_5v50.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_085C_5v50.lib.json
index bc9614b..bd8b5d4 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_085C_5v50.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_085C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.03110989,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_100C_5v50.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_100C_5v50.lib.json
index ac6896f..1cd83d4 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_100C_5v50.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_100C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.03455164,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_150C_5v50.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_150C_5v50.lib.json
index 17f2a9f..9fb7711 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_150C_5v50.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_4v40.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_4v40.lib.json
index 17f2a9f..9fb7711 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_4v40.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_4v95.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_4v95.lib.json
index 17f2a9f..9fb7711 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_4v95.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_5v50_ccsnoise.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_5v50_ccsnoise.lib.json
index 17f2a9f..9fb7711 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_1v65.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_1v65.lib.json
index 17f2a9f..9fb7711 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_1v65.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_1v95.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_1v95.lib.json
index 09d7e2d..16ad0d4 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_1v95.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_1v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.005327628,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_3v00.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_3v00.lib.json
index 17f2a9f..9fb7711 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_3v00.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_150C_1v65.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_150C_1v65.lib.json
index 17f2a9f..9fb7711 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_150C_1v65.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v32.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v32.lib.json
index 5a03733..d573d09 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v32.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v32.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0017424,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v49.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v49.lib.json
index 9af598c..f183c52 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v49.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v49.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0022201,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v65_ccsnoise.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v65_ccsnoise.lib.json
index 17f2a9f..9fb7711 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v95.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v95.lib.json
index bd4e846..20712e1 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v95.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__ss_n40C_1v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0038025,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__tt_025C_3v30.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__tt_025C_3v30.lib.json
index 5b42838..ff0742b 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__tt_025C_3v30.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__tt_025C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 1.11e-05,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8__tt_100C_3v30.lib.json b/cells/decap/sky130_fd_sc_hvl__decap_8__tt_100C_3v30.lib.json
index 17f2a9f..9fb7711 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8__tt_100C_3v30.lib.json
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
}
}
\ No newline at end of file
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_085C_5v50.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_085C_5v50.lib.json
index 33f97ab..cd8cdc3 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_085C_5v50.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_085C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_100C_5v50.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_100C_5v50.lib.json
index 2de6f6c..129fa51 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_100C_5v50.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_100C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_150C_5v50.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_150C_5v50.lib.json
index 410405d..62acbc9 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_150C_5v50.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_150C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_4v40.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_4v40.lib.json
index c4bbf14..2468ae6 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_4v40.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_4v40.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_4v95.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_4v95.lib.json
index 77ae39c..206a9ec 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_4v95.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_4v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_5v50_ccsnoise.lib.json
index 833f2d4..f42735d 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -43,18 +43,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_1v65.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_1v65.lib.json
index 5c5e9c6..2127bb3 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_1v65.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_1v95.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_1v95.lib.json
index 30ffa44..43ad0c4 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_1v95.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_3v00.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_3v00.lib.json
index 9687605..d4cbe92 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_3v00.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_100C_3v00.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_150C_1v65.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_150C_1v65.lib.json
index 9c6b021..f045349 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_150C_1v65.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_150C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v32.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v32.lib.json
index d4c6d5f..5b10db5 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v32.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v32.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v49.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v49.lib.json
index f73ed65..20803e9 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v49.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v49.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v65_ccsnoise.lib.json
index 5c19da3..7df60f5 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v95.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v95.lib.json
index 8984315..d6cc99b 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v95.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__ss_n40C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__tt_025C_3v30.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__tt_025C_3v30.lib.json
index 10bd5a7..0e176f0 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__tt_025C_3v30.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__tt_025C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__tt_100C_3v30.lib.json b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__tt_100C_3v30.lib.json
index 65f118d..f6e54b5 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__tt_100C_3v30.lib.json
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1__tt_100C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_085C_5v50.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_085C_5v50.lib.json
index d46e961..3877df2 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_085C_5v50.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_085C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_100C_5v50.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_100C_5v50.lib.json
index 7eafb95..44acc6e 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_100C_5v50.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_100C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_150C_5v50.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_150C_5v50.lib.json
index e911a72..d1538d9 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_150C_5v50.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_150C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_4v40.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_4v40.lib.json
index 0daba29..1821de9 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_4v40.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_4v40.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_4v95.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_4v95.lib.json
index 524b121..c1f1bee 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_4v95.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_4v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_5v50_ccsnoise.lib.json
index eb4cf02..4aa0808 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -43,18 +43,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_1v65.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_1v65.lib.json
index 685e3ca..df92161 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_1v65.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_1v95.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_1v95.lib.json
index 70c7911..1f06c4d 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_1v95.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_3v00.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_3v00.lib.json
index 6e2007a..8094a38 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_3v00.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_100C_3v00.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_150C_1v65.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_150C_1v65.lib.json
index afee058..58b9b7e 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_150C_1v65.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_150C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v32.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v32.lib.json
index 0e7e28f..590b146 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v32.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v32.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v49.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v49.lib.json
index 4a5fa1b..d37053a 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v49.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v49.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v65_ccsnoise.lib.json
index 73a53d6..4b6883b 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v95.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v95.lib.json
index 873d6e7..5957773 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v95.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__ss_n40C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__tt_025C_3v30.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__tt_025C_3v30.lib.json
index 75091e1..609a6d5 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__tt_025C_3v30.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__tt_025C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__tt_100C_3v30.lib.json b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__tt_100C_3v30.lib.json
index 3f6a633..ce33281 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__tt_100C_3v30.lib.json
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1__tt_100C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_085C_5v50.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_085C_5v50.lib.json
index da0d9fa..1b8c80e 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_085C_5v50.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_085C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_100C_5v50.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_100C_5v50.lib.json
index fb1d815..92b0f00 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_100C_5v50.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_100C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_150C_5v50.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_150C_5v50.lib.json
index 15caeef..9180be7 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_150C_5v50.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_150C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_4v40.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_4v40.lib.json
index 1c958e6..538c698 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_4v40.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_4v40.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_4v95.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_4v95.lib.json
index 642b79a..ec8a842 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_4v95.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_4v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_5v50_ccsnoise.lib.json
index 8031b76..5d812ea 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -43,18 +43,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_1v65.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_1v65.lib.json
index 7d944a4..851590b 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_1v65.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_1v95.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_1v95.lib.json
index 70f7523..1010c2a 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_1v95.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_3v00.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_3v00.lib.json
index ab609cf..100de28 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_3v00.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_100C_3v00.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_150C_1v65.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_150C_1v65.lib.json
index dce7c34..1876a61 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_150C_1v65.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_150C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v32.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v32.lib.json
index 9257572..40cb23a 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v32.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v32.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v49.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v49.lib.json
index 9e12e7b..06eb8df 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v49.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v49.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v65_ccsnoise.lib.json
index cf4dcdd..f473039 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v95.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v95.lib.json
index 81bf645..5bda812 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v95.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__ss_n40C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__tt_025C_3v30.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__tt_025C_3v30.lib.json
index a7884e8..5cb90cf 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__tt_025C_3v30.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__tt_025C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__tt_100C_3v30.lib.json b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__tt_100C_3v30.lib.json
index 46345a7..8413782 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__tt_100C_3v30.lib.json
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1__tt_100C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_085C_5v50.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_085C_5v50.lib.json
index 43227a2..0da9415 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_085C_5v50.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_085C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_100C_5v50.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_100C_5v50.lib.json
index e06a7a6..ab44c66 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_100C_5v50.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_100C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_150C_5v50.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_150C_5v50.lib.json
index 54ec0ce..8ee6ca8 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_150C_5v50.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_150C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_4v40.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_4v40.lib.json
index c3b82b5..19a8398 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_4v40.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_4v40.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_4v95.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_4v95.lib.json
index 44f7d5b..e80d70a 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_4v95.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_4v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_5v50_ccsnoise.lib.json
index b125dce..be19734 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -43,18 +43,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_1v65.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_1v65.lib.json
index 188a1da..44e1004 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_1v65.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_1v95.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_1v95.lib.json
index 26c63db..efaa778 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_1v95.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_3v00.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_3v00.lib.json
index f4118c0..50118ad 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_3v00.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_100C_3v00.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_150C_1v65.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_150C_1v65.lib.json
index 346155f..f7ac137 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_150C_1v65.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_150C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v32.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v32.lib.json
index ef521cb..b02b7c2 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v32.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v32.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v49.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v49.lib.json
index 82d65bf..dfa343c 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v49.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v49.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v65_ccsnoise.lib.json
index 135462d..f5f1d2f 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v95.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v95.lib.json
index 08a79f7..044c2b3 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v95.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__ss_n40C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__tt_025C_3v30.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__tt_025C_3v30.lib.json
index b2968d2..2146c20 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__tt_025C_3v30.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__tt_025C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__tt_100C_3v30.lib.json b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__tt_100C_3v30.lib.json
index 92127cf..0b937e6 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__tt_100C_3v30.lib.json
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1__tt_100C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_085C_5v50.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_085C_5v50.lib.json
index 01d2884..f51e4f6 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_085C_5v50.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_085C_5v50.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_100C_5v50.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_100C_5v50.lib.json
index 39aff15..5f8dc00 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_100C_5v50.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_100C_5v50.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_150C_5v50.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_150C_5v50.lib.json
index 4627c73..1b66b31 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_150C_5v50.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_150C_5v50.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_4v40.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_4v40.lib.json
index 8292bd1..a46748e 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_4v40.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_4v40.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_4v95.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_4v95.lib.json
index ba29669..c4a63e8 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_4v95.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_4v95.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_5v50_ccsnoise.lib.json
index bd1ee53..3eedd77 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -26,18 +26,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_1v65.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_1v65.lib.json
index c182063..b0141b9 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_1v65.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_1v65.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_1v95.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_1v95.lib.json
index 2e91b93..ac599c1 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_1v95.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_1v95.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_3v00.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_3v00.lib.json
index 691a358..237bf7b 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_3v00.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_100C_3v00.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_150C_1v65.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_150C_1v65.lib.json
index 4bb7b7c..f46c869 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_150C_1v65.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_150C_1v65.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v32.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v32.lib.json
index f1aa2f6..849c5c6 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v32.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v32.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v49.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v49.lib.json
index b768d82..81ff6ab 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v49.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v49.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v65_ccsnoise.lib.json
index d08e9b2..2169bfd 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v95.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v95.lib.json
index fa96e35..4886479 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v95.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__ss_n40C_1v95.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__tt_025C_3v30.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__tt_025C_3v30.lib.json
index 868ce8f..d266f69 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__tt_025C_3v30.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__tt_025C_3v30.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__tt_100C_3v30.lib.json b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__tt_100C_3v30.lib.json
index 0b3d042..7d2d860 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__tt_100C_3v30.lib.json
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1__tt_100C_3v30.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_085C_5v50.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_085C_5v50.lib.json
index 4bb6c9c..5453ba8 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_085C_5v50.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_085C_5v50.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_100C_5v50.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_100C_5v50.lib.json
index 42e69cc..90a52fc 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_100C_5v50.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_100C_5v50.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_150C_5v50.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_150C_5v50.lib.json
index 9c00581..b7de777 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_150C_5v50.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_150C_5v50.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_4v40.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_4v40.lib.json
index 1200bb4..ebac071 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_4v40.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_4v40.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_4v95.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_4v95.lib.json
index 8c5b370..ebb97b4 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_4v95.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_4v95.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_5v50_ccsnoise.lib.json
index 70e30b8..045e6e4 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -26,18 +26,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_1v65.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_1v65.lib.json
index 6502a16..de1efcc 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_1v65.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_1v65.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_1v95.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_1v95.lib.json
index 2a38238..eb31a4e 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_1v95.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_1v95.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_3v00.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_3v00.lib.json
index 362aec2..bb61611 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_3v00.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_100C_3v00.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_150C_1v65.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_150C_1v65.lib.json
index 7c51099..a37f0b6 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_150C_1v65.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_150C_1v65.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v32.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v32.lib.json
index ed78c83..6c49a6c 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v32.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v32.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v49.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v49.lib.json
index abb2e6b..76a9579 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v49.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v49.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v65_ccsnoise.lib.json
index 0d8267f..87f440a 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v95.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v95.lib.json
index d017527..a08cdbc 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v95.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__ss_n40C_1v95.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__tt_025C_3v30.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__tt_025C_3v30.lib.json
index b10d057..b410a1a 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__tt_025C_3v30.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__tt_025C_3v30.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__tt_100C_3v30.lib.json b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__tt_100C_3v30.lib.json
index 3bd780d..774462a 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__tt_100C_3v30.lib.json
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1__tt_100C_3v30.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_085C_5v50.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_085C_5v50.lib.json
index 55c872f..ec5523d 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_085C_5v50.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_100C_5v50.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_100C_5v50.lib.json
index cc479cf..deead89 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_100C_5v50.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_150C_5v50.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_150C_5v50.lib.json
index cb4181a..8adaa9d 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_150C_5v50.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_4v40.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_4v40.lib.json
index a02471c..7607156 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_4v40.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_4v95.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_4v95.lib.json
index 9ea3de3..cb726af 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_4v95.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_5v50_ccsnoise.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_5v50_ccsnoise.lib.json
index d350656..0e4ef6b 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_1v65.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_1v65.lib.json
index 8122ac3..f1d07d9 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_1v65.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_1v95.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_1v95.lib.json
index 5437343..b14fa21 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_1v95.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_1v95.lib.json
@@ -10,18 +10,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_3v00.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_3v00.lib.json
index 7ae6b32..7635389 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_3v00.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_150C_1v65.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_150C_1v65.lib.json
index 6cae7f3..1a45017 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_150C_1v65.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v32.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v32.lib.json
index 15295e0..6d748eb 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v32.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v49.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v49.lib.json
index 38a6188..c088978 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v49.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v65_ccsnoise.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v65_ccsnoise.lib.json
index 2e61da4..bd8c595 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v95.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v95.lib.json
index c96a247..b0c0abf 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v95.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__ss_n40C_1v95.lib.json
@@ -10,18 +10,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__tt_025C_3v30.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__tt_025C_3v30.lib.json
index 15ef785..da12161 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__tt_025C_3v30.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2__tt_100C_3v30.lib.json b/cells/diode/sky130_fd_sc_hvl__diode_2__tt_100C_3v30.lib.json
index 417e130..a71e702 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2__tt_100C_3v30.lib.json
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,DIODE": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_085C_5v50.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_085C_5v50.lib.json
index bed76b6..7757bb5 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_085C_5v50.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_085C_5v50.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_100C_5v50.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_100C_5v50.lib.json
index e6e3446..f1d689c 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_100C_5v50.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_100C_5v50.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_150C_5v50.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_150C_5v50.lib.json
index 650d56c..c20fa30 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_150C_5v50.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_150C_5v50.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_4v40.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_4v40.lib.json
index 05c8e67..eed3496 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_4v40.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_4v40.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_4v95.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_4v95.lib.json
index 9df9c31..39f3d04 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_4v95.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_4v95.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_5v50_ccsnoise.lib.json
index 4758f12..0154bfb 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -23,18 +23,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_1v65.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_1v65.lib.json
index bb06555..e711fda 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_1v65.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_1v65.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_1v95.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_1v95.lib.json
index cde20b8..7670e7a 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_1v95.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_1v95.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_3v00.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_3v00.lib.json
index fac473b..cb81436 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_3v00.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_100C_3v00.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_150C_1v65.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_150C_1v65.lib.json
index ea0e5ef..2f1ce74 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_150C_1v65.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_150C_1v65.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v32.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v32.lib.json
index 143d17c..f32f9cc 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v32.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v32.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v49.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v49.lib.json
index d2e4e43..df55774 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v49.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v49.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v65_ccsnoise.lib.json
index d35655d..033c4d9 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v95.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v95.lib.json
index 57a9fa2..8dc909e 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v95.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__ss_n40C_1v95.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__tt_025C_3v30.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__tt_025C_3v30.lib.json
index e9686b2..fa3e211 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__tt_025C_3v30.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__tt_025C_3v30.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__tt_100C_3v30.lib.json b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__tt_100C_3v30.lib.json
index 105f7ba..71dabb3 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__tt_100C_3v30.lib.json
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1__tt_100C_3v30.lib.json
@@ -25,18 +25,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_085C_5v50.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_085C_5v50.lib.json
index e9a8810..733327b 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_085C_5v50.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_085C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_100C_5v50.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_100C_5v50.lib.json
index 3625024..4dd745c 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_100C_5v50.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_100C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_150C_5v50.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_150C_5v50.lib.json
index be69be7..3223608 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_150C_5v50.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_150C_5v50.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_4v40.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_4v40.lib.json
index e2ee508..3c25920 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_4v40.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_4v40.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_4v95.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_4v95.lib.json
index 551e875..08d57a8 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_4v95.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_4v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_5v50_ccsnoise.lib.json
index 29b7a3f..24baa7c 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -43,18 +43,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_1v65.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_1v65.lib.json
index 760e149..12eb90a 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_1v65.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_1v95.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_1v95.lib.json
index 8ab41d8..02f9426 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_1v95.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_3v00.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_3v00.lib.json
index b40555e..e725493 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_3v00.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_100C_3v00.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_150C_1v65.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_150C_1v65.lib.json
index 97e86ed..958c80b 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_150C_1v65.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_150C_1v65.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v32.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v32.lib.json
index 2504168..f89d248 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v32.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v32.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v49.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v49.lib.json
index bf2363c..3d2e2d5 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v49.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v49.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v65_ccsnoise.lib.json
index 3e2b115..e0b5712 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v95.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v95.lib.json
index 35a4cba..c13f535 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v95.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__ss_n40C_1v95.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__tt_025C_3v30.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__tt_025C_3v30.lib.json
index cee2b60..cdd1d66 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__tt_025C_3v30.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__tt_025C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__tt_100C_3v30.lib.json b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__tt_100C_3v30.lib.json
index 4bb8ab7..96f9ac4 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__tt_100C_3v30.lib.json
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1__tt_100C_3v30.lib.json
@@ -45,18 +45,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_085C_5v50.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_085C_5v50.lib.json
index 275154d..7dcf2d2 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_085C_5v50.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_085C_5v50.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_100C_5v50.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_100C_5v50.lib.json
index ffe9317..56f4175 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_100C_5v50.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_100C_5v50.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_150C_5v50.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_150C_5v50.lib.json
index 48e9b40..6b51caf 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_150C_5v50.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_150C_5v50.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_4v40.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_4v40.lib.json
index ec633c8..5c9f65f 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_4v40.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_4v40.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_4v95.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_4v95.lib.json
index e1edccb..c916f1f 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_4v95.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_4v95.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_5v50_ccsnoise.lib.json
index 66d3ede..06119ce 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -26,18 +26,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_1v65.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_1v65.lib.json
index 25c7971..7c0d540 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_1v65.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_1v65.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_1v95.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_1v95.lib.json
index f038d36..1ddbec0 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_1v95.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_1v95.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_3v00.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_3v00.lib.json
index c7cb057..c3a4730 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_3v00.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_100C_3v00.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_150C_1v65.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_150C_1v65.lib.json
index 3c7e34f..ded0d4b 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_150C_1v65.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_150C_1v65.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v32.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v32.lib.json
index 78cc84a..ad439cf 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v32.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v32.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v49.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v49.lib.json
index 28d7173..26cbbb5 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v49.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v49.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v65_ccsnoise.lib.json
index 0bddee2..99539ef 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v95.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v95.lib.json
index 4fd24e1..136a40b 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v95.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__ss_n40C_1v95.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__tt_025C_3v30.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__tt_025C_3v30.lib.json
index 61b4de0..196ae5c 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__tt_025C_3v30.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__tt_025C_3v30.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__tt_100C_3v30.lib.json b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__tt_100C_3v30.lib.json
index c15727f..c643f0e 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__tt_100C_3v30.lib.json
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1__tt_100C_3v30.lib.json
@@ -28,18 +28,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_085C_5v50.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_085C_5v50.lib.json
index c6326f8..e8ee8fb 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_085C_5v50.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_085C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_100C_5v50.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_100C_5v50.lib.json
index 7c46556..e42ee41 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_100C_5v50.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_100C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_150C_5v50.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_150C_5v50.lib.json
index 88a9e02..f893547 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_150C_5v50.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_4v40.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_4v40.lib.json
index 62d17a0..b2cac79 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_4v40.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_4v95.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_4v95.lib.json
index 1d717b4..2acac4e 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_4v95.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_5v50_ccsnoise.lib.json
index 24f8123..2338999 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_1v65.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_1v65.lib.json
index a9d5891..be67e3e 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_1v65.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_1v95.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_1v95.lib.json
index 2553964..bff3aaf 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_1v95.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_3v00.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_3v00.lib.json
index 451783f..5b6c326 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_3v00.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_150C_1v65.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_150C_1v65.lib.json
index 0213b1d..90592d6 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_150C_1v65.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v32.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v32.lib.json
index 61f9d6a..d9386b4 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v32.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v32.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v49.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v49.lib.json
index 8b875a2..17fb375 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v49.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v49.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v65_ccsnoise.lib.json
index 45fbdc5..119700c 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v95.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v95.lib.json
index bc11039..b1580a1 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v95.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__ss_n40C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__tt_025C_3v30.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__tt_025C_3v30.lib.json
index 97af636..c266981 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__tt_025C_3v30.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__tt_025C_3v30.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1__tt_100C_3v30.lib.json b/cells/einvn/sky130_fd_sc_hvl__einvn_1__tt_100C_3v30.lib.json
index ce615a5..4a637a4 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1__tt_100C_3v30.lib.json
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_085C_5v50.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_085C_5v50.lib.json
index 7b5a08b..ea1c1e5 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_085C_5v50.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_085C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_100C_5v50.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_100C_5v50.lib.json
index 6b7b140..68e2562 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_100C_5v50.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_100C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_150C_5v50.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_150C_5v50.lib.json
index 96292f1..3ee848a 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_150C_5v50.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_4v40.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_4v40.lib.json
index 81ad42e..02a7038 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_4v40.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_4v95.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_4v95.lib.json
index 96ee66c..39fbcab 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_4v95.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_5v50_ccsnoise.lib.json
index 1f5164d..83b0d1d 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_1v65.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_1v65.lib.json
index 66e99af..dcfdb4f 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_1v65.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_1v95.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_1v95.lib.json
index 6fa9a67..33f68fd 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_1v95.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_3v00.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_3v00.lib.json
index 23f0dfc..4eaa2da 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_3v00.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_150C_1v65.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_150C_1v65.lib.json
index 89ba6c0..53426a9 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_150C_1v65.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v32.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v32.lib.json
index 98be32e..73bf866 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v32.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v32.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v49.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v49.lib.json
index d8347d8..667fb9e 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v49.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v49.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v65_ccsnoise.lib.json
index a56a8b5..85d3308 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v95.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v95.lib.json
index 35af3f8..f3dd750 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v95.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__ss_n40C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__tt_025C_3v30.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__tt_025C_3v30.lib.json
index 45467a3..f282120 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__tt_025C_3v30.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__tt_025C_3v30.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1__tt_100C_3v30.lib.json b/cells/einvp/sky130_fd_sc_hvl__einvp_1__tt_100C_3v30.lib.json
index e900af9..b644799 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1__tt_100C_3v30.lib.json
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_085C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_085C_5v50.lib.json
index e6f0b8f..ac09a7a 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_085C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_100C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_100C_5v50.lib.json
index bc0f69c..79df624 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_100C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_150C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_150C_5v50.lib.json
index 6365e30..23deed5 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_150C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_4v40.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_4v40.lib.json
index 39cfd7f..764f3cf 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_4v40.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_4v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_4v95.lib.json
index 7b9ac2a..b02a3e1 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_4v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_5v50_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_5v50_ccsnoise.lib.json
index c808f80..9efc779 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_1v65.lib.json
index 41c4a7b..7bee98f 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_1v95.lib.json
index 8ba43a5..8856bee 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_3v00.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_3v00.lib.json
index 33eab91..e65713c 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_3v00.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_150C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_150C_1v65.lib.json
index 07eea60..ee0d2a2 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_150C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v32.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v32.lib.json
index b6b5d2f..9bee24f 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v32.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v49.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v49.lib.json
index 2691d48..61e8e4c 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v49.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v65_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v65_ccsnoise.lib.json
index 0e46545..49efeba 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v95.lib.json
index f173a62..e473eae 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__tt_025C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__tt_025C_3v30.lib.json
index 1519875..4c50499 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__tt_025C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16__tt_100C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_16__tt_100C_3v30.lib.json
index 736b916..6908d47 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16__tt_100C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_085C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_085C_5v50.lib.json
index fdf5d9e..8571a0b 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_085C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_100C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_100C_5v50.lib.json
index 5b31ae0..9b361eb 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_100C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_150C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_150C_5v50.lib.json
index ee5b514..ffd4a09 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_150C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_4v40.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_4v40.lib.json
index 60907be..27e34b0 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_4v40.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_4v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_4v95.lib.json
index 261322c..e573a2f 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_4v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_5v50_ccsnoise.lib.json
index c484dd0..7e48c4a 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_1v65.lib.json
index 8978fe2..aaefd2e 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_1v95.lib.json
index fadb712..306fc8b 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_3v00.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_3v00.lib.json
index a31f3cb..b775771 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_3v00.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_150C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_150C_1v65.lib.json
index de55b34..f51a7cf 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_150C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v32.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v32.lib.json
index 464da11..aec54c4 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v32.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v49.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v49.lib.json
index 2fb13ed..f89f38b 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v49.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v65_ccsnoise.lib.json
index ab73d4e..6304e83 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v95.lib.json
index d9044ff..a9685e1 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__tt_025C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__tt_025C_3v30.lib.json
index 286e754..52424ec 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__tt_025C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1__tt_100C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_1__tt_100C_3v30.lib.json
index 5c3c6b5..c3295b2 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1__tt_100C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_085C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_085C_5v50.lib.json
index 54c44f6..3c3f749 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_085C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_100C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_100C_5v50.lib.json
index a206d58..cdb723d 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_100C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_150C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_150C_5v50.lib.json
index 26c9e06..bdb09fb 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_150C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_4v40.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_4v40.lib.json
index 00dbd83..a415372 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_4v40.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_4v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_4v95.lib.json
index c4e1d33..d3ac64a 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_4v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_5v50_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_5v50_ccsnoise.lib.json
index 9ca8aa9..01454ed 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_1v65.lib.json
index 3a68762..7ec78d3 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_1v95.lib.json
index df4b98b..e376769 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_3v00.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_3v00.lib.json
index 3740b18..7008b4e 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_3v00.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_150C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_150C_1v65.lib.json
index 7859140..af292ea 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_150C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v32.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v32.lib.json
index da6d328..f691b80 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v32.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v49.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v49.lib.json
index 18c289b..6f0fb09 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v49.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v65_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v65_ccsnoise.lib.json
index 14d87cf..59ae2e0 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v95.lib.json
index 2c3f0f2..7ad88fb 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__tt_025C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__tt_025C_3v30.lib.json
index aa3fa54..a278242 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__tt_025C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2__tt_100C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_2__tt_100C_3v30.lib.json
index 97efd64..25936fe 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2__tt_100C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_085C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_085C_5v50.lib.json
index 3e0c9a2..9900420 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_085C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_100C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_100C_5v50.lib.json
index 73a33a9..bb48804 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_100C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_150C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_150C_5v50.lib.json
index f1754e2..22bf844 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_150C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_4v40.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_4v40.lib.json
index b4207db..28d5218 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_4v40.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_4v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_4v95.lib.json
index 760402b..e7384b4 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_4v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_5v50_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_5v50_ccsnoise.lib.json
index ee68b3a..3f7342f 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_1v65.lib.json
index 048a276..d63a8f2 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_1v95.lib.json
index a308ed6..174967c 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_3v00.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_3v00.lib.json
index 55cfc95..6889108 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_3v00.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_150C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_150C_1v65.lib.json
index addc030..3426db5 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_150C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v32.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v32.lib.json
index fd1d038..079d485 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v32.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v49.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v49.lib.json
index 54292ca..5682da5 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v49.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v65_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v65_ccsnoise.lib.json
index e83c46f..ed03136 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v95.lib.json
index 5b0b37d..8a67909 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__tt_025C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__tt_025C_3v30.lib.json
index 69d53dc..0832250 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__tt_025C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4__tt_100C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_4__tt_100C_3v30.lib.json
index e4dc9cd..9fd418a 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4__tt_100C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_085C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_085C_5v50.lib.json
index 6a3e9e3..5fafe95 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_085C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_100C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_100C_5v50.lib.json
index c851763..545b5e3 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_100C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_150C_5v50.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_150C_5v50.lib.json
index 1e2b142..90c04af 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_150C_5v50.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_4v40.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_4v40.lib.json
index 1d84d12..8b418f8 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_4v40.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_4v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_4v95.lib.json
index 360ee65..492818e 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_4v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_5v50_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_5v50_ccsnoise.lib.json
index a4305a0..adcd231 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_1v65.lib.json
index 1184b87..d524c2e 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_1v95.lib.json
index d6fe3f7..62e7729 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_3v00.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_3v00.lib.json
index fc72d6d..ac6b33b 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_3v00.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_150C_1v65.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_150C_1v65.lib.json
index a64392f..fe6172d 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_150C_1v65.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v32.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v32.lib.json
index 87e5e16..bec86cb 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v32.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v49.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v49.lib.json
index b8c6776..e108707 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v49.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v65_ccsnoise.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v65_ccsnoise.lib.json
index 562ef8a..0bacce5 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v95.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v95.lib.json
index 707b6f1..8158edc 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v95.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__tt_025C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__tt_025C_3v30.lib.json
index aec28f7..a9df69a 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__tt_025C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8__tt_100C_3v30.lib.json b/cells/inv/sky130_fd_sc_hvl__inv_8__tt_100C_3v30.lib.json
index c4e3197..534091f 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8__tt_100C_3v30.lib.json
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_085C_5v50_lv1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_085C_5v50_lv1v95.lib.json
index c15864d..815049a 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_085C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_085C_5v50_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
index aff38a2..4e15027 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_100C_5v50_lv1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_100C_5v50_lv1v95.lib.json
index 79359cf..fe53607 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_100C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_100C_5v50_lv1v95.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_150C_5v50_lv1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_150C_5v50_lv1v95.lib.json
index 0dc723b..8a9a42d 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_150C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_150C_5v50_lv1v95.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_4v40_lv1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_4v40_lv1v95.lib.json
index 29f2d29..22a2d50 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_4v40_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_4v40_lv1v95.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_4v95_lv1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_4v95_lv1v95.lib.json
index 1e31c1e..b898b4e 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_4v95_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_4v95_lv1v95.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index aca6fab..fbeb3ac 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
index 03a84c0..cbfe9ac 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
index c83b784..69f1c39 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lv1v40.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lv1v40.lib.json
index d3b72c0..5c03ffe 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lv1v40.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lv1v40.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lv1v60.lib.json
index 2fd1fbf..1421a05 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_100C_5v50_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index e448a07..0540ebf 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lv1v35.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
index 35c3ef6..f8696b2 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
index 61087a7..f730aa9 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v65.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v65.lib.json
index 8ae80e0..5bc0634 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v65.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v65.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v95.lib.json
index ab67b78..2e5c422 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
index 25680d1..40d432a 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
index 87b83a0..a50c7fc 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v65.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v65.lib.json
index 81dac2f..59437cf 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v65.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v65.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v95.lib.json
index 818c187..3317b0f 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
index a076c82..14fa40f 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 43e7c7b..eae1da5 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_1v65_lv1v40.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_1v65_lv1v40.lib.json
index 73d7fdd..afb3c2c 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_1v65_lv1v40.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_1v65_lv1v40.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_1v65_lv1v60.lib.json
index 514bde6..e852dfb 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_1v65_lv1v60.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
index 266c35f..89f6c13 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
@@ -10,19 +10,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
index 8426752..a9a0233 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
@@ -10,19 +10,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
index 577d18e..f332cfd 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
index 0fbc875..470d67e 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_150C_1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_150C_1v65_lv1v60.lib.json
index a3eb7dc..ad8657b 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_150C_1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_150C_1v65_lv1v60.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
index 20ac281..062a5dc 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v32_lv1v28.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v32_lv1v28.lib.json
index 1cca7ff..cfddeab 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v32_lv1v28.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v32_lv1v28.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v49_lv1v44.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v49_lv1v44.lib.json
index bac0af3..7477c06 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v49_lv1v44.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v49_lv1v44.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v35.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v35.lib.json
index 2c7d72c..06d21e9 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v35.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v35.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v40.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v40.lib.json
index 1332955..d6aa7a6 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v40.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v40.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
index c0a8e88..ab12f8b 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index bdb2b3f..3584283 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_2v64_lv1v80.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_2v64_lv1v80.lib.json
index 72fd8b4..212a2cb 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_2v64_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_2v64_lv1v80.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_2v97_lv1v80.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_2v97_lv1v80.lib.json
index 36ccf3f..8a2a460 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_2v97_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_2v97_lv1v80.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_3v30_lv1v80.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_3v30_lv1v80.lib.json
index 576fa31..04cf8bf 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_025C_3v30_lv1v80.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_100C_3v30_lv1v80.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_100C_3v30_lv1v80.lib.json
index 46e2ca6..d158e5f 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_100C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_100C_3v30_lv1v80.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_150C_3v30_lv1v80.lib.json b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_150C_3v30_lv1v80.lib.json
index 36f79ae..1fa0cf6 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_150C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1__tt_150C_3v30_lv1v80.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_085C_5v50_lv1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_085C_5v50_lv1v95.lib.json
index 024f594..2be4ca6 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_085C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_085C_5v50_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
index 6edba66..e45250e 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_100C_5v50_lv1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_100C_5v50_lv1v95.lib.json
index 967af07..771d03b 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_100C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_100C_5v50_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_150C_5v50_lv1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_150C_5v50_lv1v95.lib.json
index bcdb133..469c735 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_150C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_150C_5v50_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_4v40_lv1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_4v40_lv1v95.lib.json
index e57d93f..c069679 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_4v40_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_4v40_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_4v95_lv1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_4v95_lv1v95.lib.json
index cdc78e3..8d1edd6 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_4v95_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_4v95_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 0103780..6f276aa 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
index 470a5fe..9d0c62c 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
index a0acc07..645f90c 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lv1v40.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lv1v40.lib.json
index 30b087a..46013d1 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lv1v40.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lv1v40.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lv1v60.lib.json
index da6de51..42d3b82 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_100C_5v50_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index a25174c..9a0d97d 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lv1v35.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
index 2e9a838..834c498 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
index 238355e..873dc50 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v65.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v65.lib.json
index c0b9af7..f523c5c 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v65.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v95.lib.json
index 29ef6b0..f8022ce 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
index 138fa0e..184c221 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
index 81b7796..d2f7088 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v65.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v65.lib.json
index 0c7b29b..df5c4af 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v65.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v95.lib.json
index 10fee53..8063306 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
index 53e7862..04fa583 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 7e22f6f..5982ba7 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_1v65_lv1v40.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_1v65_lv1v40.lib.json
index 07025a0..9fd0530 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_1v65_lv1v40.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_1v65_lv1v40.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_1v65_lv1v60.lib.json
index 28d47a7..d3b2300 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
index fe3487c..5f98e9b 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
@@ -18,19 +18,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
index e452e78..d05a160 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
@@ -18,19 +18,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
index 90a194a..83d7697 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
index 41ee6c4..d9b29e1 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_150C_1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_150C_1v65_lv1v60.lib.json
index 2016d4d..f2cb2a1 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_150C_1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_150C_1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
index d53d069..bbfd72f 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v32_lv1v28.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v32_lv1v28.lib.json
index 25ece5c..6c0c972 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v32_lv1v28.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v32_lv1v28.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v49_lv1v44.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v49_lv1v44.lib.json
index 0523197..5c55c7a 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v49_lv1v44.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v49_lv1v44.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v35.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v35.lib.json
index f4cef78..65aa14a 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v35.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v35.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v40.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v40.lib.json
index 0457565..43ff7b9 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v40.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v40.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
index f008ddf..834eb4c 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index d558d88..cf43943 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_2v64_lv1v80.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_2v64_lv1v80.lib.json
index 0d2f651..2a6d048 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_2v64_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_2v64_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_2v97_lv1v80.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_2v97_lv1v80.lib.json
index b867664..396db75 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_2v97_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_2v97_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_3v30_lv1v80.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_3v30_lv1v80.lib.json
index 254afd3..f80b8a5 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_025C_3v30_lv1v80.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_100C_3v30_lv1v80.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_100C_3v30_lv1v80.lib.json
index 40fe914..04f232d 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_100C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_100C_3v30_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_150C_3v30_lv1v80.lib.json b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_150C_3v30_lv1v80.lib.json
index 1c39a62..3ab9a1b 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_150C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1__tt_150C_3v30_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_085C_5v50_lv1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_085C_5v50_lv1v95.lib.json
index 6deb448..e0c03df 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_085C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_085C_5v50_lv1v95.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
index 8597cd3..578c975 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_100C_5v50_lv1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_100C_5v50_lv1v95.lib.json
index 0751b45..992f9ee 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_100C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_100C_5v50_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_150C_5v50_lv1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_150C_5v50_lv1v95.lib.json
index b88adbf..18682e7 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_150C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_150C_5v50_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_4v40_lv1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_4v40_lv1v95.lib.json
index f69a790..7e528ec 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_4v40_lv1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_4v40_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_4v95_lv1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_4v95_lv1v95.lib.json
index 256956b..6f86441 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_4v95_lv1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_4v95_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index d7e3f36..5ca51c9 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
index 4ffd383..0401750 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
index ffdfa2d..904152f 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lv1v40.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lv1v40.lib.json
index f6c4e37..8a3160a 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lv1v40.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lv1v40.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lv1v60.lib.json
index 429820f..ee15a7d 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_100C_5v50_lv1v60.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index 8c8b057..f14f027 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lv1v35.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
index 3e0347d..89c644d 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
index eec5a72..d77ef4b 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v65.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v65.lib.json
index 3d8fa2c..2bcbf0b 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v65.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v65.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v95.lib.json
index 0ef29cd..19281a1 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v95.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
index 07ec154..604e0aa 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
index 82e2775..41b7fa2 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v65.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v65.lib.json
index f364963..e75cb09 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v65.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v65.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v95.lib.json
index b9d73e9..89410d2 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v95.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
index c576d75..75f86d3 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 20429cf..140d81c 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_1v65_lv1v40.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_1v65_lv1v40.lib.json
index 0615344..7bd9a67 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_1v65_lv1v40.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_1v65_lv1v40.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_1v65_lv1v60.lib.json
index d536ea3..27e680b 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
index 5b56b1f..2d93a69 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
@@ -12,19 +12,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
index e9e1c63..46b3529 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
@@ -12,19 +12,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
index d89fd12..f5cd28f 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
index d904038..782a442 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_150C_1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_150C_1v65_lv1v60.lib.json
index b6c67c9..e205f33 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_150C_1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_150C_1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
index 7bbce1d..19a93f2 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v32_lv1v28.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v32_lv1v28.lib.json
index 8dc12eb..9045aea 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v32_lv1v28.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v32_lv1v28.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v49_lv1v44.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v49_lv1v44.lib.json
index 6addb21..da46071 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v49_lv1v44.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v49_lv1v44.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v35.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v35.lib.json
index d7e4c9f..b972cd0 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v35.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v35.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v40.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v40.lib.json
index d73e5bd..bd779ce 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v40.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v40.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
index 0958044..1f25ff5 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index 613ab84..073d73d 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_2v64_lv1v80.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_2v64_lv1v80.lib.json
index 390740c..1729db7 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_2v64_lv1v80.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_2v64_lv1v80.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_2v97_lv1v80.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_2v97_lv1v80.lib.json
index 8187ee0..e49b049 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_2v97_lv1v80.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_2v97_lv1v80.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_3v30_lv1v80.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_3v30_lv1v80.lib.json
index 03292d4..975d780 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_025C_3v30_lv1v80.lib.json
@@ -24,19 +24,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_100C_3v30_lv1v80.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_100C_3v30_lv1v80.lib.json
index f029630..02ac298 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_100C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_100C_3v30_lv1v80.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_150C_3v30_lv1v80.lib.json b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_150C_3v30_lv1v80.lib.json
index 2847a12..a78d5dd 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_150C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1__tt_150C_3v30_lv1v80.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_085C_5v50_lv1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_085C_5v50_lv1v95.lib.json
index f5d5415..5261d8e 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_085C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_085C_5v50_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
index 2727478..02f143a 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_100C_5v50_lv1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_100C_5v50_lv1v95.lib.json
index a69c8c7..bc56016 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_100C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_100C_5v50_lv1v95.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_150C_5v50_lv1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_150C_5v50_lv1v95.lib.json
index 58eadbc..ae1bbb1 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_150C_5v50_lv1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_150C_5v50_lv1v95.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_4v40_lv1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_4v40_lv1v95.lib.json
index e46983b..310282e 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_4v40_lv1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_4v40_lv1v95.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_4v95_lv1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_4v95_lv1v95.lib.json
index d0148ee..01a4186 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_4v95_lv1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_4v95_lv1v95.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 08630cf..f6d24bd 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
index 71d2a6d..af5234e 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
index 932e166..2998b17 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lv1v40.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lv1v40.lib.json
index f9e7cd6..c97b874 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lv1v40.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lv1v40.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lv1v60.lib.json
index f46baea..7c4c1f6 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_100C_5v50_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index 6975f14..7eca074 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lv1v35.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
index 815a706..08bd71d 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
index 33ca0fa..c248fc4 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v65.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v65.lib.json
index 0a9e456..75cd58d 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v65.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v65.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v95.lib.json
index eab3fcd..65191db 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
index 1940faf..d289bfa 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
index afcfb7a..9db5b80 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v65.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v65.lib.json
index 5b1a50a..6edf871 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v65.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v65.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v95.lib.json
index 270558d..79ccda7 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
index 5a14ae3..2b844e0 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 81020e0..71c020f 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_1v65_lv1v40.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_1v65_lv1v40.lib.json
index 244668e..8d4ad4e 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_1v65_lv1v40.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_1v65_lv1v40.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_1v65_lv1v60.lib.json
index 6a83473..b7f86a8 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_1v65_lv1v60.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
index 3aff81a..5420162 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
@@ -10,19 +10,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
index 1fe06ef..cb6170e 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
@@ -10,19 +10,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
index 8b34d52..84d7b24 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
index 26102f3..369a20c 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_150C_1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_150C_1v65_lv1v60.lib.json
index bf937f6..29bdd5e 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_150C_1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_150C_1v65_lv1v60.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
index c20cfc2..021ba38 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v32_lv1v28.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v32_lv1v28.lib.json
index 6212664..5b9288c 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v32_lv1v28.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v32_lv1v28.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v49_lv1v44.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v49_lv1v44.lib.json
index 787654e..f768ee0 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v49_lv1v44.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v49_lv1v44.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v35.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v35.lib.json
index 4687de3..2736004 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v35.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v35.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v40.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v40.lib.json
index 6ef7886..8745600 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v40.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v40.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
index a540b42..288a632 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index 783f91b..c867b29 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_2v64_lv1v80.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_2v64_lv1v80.lib.json
index a6a9e5b..20cba62 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_2v64_lv1v80.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_2v64_lv1v80.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_2v97_lv1v80.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_2v97_lv1v80.lib.json
index 462b1b4..2da1d66 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_2v97_lv1v80.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_2v97_lv1v80.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_3v30_lv1v80.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_3v30_lv1v80.lib.json
index e5b8314..d7ca88e 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_025C_3v30_lv1v80.lib.json
@@ -22,19 +22,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_100C_3v30_lv1v80.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_100C_3v30_lv1v80.lib.json
index 11dc939..14bb1bc 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_100C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_100C_3v30_lv1v80.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_150C_3v30_lv1v80.lib.json b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_150C_3v30_lv1v80.lib.json
index 973e3b6..f14b724 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_150C_3v30_lv1v80.lib.json
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1__tt_150C_3v30_lv1v80.lib.json
@@ -20,19 +20,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_085C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_085C_5v50_lv1v95.lib.json
index 8e8fc00..80ae944 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_085C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_085C_5v50_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
index a71ce11..234324d 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_100C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_100C_5v50_lv1v95.lib.json
index 3036957..0c87d36 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_100C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_100C_5v50_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_150C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_150C_5v50_lv1v95.lib.json
index d106d60..7fb1a42 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_150C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_150C_5v50_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_4v40_lv1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_4v40_lv1v95.lib.json
index 1fcfeb4..7b24c3e 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_4v40_lv1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_4v40_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_4v95_lv1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_4v95_lv1v95.lib.json
index 25711d0..5c817bb 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_4v95_lv1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_4v95_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 7809ff4..eda3ea0 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
index ff2e038..3954054 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
index af3d3cf..da5b248 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lv1v40.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lv1v40.lib.json
index cf38b8a..444817a 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lv1v40.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lv1v40.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lv1v60.lib.json
index a02078c..f841566 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_100C_5v50_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index 12f395e..34ad543 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lv1v35.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
index e61ff9e..e04426a 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
index fe2eb14..7e3c441 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v65.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v65.lib.json
index 735ec0a..8640b96 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v65.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v95.lib.json
index 25455dc..204177b 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
index 47877b3..70da926 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
index 4ffd056..3e89e1f 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v65.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v65.lib.json
index 6dfae72..351a77e 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v65.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v95.lib.json
index 2b03dfe..68b193e 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
index 5dcf7da..f8bd366 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 08ec6d3..f64af61 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_1v65_lv1v40.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_1v65_lv1v40.lib.json
index 04fc4d9..f473fee 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_1v65_lv1v40.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_1v65_lv1v40.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_1v65_lv1v60.lib.json
index aeba519..a4158a6 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
index 87c5254..3c53944 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
@@ -18,19 +18,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
index f8952d0..6933911 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
@@ -18,19 +18,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
index bd0220a..e585b8c 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
index 64595a4..a7fe1c7 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_150C_1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_150C_1v65_lv1v60.lib.json
index 106d52d..11a7cab 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_150C_1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_150C_1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
index f2baab5..37227e4 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v32_lv1v28.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v32_lv1v28.lib.json
index 9091164..8394af4 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v32_lv1v28.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v32_lv1v28.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v49_lv1v44.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v49_lv1v44.lib.json
index 85f7dd1..58ae27f 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v49_lv1v44.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v49_lv1v44.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v35.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v35.lib.json
index eca4672..2e9de90 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v35.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v35.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v40.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v40.lib.json
index e362cd5..798554e 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v40.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v40.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
index 80642e0..7344b53 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index f92530e..7399ddd 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_2v64_lv1v80.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_2v64_lv1v80.lib.json
index 53d36a6..6423d2b 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_2v64_lv1v80.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_2v64_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_2v97_lv1v80.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_2v97_lv1v80.lib.json
index ca7efa7..f5bb3ec 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_2v97_lv1v80.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_2v97_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_3v30_lv1v80.lib.json
index f95d19f..73bdc0a 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_025C_3v30_lv1v80.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_100C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_100C_3v30_lv1v80.lib.json
index 5e6a068..94b7873 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_100C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_100C_3v30_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_150C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_150C_3v30_lv1v80.lib.json
index a0c2fa7..5330954 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_150C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1__tt_150C_3v30_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_085C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_085C_5v50_lv1v95.lib.json
index 28bb53a..e2f8640 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_085C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_085C_5v50_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
index d7310b8..bffbeac 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_100C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_100C_5v50_lv1v95.lib.json
index 4697456..1b4bdc7 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_100C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_100C_5v50_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_150C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_150C_5v50_lv1v95.lib.json
index f1391f3..d1df9ff 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_150C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_150C_5v50_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_4v40_lv1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_4v40_lv1v95.lib.json
index 1d1015a..96513e9 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_4v40_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_4v40_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_4v95_lv1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_4v95_lv1v95.lib.json
index 3b9b9f0..329dc74 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_4v95_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_4v95_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 1a43daf..786996e 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_5v50_lv1v95_ccsnoise.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
index 9be171c..4fbe3e6 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
@@ -36,19 +36,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
index 4539c28..1291922 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lv1v40.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lv1v40.lib.json
index 8f621d6..3ecfb60 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lv1v40.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lv1v40.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lv1v60.lib.json
index e7af6e9..5ad6861 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_100C_5v50_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index a64f0f7..eed666c 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lv1v35.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lv1v35.lib.json
index ba0f29c..f6c3cf0 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lv1v35.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lv1v35.lib.json
@@ -36,19 +36,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lv1v60.lib.json
index cb54500..db2854b 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvff_lvss_n40C_5v50_lv1v60.lib.json
@@ -39,19 +39,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v65.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v65.lib.json
index 733076f..6a547ec 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v65.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v65.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v95.lib.json
index 63e1126..6a1ddea 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v95_lowhv1v65.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v95_lowhv1v65.lib.json
index bc5c101..abee5a9 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_1v95_lowhv1v65.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
index e031608..e06e4ca 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v65.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v65.lib.json
index 0109f17..da29ca4 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v65.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v65.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v95.lib.json
index 8e0101a..ff6c714 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v95_lowhv1v65.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
index 83b486e..c39d4ed 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 6af9132..f665f4f 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_1v65_lv1v40.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_1v65_lv1v40.lib.json
index 8b5af28..ab10a80 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_1v65_lv1v40.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_1v65_lv1v40.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_1v65_lv1v60.lib.json
index 2a587c7..ebfb0b0 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_2v40_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
index 3f81706..212d290 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_2v70_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
index bd72adc..8218807 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
index 3a0b056..c128004 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
index 636f4e0..9cf5211 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_150C_1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_150C_1v65_lv1v60.lib.json
index f4fac2d..7f2c0e7 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_150C_1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_150C_1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_150C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
index 1571aaa..60b5f87 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v32_lv1v28.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v32_lv1v28.lib.json
index 4ba8e65..7bc9caa 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v32_lv1v28.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v32_lv1v28.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v49_lv1v44.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v49_lv1v44.lib.json
index e1ce519..baf8cf3 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v49_lv1v44.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v49_lv1v44.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v35.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v35.lib.json
index 1052736..a6e9998 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v35.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v35.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v40.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v40.lib.json
index 7822c49..f665f32 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v40.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v40.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v60_ccsnoise.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
index e0bb776..775372f 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index ccfa970..a14a3f8 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_2v64_lv1v80.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_2v64_lv1v80.lib.json
index 5754f4d..af33682 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_2v64_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_2v64_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_2v97_lv1v80.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_2v97_lv1v80.lib.json
index 4ae02e1..fcb852b 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_2v97_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_2v97_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_3v30_lv1v80.lib.json
index e2ac525..cefdef1 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_025C_3v30_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_100C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_100C_3v30_lv1v80.lib.json
index 5bfffd8..e356235 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_100C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_100C_3v30_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_150C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_150C_3v30_lv1v80.lib.json
index 5de85cf..2dc59c6 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_150C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3__tt_150C_3v30_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_085C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_085C_5v50_lv1v95.lib.json
index fff095e..53d410a 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_085C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_085C_5v50_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
index 3c12896..84a4be6 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_100C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_100C_5v50_lv1v95.lib.json
index ae1195b..78d7d96 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_100C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_100C_5v50_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_150C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_150C_5v50_lv1v95.lib.json
index ff384c8..716d77a 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_150C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_150C_5v50_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_4v40_lv1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_4v40_lv1v95.lib.json
index e8b072a..5ab05bd 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_4v40_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_4v40_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_4v95_lv1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_4v95_lv1v95.lib.json
index 2202f36..bb164c5 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_4v95_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_4v95_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index b2bf0ad..f5e934d 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
index df7731c..0dda5fc 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
@@ -36,19 +36,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
index 9527ab8..4265cda 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lv1v40.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lv1v40.lib.json
index 6ea0721..c9efbbd 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lv1v40.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lv1v40.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lv1v60.lib.json
index f4db18d..b8c878f 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_100C_5v50_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index 5b83a95..2d68352 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lv1v35.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
index a57193b..829a0a0 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
@@ -36,19 +36,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
index 1370853..59f7a07 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v65.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v65.lib.json
index 5df9620..de5a9c9 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v65.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v65.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v95.lib.json
index cd08b92..8fa2954 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
index de2656e..a482e52 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
index a136a2e..9fcefb7 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v65.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v65.lib.json
index 4bb05e1..a01ae7a 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v65.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v65.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v95.lib.json
index 106f490..7b61351 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
index da21cad..2f40261 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index ff517a6..d53464b 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_1v65_lv1v40.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_1v65_lv1v40.lib.json
index 661b9b6..e883966 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_1v65_lv1v40.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_1v65_lv1v40.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_1v65_lv1v60.lib.json
index 7326819..d021348 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
index fe44991..b67e2c2 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
index 44a7775..3153e37 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
index 4c7cf78..a4095fd 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
index c1cc850..86408b0 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_150C_1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_150C_1v65_lv1v60.lib.json
index 75632f9..f744582 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_150C_1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_150C_1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
index 82d53e0..009ed82 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v32_lv1v28.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v32_lv1v28.lib.json
index 3141360..93a3923 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v32_lv1v28.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v32_lv1v28.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v49_lv1v44.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v49_lv1v44.lib.json
index d43db6a..d1d36cf 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v49_lv1v44.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v49_lv1v44.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v35.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v35.lib.json
index 0cfa747..29ae0d0 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v35.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v35.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v40.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v40.lib.json
index 586731e..c2e004c 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v40.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v40.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
index 7074aeb..2e0b3c2 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index 03e0eda..f6b024b 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_2v64_lv1v80.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_2v64_lv1v80.lib.json
index 4335135..d071a5a 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_2v64_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_2v64_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_2v97_lv1v80.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_2v97_lv1v80.lib.json
index d50dd52..d9f1f4e 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_2v97_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_2v97_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_3v30_lv1v80.lib.json
index 9637591..4b537ff 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_025C_3v30_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_100C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_100C_3v30_lv1v80.lib.json
index f256cbd..4ad66e4 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_100C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_100C_3v30_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_150C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_150C_3v30_lv1v80.lib.json
index b7cfe39..7f08cf7 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_150C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1__tt_150C_3v30_lv1v80.lib.json
@@ -38,19 +38,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_085C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_085C_5v50_lv1v95.lib.json
index bfda318..ab20ad5 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_085C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_085C_5v50_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
index e5f83ff..f98251e 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_100C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_100C_5v50_lv1v95.lib.json
index 1f3e2dd..e86f400 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_100C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_100C_5v50_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_150C_5v50_lv1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_150C_5v50_lv1v95.lib.json
index 3d925cc..29a05d3 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_150C_5v50_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_150C_5v50_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_4v40_lv1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_4v40_lv1v95.lib.json
index 11c0bb1..6342364 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_4v40_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_4v40_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_4v95_lv1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_4v95_lv1v95.lib.json
index 2c44bcb..1f363a5 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_4v95_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_4v95_lv1v95.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 71eea6d..3869488 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
index 6dac4b2..697450a 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ff_n40C_5v50_lv1v95_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
index d07ed07..835c4e8 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lv1v40.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lv1v40.lib.json
index e196a9f..92b411f 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lv1v40.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lv1v40.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lv1v60.lib.json
index a521be8..0772253 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_100C_5v50_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index 45266dd..c1a679c 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lv1v35.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
index b1bee7a..d4f7cdd 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lv1v35.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
index 91e0c4d..0a0b8db 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvff_lvss_n40C_5v50_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v65.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v65.lib.json
index b811243..5acb973 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v65.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v95.lib.json
index 9663784..da1b601 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
index 13c8713..aec3e77 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_1v95_lowhv1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
index e6e5fad..2afee60 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_100C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v65.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v65.lib.json
index 10772f2..ef724f3 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v65.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v95.lib.json
index 1f3cd49..6fdef80 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
index f9e57ec..7b49139 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_1v95_lowhv1v65.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
index 9ed2833..dfba3a1 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__hvss_lvff_n40C_5v50_lowhv1v65_lv1v95.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_1v65_lv1v40.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_1v65_lv1v40.lib.json
index b556402..1af3732 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_1v65_lv1v40.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_1v65_lv1v40.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_1v65_lv1v60.lib.json
index cb2fb03..30c5195 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
index f6a678e..544c7ff 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_2v40_lowhv1v65_lv1v60.lib.json
@@ -18,19 +18,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
index 6d9d2b6..9adc788 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_2v70_lowhv1v65_lv1v60.lib.json
@@ -18,19 +18,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
index 75da224..f07ee1b 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_3v00_lowhv1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
index 50c039e..a099860 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_100C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_150C_1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_150C_1v65_lv1v60.lib.json
index f3756e4..21c59ad 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_150C_1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_150C_1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
index 88f0ef2..735703c 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_150C_3v00_lowhv1v65_lv1v60.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v32_lv1v28.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v32_lv1v28.lib.json
index a82c2f0..09147b7 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v32_lv1v28.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v32_lv1v28.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v49_lv1v44.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v49_lv1v44.lib.json
index 3898d53..5067635 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v49_lv1v44.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v49_lv1v44.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v35.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v35.lib.json
index 406e50c..75df49d 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v35.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v35.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v40.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v40.lib.json
index 7d7b6ae..a054a33 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v40.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v40.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
index 633eefa..46a137f 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_1v65_lv1v60_ccsnoise.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
index aa6b8a6..4cd3be9 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__ss_n40C_5v50_lowhv1v65_lv1v60.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_2v64_lv1v80.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_2v64_lv1v80.lib.json
index 634907b..be417c1 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_2v64_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_2v64_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_2v97_lv1v80.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_2v97_lv1v80.lib.json
index 4bb786b..855dea9 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_2v97_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_2v97_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_3v30_lv1v80.lib.json
index fca7e0d..a219537 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_025C_3v30_lv1v80.lib.json
@@ -30,19 +30,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_100C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_100C_3v30_lv1v80.lib.json
index f3e0d06..bcc1986 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_100C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_100C_3v30_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_150C_3v30_lv1v80.lib.json b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_150C_3v30_lv1v80.lib.json
index d3d107b..c090ba5 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_150C_3v30_lv1v80.lib.json
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1__tt_150C_3v30_lv1v80.lib.json
@@ -28,19 +28,22 @@
},
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
- "std_cell_main_rail": "true",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_085C_5v50.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_085C_5v50.lib.json
index eee6611..518c0fb 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_085C_5v50.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_085C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_100C_5v50.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_100C_5v50.lib.json
index c0d20cf..ff33517 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_100C_5v50.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_100C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_150C_5v50.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_150C_5v50.lib.json
index 8212555..eb9c873 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_150C_5v50.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_4v40.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_4v40.lib.json
index d9a3da9..f426725 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_4v40.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_4v95.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_4v95.lib.json
index b88c5e5..12b922c 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_4v95.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_5v50_ccsnoise.lib.json
index de5190a..72d0f23 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_1v65.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_1v65.lib.json
index bc6bed3..11d69d9 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_1v65.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_1v95.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_1v95.lib.json
index 947d9e7..712bdba 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_1v95.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_3v00.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_3v00.lib.json
index 28b758c..5d22ac3 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_3v00.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_150C_1v65.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_150C_1v65.lib.json
index 6731727..022d504 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_150C_1v65.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v32.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v32.lib.json
index c0a7020..945ca56 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v32.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v32.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v49.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v49.lib.json
index 77e250d..af5edee 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v49.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v49.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v65_ccsnoise.lib.json
index e8314a9..820d1fb 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v95.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v95.lib.json
index a149edb..894110d 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v95.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__ss_n40C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__tt_025C_3v30.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__tt_025C_3v30.lib.json
index 74414c6..e372c65 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__tt_025C_3v30.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__tt_025C_3v30.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1__tt_100C_3v30.lib.json b/cells/mux2/sky130_fd_sc_hvl__mux2_1__tt_100C_3v30.lib.json
index 70d025b..cb53776 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1__tt_100C_3v30.lib.json
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_085C_5v50.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_085C_5v50.lib.json
index 76e3972..1e9ed8c 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_085C_5v50.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_085C_5v50.lib.json
@@ -264,18 +264,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_100C_5v50.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_100C_5v50.lib.json
index 96a8f1b..cecb521 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_100C_5v50.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_100C_5v50.lib.json
@@ -264,18 +264,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_150C_5v50.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_150C_5v50.lib.json
index 8b268b9..0e0c791 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_150C_5v50.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_4v40.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_4v40.lib.json
index 72e139f..6c02705 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_4v40.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_4v95.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_4v95.lib.json
index 037b010..e2c5b3e 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_4v95.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_5v50_ccsnoise.lib.json
index 6f8ace1..b18a08c 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_1v65.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_1v65.lib.json
index 5cf5fcf..2d00dbd 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_1v65.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_1v95.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_1v95.lib.json
index 4019615..7c416f0 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_1v95.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_1v95.lib.json
@@ -264,18 +264,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_3v00.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_3v00.lib.json
index 191a7ee..84f6b12 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_3v00.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_150C_1v65.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_150C_1v65.lib.json
index 0755546..b75962d 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_150C_1v65.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v32.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v32.lib.json
index e8fe061..c525907 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v32.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v32.lib.json
@@ -264,18 +264,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v49.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v49.lib.json
index ba7901a..e4f1f7e 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v49.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v49.lib.json
@@ -264,18 +264,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v65_ccsnoise.lib.json
index 2716aec..52c631d 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v95.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v95.lib.json
index 42637fd..84958b8 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v95.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__ss_n40C_1v95.lib.json
@@ -264,18 +264,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__tt_025C_3v30.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__tt_025C_3v30.lib.json
index ed8d86a..771e6d6 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__tt_025C_3v30.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__tt_025C_3v30.lib.json
@@ -264,18 +264,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1__tt_100C_3v30.lib.json b/cells/mux4/sky130_fd_sc_hvl__mux4_1__tt_100C_3v30.lib.json
index ec6c275..ea1e4fb 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1__tt_100C_3v30.lib.json
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A0": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_085C_5v50.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_085C_5v50.lib.json
index 7ab33c3..2b32b16 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_085C_5v50.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_085C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_100C_5v50.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_100C_5v50.lib.json
index 7020baa..ed0c270 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_100C_5v50.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_100C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_150C_5v50.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_150C_5v50.lib.json
index c788833..727aa19 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_150C_5v50.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_4v40.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_4v40.lib.json
index cc64a52..3be9e0e 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_4v40.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_4v95.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_4v95.lib.json
index e05d6d0..43cd64d 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_4v95.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_5v50_ccsnoise.lib.json
index 258a84b..71a1cad 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_1v65.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_1v65.lib.json
index b10d709..4defccb 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_1v65.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_1v95.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_1v95.lib.json
index 22295f6..8c9ba49 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_1v95.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_3v00.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_3v00.lib.json
index ee8db8d..93a5f3a 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_3v00.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_150C_1v65.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_150C_1v65.lib.json
index 30753cf..61303f0 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_150C_1v65.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v32.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v32.lib.json
index f935ebc..b7cdd00 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v32.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v32.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v49.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v49.lib.json
index aae59b4..988f616 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v49.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v49.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v65_ccsnoise.lib.json
index 45148d5..1765904 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v95.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v95.lib.json
index e7b6280..681b50c 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v95.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__ss_n40C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__tt_025C_3v30.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__tt_025C_3v30.lib.json
index 21fe109..ab923c2 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__tt_025C_3v30.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__tt_025C_3v30.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1__tt_100C_3v30.lib.json b/cells/nand2/sky130_fd_sc_hvl__nand2_1__tt_100C_3v30.lib.json
index 8ab9b5c..ee1e677 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1__tt_100C_3v30.lib.json
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_085C_5v50.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_085C_5v50.lib.json
index 19a2718..6eb7d6d 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_085C_5v50.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_085C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_100C_5v50.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_100C_5v50.lib.json
index c56e830..e2c172a 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_100C_5v50.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_100C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_150C_5v50.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_150C_5v50.lib.json
index 829fdd8..91b8a8d 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_150C_5v50.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_4v40.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_4v40.lib.json
index 0f58bb8..3153912 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_4v40.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_4v95.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_4v95.lib.json
index 9fff46d..e471c51 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_4v95.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_5v50_ccsnoise.lib.json
index 5baf8df..2dd9115 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_1v65.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_1v65.lib.json
index 2ae8a13..69a7092 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_1v65.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_1v95.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_1v95.lib.json
index 9d61df7..da5dd57 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_1v95.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_3v00.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_3v00.lib.json
index e1d19b8..a9b3cd0 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_3v00.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_150C_1v65.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_150C_1v65.lib.json
index fe679ea..11ad6ea 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_150C_1v65.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v32.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v32.lib.json
index 3444bf9..c73928c 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v32.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v32.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v49.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v49.lib.json
index fa22ec0..55cce36 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v49.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v49.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v65_ccsnoise.lib.json
index ca371c4..fcddc17 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v95.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v95.lib.json
index 5299e02..8f2a677 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v95.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__ss_n40C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__tt_025C_3v30.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__tt_025C_3v30.lib.json
index a04057b..1ac94cd 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__tt_025C_3v30.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__tt_025C_3v30.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1__tt_100C_3v30.lib.json b/cells/nand3/sky130_fd_sc_hvl__nand3_1__tt_100C_3v30.lib.json
index 23aaf10..cb7765f 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1__tt_100C_3v30.lib.json
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_085C_5v50.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_085C_5v50.lib.json
index 72033ae..4308761 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_085C_5v50.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_085C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_100C_5v50.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_100C_5v50.lib.json
index 0b3f609..81ac1b2 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_100C_5v50.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_100C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_150C_5v50.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_150C_5v50.lib.json
index 36478e0..da7ac44 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_150C_5v50.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_4v40.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_4v40.lib.json
index e26af0b..bd04a3d 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_4v40.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_4v95.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_4v95.lib.json
index cf625e3..2f9e3dc 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_4v95.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_5v50_ccsnoise.lib.json
index 2d649bd..2183c8d 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_1v65.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_1v65.lib.json
index 4dd2bf6..b65084c 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_1v65.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_1v95.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_1v95.lib.json
index 155de4d..ad06908 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_1v95.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_3v00.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_3v00.lib.json
index f50bae9..1c20cd3 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_3v00.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_150C_1v65.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_150C_1v65.lib.json
index 31240fb..b88b4a0 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_150C_1v65.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v32.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v32.lib.json
index f93c77d..1aa71ec 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v32.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v32.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v49.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v49.lib.json
index d3a062f..ab17578 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v49.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v49.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v65_ccsnoise.lib.json
index 9cd878c..b2918c8 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v95.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v95.lib.json
index 6733b07..b08bfce 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v95.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__ss_n40C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__tt_025C_3v30.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__tt_025C_3v30.lib.json
index c081069..e066222 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__tt_025C_3v30.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__tt_025C_3v30.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1__tt_100C_3v30.lib.json b/cells/nor2/sky130_fd_sc_hvl__nor2_1__tt_100C_3v30.lib.json
index b26bc49..b1a0249 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1__tt_100C_3v30.lib.json
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_085C_5v50.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_085C_5v50.lib.json
index 68be2b7..be66984 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_085C_5v50.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_085C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_100C_5v50.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_100C_5v50.lib.json
index aa3c3b5..48c1647 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_100C_5v50.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_100C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_150C_5v50.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_150C_5v50.lib.json
index 37fbffc..3a0de26 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_150C_5v50.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_4v40.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_4v40.lib.json
index 465dcfc..df3eb22 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_4v40.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_4v95.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_4v95.lib.json
index ab033e0..0577a36 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_4v95.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_5v50_ccsnoise.lib.json
index 1ac42ff..6e43098 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_1v65.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_1v65.lib.json
index bdb5116..a0491cb 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_1v65.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_1v95.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_1v95.lib.json
index 2376148..39b798e 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_1v95.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_3v00.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_3v00.lib.json
index d190be1..e0e9845 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_3v00.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_150C_1v65.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_150C_1v65.lib.json
index 94e1060..9b85d21 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_150C_1v65.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v32.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v32.lib.json
index 4d2e983..e3c3821 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v32.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v32.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v49.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v49.lib.json
index 39f59c4..f614dc1 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v49.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v49.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v65_ccsnoise.lib.json
index b9c2e71..9a150ff 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v95.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v95.lib.json
index 1a8e8dd..5b99394 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v95.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__ss_n40C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__tt_025C_3v30.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__tt_025C_3v30.lib.json
index 730fab0..b692987 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__tt_025C_3v30.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__tt_025C_3v30.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1__tt_100C_3v30.lib.json b/cells/nor3/sky130_fd_sc_hvl__nor3_1__tt_100C_3v30.lib.json
index 5e9cfeb..d9b3fcb 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1__tt_100C_3v30.lib.json
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_085C_5v50.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_085C_5v50.lib.json
index aa3259f..2223445 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_085C_5v50.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_085C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_100C_5v50.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_100C_5v50.lib.json
index 8ccd137..f77c122 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_100C_5v50.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_100C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_150C_5v50.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_150C_5v50.lib.json
index 8b5e59d..933a5ba 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_150C_5v50.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_4v40.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_4v40.lib.json
index 735b575..73aac01 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_4v40.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_4v95.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_4v95.lib.json
index c99b406..768a186 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_4v95.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_5v50_ccsnoise.lib.json
index 70f80c9..186fea1 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_1v65.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_1v65.lib.json
index 006add4..2a0264c 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_1v65.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_1v95.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_1v95.lib.json
index 1ab5950..b90e727 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_1v95.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_3v00.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_3v00.lib.json
index 8662e38..3f28922 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_3v00.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_150C_1v65.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_150C_1v65.lib.json
index 0c38577..2dae899 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_150C_1v65.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v32.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v32.lib.json
index ed6e073..011bff0 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v32.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v32.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v49.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v49.lib.json
index ece66b2..c7e2198 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v49.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v49.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v65_ccsnoise.lib.json
index 1f6e223..f894b80 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v95.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v95.lib.json
index 30dd355..b138b43 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v95.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__ss_n40C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__tt_025C_3v30.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__tt_025C_3v30.lib.json
index 91ef25e..c98a67a 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__tt_025C_3v30.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__tt_025C_3v30.lib.json
@@ -6,18 +6,22 @@
"driver_waveform_rise": "ramp",
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1__tt_100C_3v30.lib.json b/cells/o21a/sky130_fd_sc_hvl__o21a_1__tt_100C_3v30.lib.json
index 231d5e2..9e375f2 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1__tt_100C_3v30.lib.json
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_085C_5v50.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_085C_5v50.lib.json
index 1abeccb..2f1c9e5 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_085C_5v50.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_085C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_100C_5v50.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_100C_5v50.lib.json
index 256ee61..d61eefd 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_100C_5v50.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_100C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_150C_5v50.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_150C_5v50.lib.json
index 48443b0..f92b947 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_150C_5v50.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_4v40.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_4v40.lib.json
index 5fe9bac..2b0472c 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_4v40.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_4v95.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_4v95.lib.json
index 83559b1..6bc914e 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_4v95.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_5v50_ccsnoise.lib.json
index 70fba9a..ce6ff44 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_1v65.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_1v65.lib.json
index ee4cb26..e0f1d0f 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_1v65.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_1v95.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_1v95.lib.json
index 0395faa..26c717f 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_1v95.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_3v00.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_3v00.lib.json
index 74a6c7e..da744bb 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_3v00.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_150C_1v65.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_150C_1v65.lib.json
index ef6614d..640cd28 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_150C_1v65.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v32.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v32.lib.json
index 283982a..8330202 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v32.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v32.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v49.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v49.lib.json
index da88443..6acb30d 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v49.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v49.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v65_ccsnoise.lib.json
index b2fb2e8..de1bd43 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v95.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v95.lib.json
index 5d75e46..a4291ec 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v95.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__ss_n40C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__tt_025C_3v30.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__tt_025C_3v30.lib.json
index f582172..4475748 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__tt_025C_3v30.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__tt_025C_3v30.lib.json
@@ -6,18 +6,22 @@
"driver_waveform_rise": "ramp",
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__tt_100C_3v30.lib.json b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__tt_100C_3v30.lib.json
index 555b477..1a66696 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__tt_100C_3v30.lib.json
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_085C_5v50.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_085C_5v50.lib.json
index 228cafe..fe291c3 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_085C_5v50.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_085C_5v50.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_100C_5v50.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_100C_5v50.lib.json
index c954b58..62febe4 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_100C_5v50.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_100C_5v50.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_150C_5v50.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_150C_5v50.lib.json
index dc580e5..7a8c4ed 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_150C_5v50.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_4v40.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_4v40.lib.json
index 309bf49..9f86707 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_4v40.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_4v95.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_4v95.lib.json
index e87546e..286c8f6 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_4v95.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_5v50_ccsnoise.lib.json
index c3635f9..81802e2 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_1v65.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_1v65.lib.json
index 3381bdd..4ad6d4f 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_1v65.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_1v95.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_1v95.lib.json
index be79615..9151181 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_1v95.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_1v95.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_3v00.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_3v00.lib.json
index 0eca475..1fe13c7 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_3v00.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_150C_1v65.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_150C_1v65.lib.json
index 237b553..649863e 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_150C_1v65.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v32.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v32.lib.json
index fbad2bb..cd1e639 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v32.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v32.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v49.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v49.lib.json
index 3a453ce..724ec88 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v49.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v49.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v65_ccsnoise.lib.json
index e4b46fd..1ddcb3a 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v95.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v95.lib.json
index dd53da6..1fc3d7b 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v95.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__ss_n40C_1v95.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__tt_025C_3v30.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__tt_025C_3v30.lib.json
index 9eaad4c..2113fb9 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__tt_025C_3v30.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__tt_025C_3v30.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1__tt_100C_3v30.lib.json b/cells/o22a/sky130_fd_sc_hvl__o22a_1__tt_100C_3v30.lib.json
index 0da5601..e1583ad 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1__tt_100C_3v30.lib.json
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_085C_5v50.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_085C_5v50.lib.json
index d3b477f..f2a07da 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_085C_5v50.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_085C_5v50.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_100C_5v50.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_100C_5v50.lib.json
index 42d7197..91b4401 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_100C_5v50.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_100C_5v50.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_150C_5v50.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_150C_5v50.lib.json
index c68b020..fb06c64 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_150C_5v50.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_4v40.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_4v40.lib.json
index da63b0d..5f630c3 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_4v40.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_4v95.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_4v95.lib.json
index f51c750..68e894e 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_4v95.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_5v50_ccsnoise.lib.json
index 3f718f9..504346e 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_1v65.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_1v65.lib.json
index d5fd1ad..3be10c5 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_1v65.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_1v95.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_1v95.lib.json
index d1a8a97..d689414 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_1v95.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_1v95.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_3v00.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_3v00.lib.json
index 075fac3..b63ede5 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_3v00.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_150C_1v65.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_150C_1v65.lib.json
index 68c6344..ebc5c9d 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_150C_1v65.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v32.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v32.lib.json
index 11ce591..6c577a4 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v32.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v32.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v49.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v49.lib.json
index d4a150d..f47047b 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v49.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v49.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v65_ccsnoise.lib.json
index 8c74de7..4dbd059 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v95.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v95.lib.json
index baff83d..d5f5739 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v95.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__ss_n40C_1v95.lib.json
@@ -72,18 +72,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__tt_025C_3v30.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__tt_025C_3v30.lib.json
index cf2b2f4..f97a1c3 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__tt_025C_3v30.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__tt_025C_3v30.lib.json
@@ -6,18 +6,22 @@
"driver_waveform_rise": "ramp",
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__tt_100C_3v30.lib.json b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__tt_100C_3v30.lib.json
index 67027b7..8af592f 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__tt_100C_3v30.lib.json
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A1": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_085C_5v50.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_085C_5v50.lib.json
index ff71895..083b1bb 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_085C_5v50.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_085C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_100C_5v50.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_100C_5v50.lib.json
index 6dddc73..48783af 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_100C_5v50.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_100C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_150C_5v50.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_150C_5v50.lib.json
index 721d19e..e264108 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_150C_5v50.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_4v40.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_4v40.lib.json
index 3d31518..a68663d 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_4v40.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_4v95.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_4v95.lib.json
index 7df3763..bdf6649 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_4v95.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_5v50_ccsnoise.lib.json
index f0a4d90..009ff7b 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_1v65.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_1v65.lib.json
index 810821f..b6f353d 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_1v65.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_1v95.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_1v95.lib.json
index 029536d..34a35a7 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_1v95.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_3v00.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_3v00.lib.json
index 26ddbd9..f4574db 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_3v00.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_150C_1v65.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_150C_1v65.lib.json
index b38bb5f..074a79e 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_150C_1v65.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v32.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v32.lib.json
index f751973..ce03a94 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v32.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v32.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v49.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v49.lib.json
index 28b986f..c41e54d 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v49.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v49.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v65_ccsnoise.lib.json
index afc95a3..d994517 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v95.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v95.lib.json
index c6ec4ee..4748307 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v95.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__ss_n40C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__tt_025C_3v30.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__tt_025C_3v30.lib.json
index e4eee20..d067c3b 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__tt_025C_3v30.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__tt_025C_3v30.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1__tt_100C_3v30.lib.json b/cells/or2/sky130_fd_sc_hvl__or2_1__tt_100C_3v30.lib.json
index e0dab27..8ad5f13 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1__tt_100C_3v30.lib.json
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_085C_5v50.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_085C_5v50.lib.json
index fa06957..f3e9c1e 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_085C_5v50.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_085C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_100C_5v50.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_100C_5v50.lib.json
index 162b8bd..190b021 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_100C_5v50.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_100C_5v50.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_150C_5v50.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_150C_5v50.lib.json
index 741bf9c..bc1e743 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_150C_5v50.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_4v40.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_4v40.lib.json
index 6922444..68a35c7 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_4v40.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_4v95.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_4v95.lib.json
index 6d2b7ad..decc5f4 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_4v95.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_5v50_ccsnoise.lib.json
index bb99bd1..783cee4 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_1v65.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_1v65.lib.json
index 381f91b..b09b6e1 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_1v65.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_1v95.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_1v95.lib.json
index 5235a81..4976575 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_1v95.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_3v00.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_3v00.lib.json
index 2fedd5f..f541dda 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_3v00.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_150C_1v65.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_150C_1v65.lib.json
index e08a711..c9ece17 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_150C_1v65.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v32.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v32.lib.json
index 9853ef6..e7e0b23 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v32.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v32.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v49.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v49.lib.json
index f7e93c9..2194b38 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v49.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v49.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v65_ccsnoise.lib.json
index e1d2717..2901d39 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v95.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v95.lib.json
index 953d7d6..20f35bc 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v95.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__ss_n40C_1v95.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__tt_025C_3v30.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__tt_025C_3v30.lib.json
index 62db9fd..dde37cc 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__tt_025C_3v30.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__tt_025C_3v30.lib.json
@@ -40,18 +40,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1__tt_100C_3v30.lib.json b/cells/or3/sky130_fd_sc_hvl__or3_1__tt_100C_3v30.lib.json
index c5b0412..658e15c 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1__tt_100C_3v30.lib.json
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_085C_5v50.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_085C_5v50.lib.json
index 84b6837..a35e658 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_085C_5v50.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_085C_5v50.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_100C_5v50.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_100C_5v50.lib.json
index 52abd78..14b6fc9 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_100C_5v50.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_100C_5v50.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_150C_5v50.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_150C_5v50.lib.json
index b538f93..30db5bc 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_150C_5v50.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_150C_5v50.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_4v40.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_4v40.lib.json
index 9a90c83..b86cc9b 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_4v40.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_4v40.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_4v95.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_4v95.lib.json
index 17d005e..8603da7 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_4v95.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_4v95.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_5v50_ccsnoise.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_5v50_ccsnoise.lib.json
index d5374a2..4ee8a74 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ff_n40C_5v50_ccsnoise.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_1v65.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_1v65.lib.json
index 933e0bc..c1732b8 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_1v65.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_1v65.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_1v95.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_1v95.lib.json
index beab68b..f3b6507 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_1v95.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_1v95.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_3v00.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_3v00.lib.json
index 6007288..d320465 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_3v00.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_100C_3v00.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_150C_1v65.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_150C_1v65.lib.json
index 5da3f7c..e38edab 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_150C_1v65.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_150C_1v65.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v32.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v32.lib.json
index aa226e0..19f8c89 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v32.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v32.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v49.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v49.lib.json
index a8f952a..905d529 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v49.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v49.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v65_ccsnoise.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v65_ccsnoise.lib.json
index b08d748..6c39375 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v65_ccsnoise.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v95.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v95.lib.json
index 222667a..6e32fac 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v95.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__ss_n40C_1v95.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__tt_025C_3v30.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__tt_025C_3v30.lib.json
index 059e57c..ec98d2f 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__tt_025C_3v30.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__tt_025C_3v30.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__tt_100C_3v30.lib.json b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__tt_100C_3v30.lib.json
index a15a546..65a920a 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__tt_100C_3v30.lib.json
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8__tt_100C_3v30.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_085C_5v50.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_085C_5v50.lib.json
index 0742f3a..f06b0f9 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_085C_5v50.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_085C_5v50.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_100C_5v50.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_100C_5v50.lib.json
index 0e6a76f..ad21587 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_100C_5v50.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_100C_5v50.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_150C_5v50.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_150C_5v50.lib.json
index 47d97d2..5766425 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_150C_5v50.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_150C_5v50.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_4v40.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_4v40.lib.json
index 699de33..4ea9178 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_4v40.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_4v40.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_4v95.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_4v95.lib.json
index 8c0d406..0c92aae 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_4v95.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_4v95.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_5v50_ccsnoise.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_5v50_ccsnoise.lib.json
index ce8dceb..e2ebdf6 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ff_n40C_5v50_ccsnoise.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_1v65.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_1v65.lib.json
index e8fbc06..55a323d 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_1v65.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_1v65.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_1v95.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_1v95.lib.json
index de31bd0..89a508f 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_1v95.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_1v95.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_3v00.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_3v00.lib.json
index 44416f9..f99725a 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_3v00.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_100C_3v00.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_150C_1v65.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_150C_1v65.lib.json
index 3682499..952784e 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_150C_1v65.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_150C_1v65.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v32.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v32.lib.json
index a7cbf61..ae006a8 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v32.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v32.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v49.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v49.lib.json
index 2992fd1..70b9c76 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v49.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v49.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v65_ccsnoise.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v65_ccsnoise.lib.json
index 3ecb942..67944fc 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v65_ccsnoise.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v95.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v95.lib.json
index b17b4f7..baffbb2 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v95.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__ss_n40C_1v95.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__tt_025C_3v30.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__tt_025C_3v30.lib.json
index 68cb83a..ccf8169 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__tt_025C_3v30.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__tt_025C_3v30.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__tt_100C_3v30.lib.json b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__tt_100C_3v30.lib.json
index 9ad3e7d..3c166b2 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__tt_100C_3v30.lib.json
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8__tt_100C_3v30.lib.json
@@ -18,18 +18,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_085C_5v50.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_085C_5v50.lib.json
index da53972..9269541 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_085C_5v50.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_085C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_100C_5v50.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_100C_5v50.lib.json
index d8a0d40..2521136 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_100C_5v50.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_100C_5v50.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_150C_5v50.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_150C_5v50.lib.json
index 772c1e6..4b6e082 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_150C_5v50.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_4v40.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_4v40.lib.json
index 54a93ac..4bfc545 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_4v40.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_4v95.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_4v95.lib.json
index eff4a66..5ec1c63 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_4v95.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_5v50_ccsnoise.lib.json
index c7f7439..54e8339 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_1v65.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_1v65.lib.json
index 87f38c0..3f28fc2 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_1v65.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_1v95.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_1v95.lib.json
index 704945d..f09d69a 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_1v95.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_3v00.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_3v00.lib.json
index b871a54..2c52a91 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_3v00.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_150C_1v65.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_150C_1v65.lib.json
index 9033fba..07d65ee 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_150C_1v65.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v32.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v32.lib.json
index b99daa4..20f65d0 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v32.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v32.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v49.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v49.lib.json
index a036ed1..e5d5a32 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v49.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v49.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v65_ccsnoise.lib.json
index 35d6e4c..2fff4f0 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v95.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v95.lib.json
index d864f01..5fd64b2 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v95.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__ss_n40C_1v95.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__tt_025C_3v30.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__tt_025C_3v30.lib.json
index 8c377f8..12505c1 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__tt_025C_3v30.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__tt_025C_3v30.lib.json
@@ -16,18 +16,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__tt_100C_3v30.lib.json b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__tt_100C_3v30.lib.json
index 7f7c68d..a5474c9 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__tt_100C_3v30.lib.json
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_085C_5v50.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_085C_5v50.lib.json
index e917e12..f2684e6 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_085C_5v50.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_085C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_100C_5v50.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_100C_5v50.lib.json
index c768ee9..6cd4667 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_100C_5v50.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_100C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_150C_5v50.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_150C_5v50.lib.json
index 905848e..306859a 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_150C_5v50.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_150C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_4v40.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_4v40.lib.json
index ff29613..bab0015 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_4v40.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_4v40.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_4v95.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_4v95.lib.json
index bcc3081..7191eec 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_4v95.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_4v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_5v50_ccsnoise.lib.json
index 031d631..1bcb34a 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -139,18 +139,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_1v65.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_1v65.lib.json
index 3366a63..7aed9e4 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_1v65.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_1v65.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_1v95.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_1v95.lib.json
index 01017d0..dbc9de3 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_1v95.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_1v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_3v00.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_3v00.lib.json
index 1f69f85..3ef6856 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_3v00.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_100C_3v00.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_150C_1v65.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_150C_1v65.lib.json
index b134f52..7820063 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_150C_1v65.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_150C_1v65.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v32.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v32.lib.json
index dffd696..b92afda 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v32.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v32.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v49.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v49.lib.json
index 4467b28..ee9df61 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v49.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v49.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v65_ccsnoise.lib.json
index a093fe7..66107e0 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v95.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v95.lib.json
index 81a0d62..eda57cd 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v95.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__ss_n40C_1v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__tt_025C_3v30.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__tt_025C_3v30.lib.json
index 0036c81..2e09704 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__tt_025C_3v30.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__tt_025C_3v30.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__tt_100C_3v30.lib.json b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__tt_100C_3v30.lib.json
index d0cb249..3468703 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__tt_100C_3v30.lib.json
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1__tt_100C_3v30.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_085C_5v50.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_085C_5v50.lib.json
index 7a4b1c7..89d156d 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_085C_5v50.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_085C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_100C_5v50.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_100C_5v50.lib.json
index 8019993..39d5b19 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_100C_5v50.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_100C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_150C_5v50.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_150C_5v50.lib.json
index 47cad9a..e9f0931 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_150C_5v50.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_150C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_4v40.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_4v40.lib.json
index 9975de3..35b4e15 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_4v40.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_4v40.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_4v95.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_4v95.lib.json
index 80d7740..ecb92ab 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_4v95.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_4v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_5v50_ccsnoise.lib.json
index b39d2e0..f60ef38 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -139,18 +139,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_1v65.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_1v65.lib.json
index bbdfe4d..ef808f7 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_1v65.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_1v65.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_1v95.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_1v95.lib.json
index 38c52d1..8e620f2 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_1v95.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_1v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_3v00.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_3v00.lib.json
index 5240bde..4bf103a 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_3v00.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_100C_3v00.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_150C_1v65.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_150C_1v65.lib.json
index 7013d47..a9b2d22 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_150C_1v65.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_150C_1v65.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v32.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v32.lib.json
index 7d10345..410827e 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v32.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v32.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v49.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v49.lib.json
index be3936f..2786b77 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v49.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v49.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v65_ccsnoise.lib.json
index 8a45014..547b65a 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v95.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v95.lib.json
index 9c1b15e..dc66d4e 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v95.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__ss_n40C_1v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__tt_025C_3v30.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__tt_025C_3v30.lib.json
index 69c96c8..5cf51e0 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__tt_025C_3v30.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__tt_025C_3v30.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__tt_100C_3v30.lib.json b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__tt_100C_3v30.lib.json
index c1d0a69..bc855ed 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__tt_100C_3v30.lib.json
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1__tt_100C_3v30.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_085C_5v50.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_085C_5v50.lib.json
index c1ffe87..096b790 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_085C_5v50.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_085C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_100C_5v50.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_100C_5v50.lib.json
index dcd259e..9b6bb52 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_100C_5v50.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_100C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_150C_5v50.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_150C_5v50.lib.json
index db4eef7..70e938d 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_150C_5v50.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_150C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_4v40.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_4v40.lib.json
index e8e8bb6..ca68d40 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_4v40.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_4v40.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_4v95.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_4v95.lib.json
index 72edaf9..586bdbc 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_4v95.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_4v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_5v50_ccsnoise.lib.json
index c46c72f..28858b6 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -139,18 +139,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_1v65.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_1v65.lib.json
index 4e3c618..707e761 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_1v65.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_1v65.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_1v95.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_1v95.lib.json
index 90494f7..dbb2603 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_1v95.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_1v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_3v00.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_3v00.lib.json
index e70d7ef..5e93571 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_3v00.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_100C_3v00.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_150C_1v65.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_150C_1v65.lib.json
index a9644ff..5c30300 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_150C_1v65.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_150C_1v65.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v32.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v32.lib.json
index b467684..de2ad82 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v32.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v32.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v49.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v49.lib.json
index cd0f92f..ec26df6 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v49.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v49.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v65_ccsnoise.lib.json
index 2bf65e5..289dfeb 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v95.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v95.lib.json
index b50d228..f57df52 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v95.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__ss_n40C_1v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__tt_025C_3v30.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__tt_025C_3v30.lib.json
index 95f6c4e..a0f36ab 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__tt_025C_3v30.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__tt_025C_3v30.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__tt_100C_3v30.lib.json b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__tt_100C_3v30.lib.json
index 7d266b6..9c147b6 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__tt_100C_3v30.lib.json
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1__tt_100C_3v30.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_085C_5v50.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_085C_5v50.lib.json
index aaa1a9d..ccd403a 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_085C_5v50.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_085C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_100C_5v50.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_100C_5v50.lib.json
index d4f1129..56b2863 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_100C_5v50.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_100C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_150C_5v50.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_150C_5v50.lib.json
index a8d9cac..022ff99 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_150C_5v50.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_150C_5v50.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_4v40.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_4v40.lib.json
index 3739164..64c1606 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_4v40.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_4v40.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_4v95.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_4v95.lib.json
index 4fd2d22..78c58c7 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_4v95.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_4v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_5v50_ccsnoise.lib.json
index 4e120c9..25f404a 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -139,18 +139,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_1v65.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_1v65.lib.json
index 5d1db7d..28ff0e2 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_1v65.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_1v65.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_1v95.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_1v95.lib.json
index a57c2a1..d7be756 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_1v95.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_1v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_3v00.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_3v00.lib.json
index 733cb3e..eaff43a 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_3v00.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_100C_3v00.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_150C_1v65.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_150C_1v65.lib.json
index 9302792..17ab3ef 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_150C_1v65.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_150C_1v65.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v32.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v32.lib.json
index 7853a11..62f127e 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v32.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v32.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v49.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v49.lib.json
index d26e3ca..8094b99 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v49.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v49.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v65_ccsnoise.lib.json
index 994fcf2..34bc681 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v95.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v95.lib.json
index 488d998..dc93897 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v95.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__ss_n40C_1v95.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__tt_025C_3v30.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__tt_025C_3v30.lib.json
index 35a16fd..ec21f47 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__tt_025C_3v30.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__tt_025C_3v30.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__tt_100C_3v30.lib.json b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__tt_100C_3v30.lib.json
index 67e5dd3..6020a3e 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__tt_100C_3v30.lib.json
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1__tt_100C_3v30.lib.json
@@ -141,18 +141,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_085C_5v50.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_085C_5v50.lib.json
index afc9b7e..468868b 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_085C_5v50.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_085C_5v50.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_100C_5v50.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_100C_5v50.lib.json
index ba7a977..0df9dba 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_100C_5v50.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_100C_5v50.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_150C_5v50.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_150C_5v50.lib.json
index 558de45..e1a032e 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_150C_5v50.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_150C_5v50.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_4v40.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_4v40.lib.json
index 1808b2f..84ef339 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_4v40.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_4v40.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_4v95.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_4v95.lib.json
index 6962759..8f11c88 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_4v95.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_4v95.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_5v50_ccsnoise.lib.json
index 462bbf2..6e30743 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -74,18 +74,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_1v65.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_1v65.lib.json
index fcb73dc..6f02a47 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_1v65.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_1v65.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_1v95.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_1v95.lib.json
index e262e5a..1338d29 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_1v95.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_1v95.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_3v00.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_3v00.lib.json
index 9465551..f485b45 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_3v00.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_100C_3v00.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_150C_1v65.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_150C_1v65.lib.json
index 2f3f140..0113d3e 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_150C_1v65.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_150C_1v65.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v32.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v32.lib.json
index a869852..998aa7d 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v32.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v32.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v49.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v49.lib.json
index 8076dc6..ecadf60 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v49.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v49.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v65_ccsnoise.lib.json
index d1ca6f3..855bea5 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v95.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v95.lib.json
index 1ad2120..9d7f5f1 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v95.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__ss_n40C_1v95.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__tt_025C_3v30.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__tt_025C_3v30.lib.json
index 4a4c17a..81de0e2 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__tt_025C_3v30.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__tt_025C_3v30.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__tt_100C_3v30.lib.json b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__tt_100C_3v30.lib.json
index f648f98..2a346a8 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__tt_100C_3v30.lib.json
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1__tt_100C_3v30.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_085C_5v50.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_085C_5v50.lib.json
index 2932d38..ed90855 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_085C_5v50.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_085C_5v50.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_100C_5v50.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_100C_5v50.lib.json
index dd23830..d629984 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_100C_5v50.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_100C_5v50.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_150C_5v50.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_150C_5v50.lib.json
index 4625900..599ffc1 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_150C_5v50.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_150C_5v50.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_4v40.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_4v40.lib.json
index 90ce64e..6cc7ba0 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_4v40.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_4v40.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_4v95.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_4v95.lib.json
index 1a4df57..6cc106b 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_4v95.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_4v95.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_5v50_ccsnoise.lib.json
index 1ada0c4..079d76a 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -74,18 +74,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_1v65.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_1v65.lib.json
index 86a238b..d0394cc 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_1v65.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_1v65.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_1v95.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_1v95.lib.json
index aad453c..e122a02 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_1v95.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_1v95.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_3v00.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_3v00.lib.json
index d4b27e3..49195ed 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_3v00.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_100C_3v00.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_150C_1v65.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_150C_1v65.lib.json
index 3c2347f..5409157 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_150C_1v65.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_150C_1v65.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v32.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v32.lib.json
index 64959a3..32ae45b 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v32.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v32.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v49.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v49.lib.json
index fd269e5..4a6ce5b 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v49.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v49.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v65_ccsnoise.lib.json
index 2d27f36..1dd758e 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v95.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v95.lib.json
index d9379c0..120fa9d 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v95.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__ss_n40C_1v95.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__tt_025C_3v30.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__tt_025C_3v30.lib.json
index 382f5b7..42f1c93 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__tt_025C_3v30.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__tt_025C_3v30.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__tt_100C_3v30.lib.json b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__tt_100C_3v30.lib.json
index a854514..25a827b 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__tt_100C_3v30.lib.json
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1__tt_100C_3v30.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_085C_5v50.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_085C_5v50.lib.json
index ae80fcb..505b712 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_085C_5v50.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_085C_5v50.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_100C_5v50.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_100C_5v50.lib.json
index 53e887b..8822a15 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_100C_5v50.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_100C_5v50.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_150C_5v50.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_150C_5v50.lib.json
index b3d4e67..b62052b 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_150C_5v50.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_150C_5v50.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_4v40.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_4v40.lib.json
index ae58bff..73d9199 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_4v40.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_4v40.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_4v95.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_4v95.lib.json
index ad6acfc..9edb93a 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_4v95.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_4v95.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_5v50_ccsnoise.lib.json
index 6a3cfc6..7e9423e 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -39,18 +39,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_1v65.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_1v65.lib.json
index 616e7c4..222a8f5 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_1v65.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_1v65.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_1v95.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_1v95.lib.json
index 2b759b5..a7f89ce 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_1v95.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_1v95.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_3v00.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_3v00.lib.json
index 3dd4ef3..c416a94 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_3v00.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_100C_3v00.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_150C_1v65.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_150C_1v65.lib.json
index 3732f7e..439a8c7 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_150C_1v65.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_150C_1v65.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v32.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v32.lib.json
index 33623f1..019835a 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v32.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v32.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v49.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v49.lib.json
index 5661ad4..f92eed6 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v49.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v49.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v65_ccsnoise.lib.json
index 0ae42c2..872b280 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v95.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v95.lib.json
index 66ce585..750ba0c 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v95.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__ss_n40C_1v95.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__tt_025C_3v30.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__tt_025C_3v30.lib.json
index d11151b..6eb33b6 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__tt_025C_3v30.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__tt_025C_3v30.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__tt_100C_3v30.lib.json b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__tt_100C_3v30.lib.json
index b00962c..6587bd6 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__tt_100C_3v30.lib.json
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1__tt_100C_3v30.lib.json
@@ -41,18 +41,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,CLK": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_085C_5v50.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_085C_5v50.lib.json
index 0dd1e63..db91070 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_085C_5v50.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_085C_5v50.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_100C_5v50.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_100C_5v50.lib.json
index 7debd0e..8a1232b 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_100C_5v50.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_100C_5v50.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_150C_5v50.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_150C_5v50.lib.json
index 74a8526..12eae30 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_150C_5v50.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_150C_5v50.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_4v40.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_4v40.lib.json
index fcd0d5c..c9e2611 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_4v40.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_4v40.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_4v95.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_4v95.lib.json
index 62b7ecc..a2c461b 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_4v95.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_4v95.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_5v50_ccsnoise.lib.json
index 9e19b38..0d5df9d 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -106,18 +106,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_1v65.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_1v65.lib.json
index 1e2ed76..4ff4a06 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_1v65.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_1v65.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_1v95.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_1v95.lib.json
index c4e8634..0b38b98 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_1v95.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_1v95.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_3v00.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_3v00.lib.json
index e1b0df9..87f6262 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_3v00.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_100C_3v00.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_150C_1v65.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_150C_1v65.lib.json
index ed66843..0339b46 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_150C_1v65.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_150C_1v65.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v32.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v32.lib.json
index face775..ec144ee 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v32.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v32.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v49.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v49.lib.json
index 93b901d..88df280 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v49.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v49.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v65_ccsnoise.lib.json
index 567695a..42f064c 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v95.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v95.lib.json
index d98d2f8..c82c6fb 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v95.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__ss_n40C_1v95.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__tt_025C_3v30.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__tt_025C_3v30.lib.json
index 6cdf24e..78bddbb 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__tt_025C_3v30.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__tt_025C_3v30.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__tt_100C_3v30.lib.json b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__tt_100C_3v30.lib.json
index f51bc3a..2cbd9d4 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__tt_100C_3v30.lib.json
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1__tt_100C_3v30.lib.json
@@ -76,18 +76,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,D": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_085C_5v50.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_085C_5v50.lib.json
index 8db3a14..5174dc8 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_085C_5v50.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_085C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_100C_5v50.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_100C_5v50.lib.json
index 97613a2..51b4dc4 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_100C_5v50.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_100C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_150C_5v50.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_150C_5v50.lib.json
index c6de956..4d90af3 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_150C_5v50.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_4v40.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_4v40.lib.json
index fc4ebf9..ccaf592 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_4v40.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_4v95.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_4v95.lib.json
index 89f74dd..f7c6ed8 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_4v95.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_5v50_ccsnoise.lib.json
index e5192f4..b226e6d 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_1v65.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_1v65.lib.json
index 7d84e1d..6b25e0c 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_1v65.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_1v95.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_1v95.lib.json
index 550a5f6..5318341 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_1v95.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_3v00.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_3v00.lib.json
index 73e38d8..946d402 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_3v00.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_150C_1v65.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_150C_1v65.lib.json
index 453d81b..1c145e1 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_150C_1v65.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v32.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v32.lib.json
index df68dcd..2103c70 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v32.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v32.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v49.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v49.lib.json
index 0544b84..3634b71 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v49.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v49.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v65_ccsnoise.lib.json
index f2defce..a22b3ce 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v95.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v95.lib.json
index 3686df5..18130f3 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v95.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__ss_n40C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__tt_025C_3v30.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__tt_025C_3v30.lib.json
index f1c0db0..cf6436c 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__tt_025C_3v30.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__tt_025C_3v30.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__tt_100C_3v30.lib.json b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__tt_100C_3v30.lib.json
index 97a491b..fb36769 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__tt_100C_3v30.lib.json
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_085C_5v50.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_085C_5v50.lib.json
index 57428e8..0f2f703 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_085C_5v50.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_085C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_100C_5v50.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_100C_5v50.lib.json
index 196c392..1136e01 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_100C_5v50.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_100C_5v50.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_150C_5v50.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_150C_5v50.lib.json
index 7005766..c9ea6ff 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_150C_5v50.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_150C_5v50.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_4v40.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_4v40.lib.json
index 43abe76..0af7325 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_4v40.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_4v40.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_4v95.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_4v95.lib.json
index 61e44ab..b4eec95 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_4v95.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_4v95.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_5v50_ccsnoise.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_5v50_ccsnoise.lib.json
index 79fa826..941c2be 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_5v50_ccsnoise.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ff_n40C_5v50_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_1v65.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_1v65.lib.json
index ba16f14..fa7418f 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_1v65.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_1v95.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_1v95.lib.json
index 67b5437..9c2e061 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_1v95.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_3v00.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_3v00.lib.json
index 64a9bb3..e441d63 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_3v00.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_100C_3v00.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_150C_1v65.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_150C_1v65.lib.json
index aa600c7..fdb46ea 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_150C_1v65.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_150C_1v65.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v32.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v32.lib.json
index 99483a3..f0749f3 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v32.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v32.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v49.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v49.lib.json
index eacfd56..20c33d9 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v49.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v49.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v65_ccsnoise.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v65_ccsnoise.lib.json
index d735231..a829321 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v65_ccsnoise.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v65_ccsnoise.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v95.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v95.lib.json
index 274c99d..6c6568e 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v95.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__ss_n40C_1v95.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__tt_025C_3v30.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__tt_025C_3v30.lib.json
index 5d63121..ba7c417 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__tt_025C_3v30.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__tt_025C_3v30.lib.json
@@ -24,18 +24,22 @@
],
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1__tt_100C_3v30.lib.json b/cells/xor2/sky130_fd_sc_hvl__xor2_1__tt_100C_3v30.lib.json
index 2518bab..c8120b0 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1__tt_100C_3v30.lib.json
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1__tt_100C_3v30.lib.json
@@ -4,18 +4,22 @@
"cell_leakage_power": 0.0,
"pg_pin,VGND": {
"pg_type": "primary_ground",
+ "related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
- "pg_type": "pwell",
+ "pg_type": "nwell",
+ "physical_connection": "device_layer",
"voltage_name": "VNB"
},
"pg_pin,VPB": {
- "pg_type": "nwell",
+ "pg_type": "pwell",
+ "physical_connection": "device_layer",
"voltage_name": "VPB"
},
"pg_pin,VPWR": {
"pg_type": "primary_power",
+ "related_bias_pin": "VNB",
"voltage_name": "VPWR"
},
"pin,A": {
