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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_hvl

"High voltage" digital standard cells provided by the SkyWater foundry.

Mirrored from https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git
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  1. 4fd4f85 Fix JSON for muxes using udp_mux_4to2. by Tim 'mithro' Ansell · 1 year, 8 months ago branch-0.0.3 main
  2. fc47788 Fix JSON for muxes using udp_mux_4to2. by Tim 'mithro' Ansell · 1 year, 8 months ago branch-0.0.2
  3. c86542d Fix JSON for muxes using udp_mux_4to2. by Tim 'mithro' Ansell · 1 year, 8 months ago branch-0.0.1
  4. 4cecae5 lef: Fixing VNB/VPB properties in .magic.lef files. by Tim 'mithro' Ansell · 1 year, 8 months ago
  5. fe2ca20 lef: Fixing VNB/VPB properties in .magic.lef files. by Tim 'mithro' Ansell · 1 year, 8 months ago
  6. 0f5ece9 lef: Fixing VNB/VPB properties in .magic.lef files. by Tim 'mithro' Ansell · 1 year, 8 months ago
  7. 92e78fb verilog: Fixing power pins usage in non-powerpin mode. by Tim 'mithro' Ansell · 1 year, 8 months ago
  8. 52f30ef verilog: Fixing power pins usage in non-powerpin mode. by Tim 'mithro' Ansell · 1 year, 8 months ago
  9. 85e478c verilog: Fixing power pins usage in non-powerpin mode. by Tim 'mithro' Ansell · 1 year, 8 months ago
  10. 816a157 cdl: Fixing missing terminals. by Tim 'mithro' Ansell · 1 year, 8 months ago
  11. 95012fe cdl: Fixing missing terminals. by Tim 'mithro' Ansell · 1 year, 8 months ago
  12. 1bdde9b cdl: Fixing missing terminals. by Tim 'mithro' Ansell · 1 year, 8 months ago
  13. 38fa0f4 verilog: Fixing ordering of ports in primitives. by Tim 'mithro' Ansell · 1 year, 9 months ago
  14. 475761d verilog: Fixing ordering of ports in primitives. by Tim 'mithro' Ansell · 1 year, 9 months ago
  15. e16912f verilog: Fixing ordering of ports in primitives. by Tim 'mithro' Ansell · 1 year, 9 months ago
  16. 6dc6081 verilog: Fixing usage of cell reserved word. by Tim 'mithro' Ansell · 1 year, 9 months ago
  17. a94c816 verilog: Fixing usage of cell reserved word. by Tim 'mithro' Ansell · 1 year, 9 months ago
  18. c54a9af verilog: Fixing usage of cell reserved word. by Tim 'mithro' Ansell · 1 year, 9 months ago
  19. bf24011 verilog: Fixing include path. by Tim 'mithro' Ansell · 1 year, 9 months ago
  20. 916398a verilog: Fixing include path. by Tim 'mithro' Ansell · 1 year, 9 months ago