"High voltage" digital standard cells provided by the SkyWater foundry.

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  1. 4cecae5 lef: Fixing VNB/VPB properties in .magic.lef files. by Tim 'mithro' Ansell · 2 days ago branch-0.0.3 master
  2. fe2ca20 lef: Fixing VNB/VPB properties in .magic.lef files. by Tim 'mithro' Ansell · 2 days ago branch-0.0.2
  3. 0f5ece9 lef: Fixing VNB/VPB properties in .magic.lef files. by Tim 'mithro' Ansell · 2 days ago branch-0.0.1
  4. 92e78fb verilog: Fixing power pins usage in non-powerpin mode. by Tim 'mithro' Ansell · 2 days ago
  5. 52f30ef verilog: Fixing power pins usage in non-powerpin mode. by Tim 'mithro' Ansell · 2 days ago
  6. 85e478c verilog: Fixing power pins usage in non-powerpin mode. by Tim 'mithro' Ansell · 2 days ago
  7. 816a157 cdl: Fixing missing terminals. by Tim 'mithro' Ansell · 2 days ago
  8. 95012fe cdl: Fixing missing terminals. by Tim 'mithro' Ansell · 2 days ago
  9. 1bdde9b cdl: Fixing missing terminals. by Tim 'mithro' Ansell · 2 days ago
  10. 475761d verilog: Fixing ordering of ports in primitives. by Tim 'mithro' Ansell · 4 weeks ago
  11. e16912f verilog: Fixing ordering of ports in primitives. by Tim 'mithro' Ansell · 4 weeks ago
  12. a94c816 verilog: Fixing usage of cell reserved word. by Tim 'mithro' Ansell · 4 weeks ago
  13. c54a9af verilog: Fixing usage of cell reserved word. by Tim 'mithro' Ansell · 4 weeks ago
  14. 916398a verilog: Fixing include path. by Tim 'mithro' Ansell · 4 weeks ago
  15. f604d5b verilog: Fixing include path. by Tim 'mithro' Ansell · 4 weeks ago
  16. 115a236 Fixing the technology LEF file. by Tim 'mithro' Ansell · 4 weeks ago
  17. b957a11 Fixing the technology LEF file. by Tim 'mithro' Ansell · 4 weeks ago
  18. 38fa0f4 verilog: Fixing ordering of ports in primitives. by Tim 'mithro' Ansell · 4 weeks ago
  19. 6dc6081 verilog: Fixing usage of cell reserved word. by Tim 'mithro' Ansell · 4 weeks ago
  20. bf24011 verilog: Fixing include path. by Tim 'mithro' Ansell · 4 weeks ago