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foss-eda-tools
/
skywater-pdk
/
libs
/
sky130_fd_sc_hvl
"High voltage" digital standard cells provided by the SkyWater foundry.
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master
branch-0.0.1
branch-0.0.2
branch-0.0.3
new-spice
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v0.0.3
v0.0.2
v0.0.1
v0.0.0
4fd4f85
Fix JSON for muxes using udp_mux_4to2.
by Tim 'mithro' Ansell
· 3 months ago
branch-0.0.3
master
fc47788
Fix JSON for muxes using udp_mux_4to2.
by Tim 'mithro' Ansell
· 3 months ago
branch-0.0.2
c86542d
Fix JSON for muxes using udp_mux_4to2.
by Tim 'mithro' Ansell
· 3 months ago
branch-0.0.1
4cecae5
lef: Fixing VNB/VPB properties in .magic.lef files.
by Tim 'mithro' Ansell
· 3 months ago
fe2ca20
lef: Fixing VNB/VPB properties in .magic.lef files.
by Tim 'mithro' Ansell
· 3 months ago
0f5ece9
lef: Fixing VNB/VPB properties in .magic.lef files.
by Tim 'mithro' Ansell
· 3 months ago
92e78fb
verilog: Fixing power pins usage in non-powerpin mode.
by Tim 'mithro' Ansell
· 3 months ago
52f30ef
verilog: Fixing power pins usage in non-powerpin mode.
by Tim 'mithro' Ansell
· 3 months ago
85e478c
verilog: Fixing power pins usage in non-powerpin mode.
by Tim 'mithro' Ansell
· 3 months ago
816a157
cdl: Fixing missing terminals.
by Tim 'mithro' Ansell
· 3 months ago
95012fe
cdl: Fixing missing terminals.
by Tim 'mithro' Ansell
· 3 months ago
1bdde9b
cdl: Fixing missing terminals.
by Tim 'mithro' Ansell
· 3 months ago
475761d
verilog: Fixing ordering of ports in primitives.
by Tim 'mithro' Ansell
· 4 months ago
e16912f
verilog: Fixing ordering of ports in primitives.
by Tim 'mithro' Ansell
· 4 months ago
a94c816
verilog: Fixing usage of cell reserved word.
by Tim 'mithro' Ansell
· 4 months ago
c54a9af
verilog: Fixing usage of cell reserved word.
by Tim 'mithro' Ansell
· 4 months ago
916398a
verilog: Fixing include path.
by Tim 'mithro' Ansell
· 4 months ago
f604d5b
verilog: Fixing include path.
by Tim 'mithro' Ansell
· 4 months ago
115a236
Fixing the technology LEF file.
by Tim 'mithro' Ansell
· 4 months ago
b957a11
Fixing the technology LEF file.
by Tim 'mithro' Ansell
· 4 months ago
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