verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
tree: b8b9bff5a120de4d0be2aa1a1bab4b8d7a5f29d2
  1. .gitignore
  2. LICENSE
  3. README.rst
  4. cells/
  5. models/
  6. tech/
  7. timing/