)]}'
{
  "commit": "475761dadc1e366a3be3630a10b51dd467ab0128",
  "tree": "b8b9bff5a120de4d0be2aa1a1bab4b8d7a5f29d2",
  "parents": [
    "a94c8163a66304bd2b850537739392ad27ba388b",
    "e16912f6328429ac8ad9b88857be6ccd9291f698"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}