| commit | e16912f6328429ac8ad9b88857be6ccd9291f698 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 1c6cb8ae3e9d5f1825e68d29c2b144db175bf0da | |
| parent | c54a9afeeb0a1ed1805569e94e14d0eacd3e4580 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>