| commit | 38fa0f4f8ccd4e4a908fa2d833dd11f91f6e3ab3 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | abd3382f4a7be52e34b7035b432d58845baf8f4b | |
| parent | 6dc60815830e2a6c26a4974475a782f2f94571d8 [diff] | |
| parent | 475761dadc1e366a3be3630a10b51dd467ab0128 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>