)]}'
{
  "commit": "38fa0f4f8ccd4e4a908fa2d833dd11f91f6e3ab3",
  "tree": "abd3382f4a7be52e34b7035b432d58845baf8f4b",
  "parents": [
    "6dc60815830e2a6c26a4974475a782f2f94571d8",
    "475761dadc1e366a3be3630a10b51dd467ab0128"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}