| commit | 475761dadc1e366a3be3630a10b51dd467ab0128 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | b8b9bff5a120de4d0be2aa1a1bab4b8d7a5f29d2 | |
| parent | a94c8163a66304bd2b850537739392ad27ba388b [diff] | |
| parent | e16912f6328429ac8ad9b88857be6ccd9291f698 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>