precheck clean-up & mac timing constraints cleanup
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index ba62c85..57e93ac 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 97c7e2c..675a160 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/openlane/mac_wrapper/base.sdc b/openlane/mac_wrapper/base.sdc
index 25354a8..0a7529f 100644
--- a/openlane/mac_wrapper/base.sdc
+++ b/openlane/mac_wrapper/base.sdc
@@ -7,9 +7,9 @@
# Timing Constraints
###############################################################################
create_clock -name app_clk -period 10.0000 [get_ports {app_clk}]
-create_clock -name phy_tx_clk -period 10.0000 [get_ports {phy_tx_clk}]
-create_clock -name phy_rx_clk -period 10.0000 [get_ports {phy_rx_clk}]
-create_clock -name mdio_clk -period 10.0000 [get_ports {mdio_clk}]
+create_clock -name phy_tx_clk -period 40.0000 [get_ports {phy_tx_clk}]
+create_clock -name phy_rx_clk -period 40.0000 [get_ports {phy_rx_clk}]
+create_clock -name mdio_clk -period 100.0000 [get_ports {mdio_clk}]
set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.5000 [all_clocks]
@@ -58,10 +58,10 @@
########################################
# phy_rx_clk Clock Domain
########################################
-set_input_delay -max 6.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_crs}]
-set_input_delay -max 6.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rx_dv}]
-set_input_delay -max 6.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rx_er}]
-set_input_delay -max 6.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rxd[*]}]
+set_input_delay -max 20.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_crs}]
+set_input_delay -max 20.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rx_dv}]
+set_input_delay -max 20.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rx_er}]
+set_input_delay -max 20.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rxd[*]}]
set_input_delay -min -2.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_crs}]
set_input_delay -min -2.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rx_dv}]
@@ -73,9 +73,9 @@
# phy_tx_clk Clock Domain
########################################
-set_output_delay -max 6.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_en}]
-set_output_delay -max 6.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_er}]
-set_output_delay -max 6.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_txd[*]}]
+set_output_delay -max 20.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_en}]
+set_output_delay -max 20.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_er}]
+set_output_delay -max 20.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_txd[*]}]
set_output_delay -min -2.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_en}]
set_output_delay -min -2.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_er}]
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 4a4ef2c..8d15ccf 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -46,12 +46,14 @@
$::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/glbl/src/glbl_cfg.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/glbl/src/glbl_cfg.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/clkgen.sv \
"
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/ ]
+
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SDC_FILE) "$::env(DESIGN_DIR)/base.sdc"
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index f36d7e8..34e18d9 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -64,6 +64,7 @@
$::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2_core.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \
"
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/ ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
diff --git a/sdc/caravel.sdc b/sdc/caravel.sdc
index ad4ea45..4371121 100644
--- a/sdc/caravel.sdc
+++ b/sdc/caravel.sdc
@@ -15,10 +15,15 @@
create_clock -name wbs_clk_i -period 10.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
create_clock -name lbist_clk -period 10.0000 [get_pins {mprj/u_wb_host/clkbuf_0_u_lbist.lbist_clk/X}]
create_clock -name uart_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+create_clock -name mdio_refclk -period 10.0000 [get_pins {mprj/u_pinmux/u_clkgen.u_mdio_ref_mux.u_mux_l10/X}]
# Mac Tx and RX clock is 25Mhx-40ns
-create_clock -name mac_tx_clk -period 40.0000 [get_ports {mprj_io[5]}]
-create_clock -name mac_rx_clk -period 40.0000 [get_ports {mprj_io[12]}]
+create_clock -name pad_mac_tx_clk -period 40.0000 [get_ports {mprj_io[5]}]
+create_clock -name pad_mac_rx_clk -period 40.0000 [get_ports {mprj_io[12]}]
+create_clock -name mdio_clk -period 100.0000 [get_pins {mprj/u_pinmux/u_clkgen.u_mdio_clkbuf.u_buf/X}]
+
+create_generated_clock -name mac_tx_clk -add -source [get_ports {mprj_io[5]}] -master_clock [get_clocks pad_mac_tx_clk] -divide_by 1 -comment {mac tx clock} [get_pins {mprj/u_pinmux/mac_tx_clk}]
+create_generated_clock -name mac_rx_clk -add -source [get_ports {mprj_io[12]}] -master_clock [get_clocks pad_mac_rx_clk] -divide_by 1 -comment {mac rx clock} [get_pins {mprj/u_pinmux/mac_rx_clk}]
set_clock_uncertainty -setup 0.2500 [all_clocks]
set_clock_uncertainty -hold 0.1000 [all_clocks]
@@ -30,8 +35,10 @@
-group [get_clocks {wbs_clk_i}]\
-group [get_clocks {uart_clk}]\
-group [get_clocks {lbist_clk}]\
- -group [get_clocks {mac_tx_clk}]\
- -group [get_clocks {mac_rx_clk}]\
+ -group [get_clocks {mac_tx_clk pad_mac_tx_clk}]\
+ -group [get_clocks {mac_rx_clk pad_mac_rx_clk}]\
+ -group [get_clocks {mdio_refclk}]\
+ -group [get_clocks {mdio_clk}]\
-group [get_clocks {hk_serial_clk}]\
-group [get_clocks {hk_serial_load}]\
-group [get_clocks {hkspi_clk}]
@@ -99,6 +106,48 @@
# set_output_delay $output_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}]
+########################################
+# phy_rx_clk Clock Domain
+########################################
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[13]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[13]}]
+
+
+
+########################################
+# phy_tx_clk Clock Domain
+########################################
+
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[6]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[7]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[8]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[9]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[10]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[11]}]
+
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[6]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[7]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[8]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[9]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[10]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[11]}]
+
+
+
+
set_max_fanout 12 [current_design]
# synthesis max fanout should be less than 12 (7 maybe)
diff --git a/sdc/mac_wrapper.sdc b/sdc/mac_wrapper.sdc
index 00de317..1019eef 100644
--- a/sdc/mac_wrapper.sdc
+++ b/sdc/mac_wrapper.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sun Dec 25 11:03:09 2022
+# Sat Dec 31 08:01:52 2022
###############################################################################
current_design mac_wrapper
###############################################################################
@@ -11,17 +11,17 @@
set_clock_uncertainty -setup 0.5000 app_clk
set_clock_uncertainty -hold 0.2500 app_clk
set_propagated_clock [get_clocks {app_clk}]
-create_clock -name phy_tx_clk -period 10.0000 [get_ports {phy_tx_clk}]
+create_clock -name phy_tx_clk -period 40.0000 [get_ports {phy_tx_clk}]
set_clock_transition 0.1500 [get_clocks {phy_tx_clk}]
set_clock_uncertainty -setup 0.5000 phy_tx_clk
set_clock_uncertainty -hold 0.2500 phy_tx_clk
set_propagated_clock [get_clocks {phy_tx_clk}]
-create_clock -name phy_rx_clk -period 10.0000 [get_ports {phy_rx_clk}]
+create_clock -name phy_rx_clk -period 40.0000 [get_ports {phy_rx_clk}]
set_clock_transition 0.1500 [get_clocks {phy_rx_clk}]
set_clock_uncertainty -setup 0.5000 phy_rx_clk
set_clock_uncertainty -hold 0.2500 phy_rx_clk
set_propagated_clock [get_clocks {phy_rx_clk}]
-create_clock -name mdio_clk -period 10.0000 [get_ports {mdio_clk}]
+create_clock -name mdio_clk -period 100.0000 [get_ports {mdio_clk}]
set_clock_transition 0.1500 [get_clocks {mdio_clk}]
set_clock_uncertainty -setup 0.5000 mdio_clk
set_clock_uncertainty -hold 0.2500 mdio_clk
@@ -42,27 +42,27 @@
set_input_delay -2.0000 -clock [get_clocks {mdio_clk}] -min -add_delay [get_ports {mdio_in}]
set_input_delay 6.0000 -clock [get_clocks {mdio_clk}] -max -add_delay [get_ports {mdio_in}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_crs}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_crs}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_crs}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rx_dv}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rx_dv}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rx_dv}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rx_er}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rx_er}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rx_er}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rxd[0]}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[0]}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[0]}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rxd[1]}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[1]}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[1]}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rxd[2]}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[2]}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[2]}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rxd[3]}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[3]}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[3]}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rxd[4]}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[4]}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[4]}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rxd[5]}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[5]}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[5]}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rxd[6]}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[6]}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[6]}]
set_input_delay -2.0000 -clock [get_clocks {phy_rx_clk}] -min -add_delay [get_ports {phy_rxd[7]}]
-set_input_delay 6.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[7]}]
+set_input_delay 20.0000 -clock [get_clocks {phy_rx_clk}] -max -add_delay [get_ports {phy_rxd[7]}]
set_input_delay 1.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {wbm_grx_ack_i}]
set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {wbm_grx_ack_i}]
set_input_delay 1.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {wbm_grx_dat_i[0]}]
@@ -344,25 +344,25 @@
set_output_delay -2.0000 -clock [get_clocks {mdio_clk}] -min -add_delay [get_ports {mdio_out_en}]
set_output_delay 6.0000 -clock [get_clocks {mdio_clk}] -max -add_delay [get_ports {mdio_out_en}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_tx_en}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_tx_en}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_tx_en}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_tx_er}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_tx_er}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_tx_er}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_txd[0]}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[0]}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[0]}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_txd[1]}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[1]}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[1]}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_txd[2]}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[2]}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[2]}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_txd[3]}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[3]}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[3]}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_txd[4]}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[4]}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[4]}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_txd[5]}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[5]}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[5]}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_txd[6]}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[6]}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[6]}]
set_output_delay -2.0000 -clock [get_clocks {phy_tx_clk}] -min -add_delay [get_ports {phy_txd[7]}]
-set_output_delay 6.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[7]}]
+set_output_delay 20.0000 -clock [get_clocks {phy_tx_clk}] -max -add_delay [get_ports {phy_txd[7]}]
set_output_delay 1.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {wbm_grx_adr_o[0]}]
set_output_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {wbm_grx_adr_o[0]}]
set_output_delay 1.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {wbm_grx_adr_o[10]}]
diff --git a/sdc/pinmux_top.sdc b/sdc/pinmux_top.sdc
index 496da89..f08cfc5 100644
--- a/sdc/pinmux_top.sdc
+++ b/sdc/pinmux_top.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sun Dec 25 14:12:46 2022
+# Sat Dec 31 03:58:51 2022
###############################################################################
current_design pinmux_top
###############################################################################
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index 7b98d7b..a371c21 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Dec 31 03:25:00 2022
+# Sat Dec 31 10:51:33 2022
###############################################################################
current_design user_project_wrapper
###############################################################################
diff --git a/sdc/wb_host.sdc b/sdc/wb_host.sdc
index 2186c75..30fc1b4 100644
--- a/sdc/wb_host.sdc
+++ b/sdc/wb_host.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Dec 24 13:52:44 2022
+# Sat Dec 31 06:48:36 2022
###############################################################################
current_design wb_host
###############################################################################
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index c0a36db..f338234 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -56,6 +56,10 @@
read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v
read_verilog $::env(USER_ROOT)/verilog/gl/mbist_wrapper.v
read_verilog $::env(USER_ROOT)/verilog/gl/mac_wrapper.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/bus_rep_north.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/bus_rep_south.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/bus_rep_east.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/bus_rep_west.v
read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v
@@ -115,6 +119,10 @@
read_spef -path mprj/u_mbist0 $::env(USER_ROOT)/signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef
read_spef -path mprj/u_mbist1 $::env(USER_ROOT)/signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef
read_spef -path mprj/u_pinmux $::env(USER_ROOT)/signoff/pinmux_top/openlane-signoff/spef/pinmux_top.min.spef
+ read_spef -path mprj/u_rp_north $::env(USER_ROOT)/signoff/bus_rep_north/openlane-signoff/spef/bus_rep_north.nom.spef
+ read_spef -path mprj/u_rp_south $::env(USER_ROOT)/signoff/bus_rep_south/openlane-signoff/spef/bus_rep_south.nom.spef
+ read_spef -path mprj/u_rp_east $::env(USER_ROOT)/signoff/bus_rep_east/openlane-signoff/spef/bus_rep_east.nom.spef
+ read_spef -path mprj/u_rp_west $::env(USER_ROOT)/signoff/bus_rep_west/openlane-signoff/spef/bus_rep_west.nom.spef
read_spef -path mprj $::env(USER_ROOT)/signoff/user_project_wrapper/openlane-signoff/spef/user_project_wrapper.min.spef
read_spef $::env(CARAVEL_ROOT)/signoff/caravel/openlane-signoff/spef/caravel.min.spef
@@ -181,4 +189,35 @@
#set sram_oport [concat $sram_oport [get_pins {soc/core/sky130_sram_2kbyte_1rw1r_32x512_8/dout1[*]}]]
### Caravel SRAM Path ######################################
+ #MAC RX Path
+ report_checks -path_group mac_rx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[19]}] -through [get_pins mprj/u_mac_wrap/phy_rxd[3]] > mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[18]}] -through [get_pins mprj/u_mac_wrap/phy_rxd[2]] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[17]}] -through [get_pins mprj/u_mac_wrap/phy_rxd[1]] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[16]}] -through [get_pins mprj/u_mac_wrap/phy_rxd[0]] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[15]}] -through [get_pins mprj/u_mac_wrap/phy_crs] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[14]}] -through [get_pins mprj/u_mac_wrap/phy_rx_er] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[13]}] -through [get_pins mprj/u_mac_wrap/phy_rx_dv] >> mac.vio.rpt
+
+ report_checks -path_group mac_rx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[19]}] -through [get_pins mprj/u_mac_wrap/phy_rxd[3]] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[18]}] -through [get_pins mprj/u_mac_wrap/phy_rxd[2]] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[17]}] -through [get_pins mprj/u_mac_wrap/phy_rxd[1]] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[16]}] -through [get_pins mprj/u_mac_wrap/phy_rxd[0]] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[15]}] -through [get_pins mprj/u_mac_wrap/phy_crs] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[14]}] -through [get_pins mprj/u_mac_wrap/phy_rx_er] >> mac.vio.rpt
+ report_checks -path_group mac_rx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -from [get_ports {mprj_io[13]}] -through [get_pins mprj/u_mac_wrap/phy_rx_dv] >> mac.vio.rpt
+
+ #MAC TX Path
+ report_checks -path_group pad_mac_tx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[6]}] -through [get_pins mprj/u_mac_wrap/phy_tx_en] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[7]}] -through [get_pins mprj/u_mac_wrap/phy_tx_er] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[8]}] -through [get_pins mprj/u_mac_wrap/phy_txd[0]] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[9]}] -through [get_pins mprj/u_mac_wrap/phy_txd[1]] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[10]}] -through [get_pins mprj/u_mac_wrap/phy_txd[2]] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[11]}] -through [get_pins mprj/u_mac_wrap/phy_txd[3]] >> mac.vio.rpt
+
+ report_checks -path_group pad_mac_tx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[6]}] -through [get_pins mprj/u_mac_wrap/phy_tx_en] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[7]}] -through [get_pins mprj/u_mac_wrap/phy_tx_er] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[8]}] -through [get_pins mprj/u_mac_wrap/phy_txd[0]] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[9]}] -through [get_pins mprj/u_mac_wrap/phy_txd[1]] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[10]}] -through [get_pins mprj/u_mac_wrap/phy_txd[2]] >> mac.vio.rpt
+ report_checks -path_group pad_mac_tx_clk -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -to [get_ports {mprj_io[11]}] -through [get_pins mprj/u_mac_wrap/phy_txd[3]] >> mac.vio.rpt
diff --git a/sta/slew.cap.fanout.vio.rpt b/sta/slew.cap.fanout.vio.rpt
index e58f107..f3d4394 100644
--- a/sta/slew.cap.fanout.vio.rpt
+++ b/sta/slew.cap.fanout.vio.rpt
@@ -249,8 +249,6 @@
soc/core.RAM128/BLOCK[1].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.37 -0.85 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[5]_D/DIODE 1.50 2.35 -0.85 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[5]/D 1.50 2.35 -0.85 (VIOLATED)
-mprj/u_mbist1/ANTENNA_hold89_A/DIODE 1.50 2.34 -0.84 (VIOLATED)
-mprj/u_mbist1/hold89/A 1.50 2.34 -0.84 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 2.36 -0.84 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 2.36 -0.84 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.36 -0.84 (VIOLATED)
@@ -384,396 +382,33 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.32 -0.80 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.32 -0.80 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.32 -0.80 (VIOLATED)
-mprj/u_wb_host/_6349_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6349__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6287__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6287_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6286_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6286__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6288_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6288__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6423_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6423__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6424_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6424__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6425_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6425__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6422_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6422__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6523_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6523__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5595_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6401_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5595__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6402_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6402__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6524_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6524__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6401__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6525_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6525__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6426_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6358_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6358__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5642_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5607_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6259_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6426__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6372_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6372__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5642__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6359_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6362_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6362__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6359__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6464_/CLK 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6464__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5607__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6465_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5602_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5602__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5548_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5548__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6465__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6311__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6345_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6345__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6290__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6310__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6291__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6292__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6292_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6522__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6314__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6310_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6318__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6343_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6343__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5553_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6311_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6290_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6522_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6296_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6313_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6315__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5553__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6350_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6350__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6294_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6427_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6427__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6312_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6317_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6291_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6296__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6316__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6313__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6319__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6294__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6312__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6295__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5902_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6298_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6293_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6297_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6293__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6317__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6439__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6439_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6434__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6434_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6521_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6521__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5902__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6298__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6321_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6368_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6368__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5550__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5550_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6259__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6347_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6347__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5894_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5894__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6301_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6297__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6300_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5901_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6301__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6300__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5901__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6318_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6319_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6322_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6321__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6323_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6314_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6325_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6315_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6295_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6324_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6323__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6316_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6327__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6320__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6302_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6320_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6299__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6322__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6324__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5900_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5549_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5547_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6299_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5549__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6346_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6346__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6344_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6303_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6344__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6303__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5547__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5603__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5603_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6348__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6348_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5551__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5551_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5605__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5605_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5900__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6360__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6302__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5552_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5606_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5552__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6361__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5606__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6361_/CLK 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/_6360_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6397_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6397__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6373__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6373_/CLK 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6421__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6421_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6437_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6377__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6420_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6420__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/_6306_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6305_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6325__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6304_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6305__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6377_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6309_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6304__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6308_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6309__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6405_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6380_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6380__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6308__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6405__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6394_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6333__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6332_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6404_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6333_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6330__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6307_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6329__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6438_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6329_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6404__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6331__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6394__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6383_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6383__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6306__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6374__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6374_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6326__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6398__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6398_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6307__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6328__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6433_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6387_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6387__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5899__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5899_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6428__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6428_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5896_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6429__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5896__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6429_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6433__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5888_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5891__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5891_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6449__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5888__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6449_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5889_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5889__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6430__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6435_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6435__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6385_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6447__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6447_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6463__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6430_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6431_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6390__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6390_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6431__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6385__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6384__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6384_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6379_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6379__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5890__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6391__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6391_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6438__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5890_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6389_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6382_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6381_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6382__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6376__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6376_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6328_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6463_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6432_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6432__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6436_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6436__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6450_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6450__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5895_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5895__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6378_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6378__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5898__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6437__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5898_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5903_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5903__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6375_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6400_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5609_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6400__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6352_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6352__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6395__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6399__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6395_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6399_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6388__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5892_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5892__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5599_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5599__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6392__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5897__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6388_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6392_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6375__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6326_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6327_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6381__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/ANTENNA_BANK128[1].RAM128.BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[1].Do_FF[3]_D/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[1].Do_FF[3]/D 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6389__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5897_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6386_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6393_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6330_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5893_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6393__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6335__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5893__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6370__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6386__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6370_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6335_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6331_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6396_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6396__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6334__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6369__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6334_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5640__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5640_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5641__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5641_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6332__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6403_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6369_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6336_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6403__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/_6339_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6338_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5598_/CLK 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/ANTENNA_BANK128[1].RAM128.BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[3]_D/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[3]/D 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/_5594_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6371__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6336__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/_6337_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6371_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6340_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5598__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5594__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6355__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6355_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_5613_/CLK 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5609__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/_6356_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5613__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6356__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6261__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6340__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5600__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6338__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6339__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/_5600_/CLK 1.50 2.29 -0.79 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6337__CLK/DIODE 1.50 2.29 -0.79 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.31 -0.79 (VIOLATED)
-mprj/u_wb_host/_6353_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6261_/CLK 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[1]_D/DIODE 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[1]/D 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6353__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5596__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6341_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5596_/CLK 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
@@ -781,12 +416,8 @@
soc/core.RAM128/BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.BYTE[2].FLOATBUF0[20].cell/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5633__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/_5597_/CLK 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6341__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5633_/CLK 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
@@ -797,7 +428,6 @@
soc/core.RAM128/BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5597__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
@@ -807,243 +437,32 @@
soc/core.RAM128/BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/_5635_/CLK 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5635__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/_6260_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6260__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6289_/CLK 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/_6491_/CLK 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/_6357_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6357__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6351_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6351__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5621_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5608_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5612_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5619__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5619_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5612__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/_5614_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5614__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5611_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5634__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6354_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6354__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5626_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5626__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5628_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5628__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5634_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6504_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6491__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6504__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6505_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6289__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6505__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/_6511_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6342_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6514_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6517_/CLK 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/_6499_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6499__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6497_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6503_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6503__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6502_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6497__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6492_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6495_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6502__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6507_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6501_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6495__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6507__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6500_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6501__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6508_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6511__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6517__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6514__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6500__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6492__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6489_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6490__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6506__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6509__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6493_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6488__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6496_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6493__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6342__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6488_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6490_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6512_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6506_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6515_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6513__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6512__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6509_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6513_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6508__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6471_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6472__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6476__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6474_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6473__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6472_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6473_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6476_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6479_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6479__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6480__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6480_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6419__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6419_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6519_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5629__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5629_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5636_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5636__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5601__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_5601_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6519__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6365_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6365__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6516_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6448__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6448_/CLK 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6363__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/_6363_/CLK 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6516__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6515__CLK/DIODE 1.50 2.28 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.30 -0.78 (VIOLATED)
-mprj/u_wb_host/_6518_/CLK 1.50 2.27 -0.77 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.29 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6469__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6469_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6475_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6366_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6467_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6367__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6367_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6366__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6518__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6510__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6510_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6494_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6496__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6494__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6498__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5618_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6498_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5616__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5616_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5623_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5588_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6489__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5588__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5639_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6446__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6446_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6443__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5623__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.29 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5589__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5589_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5610__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5617_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5617__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5618__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5590_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5625_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5625__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5590__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6443_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5639__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6445_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5632__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.29 -0.77 (VIOLATED)
-mprj/u_wb_host/_5632_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5591__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5611__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5627__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5591_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5627_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5592__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5608__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5621__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5593_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5593__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5592_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5615_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5615__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5620_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5620__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5610_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5587__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5587_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5622_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5622__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5638__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5638_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5631__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5631_/CLK 1.50 2.27 -0.77 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.29 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5624__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5624_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5630_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5630__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5604_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5604__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6364__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__5637__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_5637_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6364_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6475__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6520_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6520__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6445__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6466_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6466__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6440__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6441__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6440_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6441_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6442__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6442_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6471__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6474__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6470__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6470_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6468_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6468__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/_6444_/CLK 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6444__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/ANTENNA__6467__CLK/DIODE 1.50 2.27 -0.77 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[0].RAM32.Do0_REG.OUTREG_BYTE[1].Do_FF[4]_D/DIODE 1.50 2.27 -0.77 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.Do0_REG.OUTREG_BYTE[1].Do_FF[4]/D 1.50 2.27 -0.77 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.29 -0.77 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.29 -0.77 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.29 -0.77 (VIOLATED)
-mprj/u_mbist0/ANTENNA_hold89_A/DIODE 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_mbist0/hold89/A 1.50 2.27 -0.77 (VIOLATED)
-mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X 1.51 2.27 -0.77 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 2.29 -0.77 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 2.29 -0.77 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 2.28 -0.76 (VIOLATED)
@@ -5279,7 +4698,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/_4057_/Y 1.49 2.08 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
@@ -5429,95 +4847,21 @@
soc/core.RAM256/ANTENNA_BANK128[0].RAM128.BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[1].Do_FF[1]_D/DIODE 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[1].Do_FF[1]/D 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/_4084_/A 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4084__A/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4082__A/DIODE 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/_4082_/A 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4334_/B 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4334__B/DIODE 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/ANTENNA_BANK128[0].RAM128.BLOCK[0].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[5]_D/DIODE 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[5]/D 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4390_/A2 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4386__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4063__A/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4390__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4386_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4362__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4063_/A 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4394_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4362_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4394__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4370_/A2 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4370__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4374_/A2 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4374__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4353__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4353_/A2 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.BYTE[2].FLOATBUF0[22].__cell__/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/_4366_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4366__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4387__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/_4387_/A2 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
-mprj/u_wb_host/_4352_/A 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4352__A/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4383_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4391__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4391_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4383__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4402__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4398_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4414__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4414_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4398__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4382__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4382_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4378_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4410_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4378__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4358_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4410__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4367__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4367_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4395_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4354__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4354_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4358__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4359_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4395__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4406__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4402_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4371__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4406_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4371_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4359__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4375_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4375__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4363__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4363_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4399_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4379__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4379_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4403_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4403__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4415__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4399__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4407_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4415_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4407__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/_4411_/A2 1.50 2.08 -0.58 (VIOLATED)
-mprj/u_wb_host/ANTENNA__4411__A2/DIODE 1.50 2.08 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.10 -0.58 (VIOLATED)
@@ -5835,7 +5179,6 @@
soc/core.RAM128/BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.09 -0.57 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 2.09 -0.57 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 2.09 -0.57 (VIOLATED)
-mprj/u_sram0_2kb/addr0[4] 0.04 0.61 -0.57 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 2.09 -0.57 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 2.09 -0.57 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 2.09 -0.57 (VIOLATED)
@@ -6799,7 +6142,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
-mprj/u_sram0_2kb/addr0[8] 0.04 0.58 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
@@ -6985,7 +6327,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
-mprj/u_sram1_2kb/addr0[7] 0.04 0.58 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.06 -0.54 (VIOLATED)
@@ -7135,7 +6476,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
-mprj/u_sram0_2kb/addr0[7] 0.04 0.57 -0.53 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
@@ -7197,10 +6537,8 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[2]/D 1.50 2.03 -0.53 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
-mprj/u_wb_host/output135/X 1.51 2.04 -0.53 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
-mprj/u_sram2_2kb/addr0[8] 0.04 0.57 -0.53 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[4]/D 1.50 2.03 -0.53 (VIOLATED)
soc/core.RAM256/ANTENNA_BANK128[0].RAM128.BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[4]_D/DIODE 1.50 2.03 -0.53 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 2.05 -0.53 (VIOLATED)
@@ -7353,7 +6691,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
-mprj/u_sram0_2kb/addr0[3] 0.04 0.56 -0.52 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
@@ -7503,7 +6840,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
-mprj/u_sram2_2kb/addr0[5] 0.04 0.56 -0.52 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF0[10].cell/Z 1.52 2.04 -0.52 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 2.04 -0.52 (VIOLATED)
@@ -7694,7 +7030,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
-mprj/u_sram0_2kb/addr0[5] 0.04 0.55 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
@@ -7729,7 +7064,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
-mprj/u_sram6_2kb/addr0[6] 0.04 0.55 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
@@ -7744,7 +7078,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
-mprj/u_sram7_2kb/addr0[8] 0.04 0.55 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
@@ -7774,7 +7107,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
-mprj/u_sram4_2kb/addr0[2] 0.04 0.55 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
@@ -7795,7 +7127,6 @@
soc/core.RAM256/ANTENNA_BANK128[0].RAM128.BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[0]_D/DIODE 1.50 2.01 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[0]/D 1.50 2.01 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
-mprj/u_sram7_2kb/addr0[5] 0.04 0.55 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.03 -0.51 (VIOLATED)
@@ -7888,7 +7219,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
-mprj/u_sram6_2kb/addr0[8] 0.04 0.54 -0.50 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
@@ -7961,7 +7291,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
-mprj/u_sram0_2kb/addr0[6] 0.04 0.54 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
@@ -8052,9 +7381,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
-mprj/u_sram7_2kb/addr0[7] 0.04 0.54 -0.50 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
-mprj/u_sram0_2kb/addr0[2] 0.04 0.54 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
@@ -8096,7 +7423,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
-mprj/u_sram1_2kb/addr0[8] 0.04 0.54 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.02 -0.50 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
@@ -8138,7 +7464,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
-mprj/u_sram6_2kb/addr0[4] 0.04 0.53 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
@@ -8212,7 +7537,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
-mprj/u_sram1_2kb/addr0[2] 0.04 0.53 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
@@ -8281,6 +7605,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
+mprj/u_sram2_2kb/addr0[8] 0.04 0.53 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 2.01 -0.49 (VIOLATED)
soc/core.RAM256/ANTENNA_BANK128[0].RAM128.BLOCK[0].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[0]_D/DIODE 1.50 1.99 -0.49 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[0]/D 1.50 1.99 -0.49 (VIOLATED)
@@ -8457,7 +7782,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
-mprj/u_sram4_2kb/addr0[4] 0.04 0.52 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
@@ -8486,7 +7810,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
-mprj/u_sram5_2kb/addr0[8] 0.04 0.52 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
@@ -8507,7 +7830,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
-mprj/u_sram4_2kb/addr0[7] 0.04 0.52 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
@@ -8534,7 +7856,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF0[8].cell/Z 1.52 2.00 -0.48 (VIOLATED)
-mprj/u_sram2_2kb/addr0[4] 0.04 0.52 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[1]/D 1.50 1.98 -0.48 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[1]_D/DIODE 1.50 1.98 -0.48 (VIOLATED)
@@ -8553,6 +7874,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
+mprj/u_sram0_2kb/addr0[3] 0.04 0.52 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
@@ -8585,7 +7907,6 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
-mprj/u_sram5_2kb/addr0[4] 0.04 0.52 -0.48 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
@@ -8680,7 +8001,6 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
-mprj/u_sram4_2kb/addr0[8] 0.04 0.52 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
@@ -8691,7 +8011,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
-mprj/u_sram4_2kb/addr0[6] 0.04 0.52 -0.48 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 2.00 -0.48 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[3]_D/DIODE 1.50 1.98 -0.48 (VIOLATED)
@@ -8714,6 +8033,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[5]/D 1.50 1.97 -0.47 (VIOLATED)
soc/core.RAM256/ANTENNA_BANK128[0].RAM128.BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[5]_D/DIODE 1.50 1.97 -0.47 (VIOLATED)
+mprj/u_sram2_2kb/addr0[7] 0.04 0.51 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
@@ -8819,7 +8139,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
-mprj/u_sram6_2kb/addr0[7] 0.04 0.51 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
@@ -8854,9 +8173,12 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
+mprj/u_sram0_2kb/addr0[8] 0.04 0.51 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
+mprj/u_sram4_2kb/addr0[6] 0.04 0.51 -0.47 (VIOLATED)
+mprj/u_sram2_2kb/addr0[6] 0.04 0.51 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
@@ -8889,7 +8211,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
-mprj/u_sram1_2kb/addr0[3] 0.04 0.51 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
@@ -8912,14 +8233,13 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
-mprj/u_sram3_2kb/addr0[5] 0.04 0.51 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
+mprj/u_sram6_2kb/addr0[7] 0.04 0.51 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
-mprj/u_sram6_2kb/addr0[5] 0.04 0.51 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.99 -0.47 (VIOLATED)
@@ -9014,12 +8334,12 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
-mprj/u_sram3_2kb/addr0[2] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
+mprj/u_sram4_2kb/addr0[7] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
@@ -9074,9 +8394,11 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
+mprj/u_sram2_2kb/addr0[5] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
+mprj/u_sram4_2kb/addr0[8] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
@@ -9135,6 +8457,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
+mprj/u_sram4_2kb/addr0[4] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
@@ -9146,7 +8469,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
-mprj/u_sram2_2kb/addr0[7] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
@@ -9331,7 +8653,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
-mprj/u_sram3_2kb/addr0[7] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
@@ -9343,12 +8664,14 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
+mprj/u_sram0_2kb/addr0[5] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.BYTE[2].FLOATBUF0[19].cell/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
+mprj/u_sram6_2kb/addr0[3] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
@@ -9399,6 +8722,7 @@
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
+mprj/u_sram6_2kb/addr0[5] 0.04 0.50 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.98 -0.46 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
@@ -9406,7 +8730,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
-mprj/u_sram3_2kb/addr0[4] 0.04 0.49 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
@@ -9460,7 +8783,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
-mprj/u_sram7_2kb/addr0[3] 0.04 0.49 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
@@ -9501,7 +8823,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[2].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
-mprj/u_sram3_2kb/addr0[6] 0.04 0.49 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
@@ -9579,7 +8900,6 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
-mprj/u_sram3_2kb/addr0[3] 0.04 0.49 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[1].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
@@ -9639,7 +8959,6 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
-mprj/u_sram7_2kb/addr0[6] 0.04 0.49 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
@@ -9653,6 +8972,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
+mprj/u_sram0_2kb/addr0[7] 0.04 0.49 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
@@ -9698,7 +9018,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
-mprj/u_sram7_2kb/addr0[2] 0.04 0.49 -0.45 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.97 -0.45 (VIOLATED)
@@ -9776,6 +9095,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
+mprj/u_sram6_2kb/addr0[8] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -9816,6 +9136,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
+mprj/u_sram2_2kb/addr0[3] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -9823,7 +9144,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
-mprj/u_sram6_2kb/addr0[2] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -9871,7 +9191,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF0[16].cell/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
-mprj/u_sram3_2kb/addr0[8] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -9887,6 +9206,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
+mprj/u_sram4_2kb/addr0[2] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -9898,6 +9218,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
+mprj/u_sram4_2kb/addr0[3] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -9945,6 +9266,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
+mprj/u_sram7_2kb/addr0[5] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -10006,7 +9328,6 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
-mprj/u_sram2_2kb/addr0[2] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.BYTE[2].FLOATBUF0[19].cell/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -10024,7 +9345,10 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
+mprj/u_mbist1/ANTENNA_hold45_A/DIODE 1.50 1.94 -0.44 (VIOLATED)
+mprj/u_mbist1/hold45/A 1.50 1.94 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
+mprj/u_sram5_2kb/addr0[3] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -10068,7 +9392,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
-mprj/u_sram2_2kb/addr0[6] 0.04 0.48 -0.44 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.96 -0.44 (VIOLATED)
@@ -10079,7 +9402,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_sram1_2kb/addr0[5] 0.04 0.47 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
@@ -10108,35 +9430,15 @@
soc/core.RAM256/ANTENNA_BANK128[1].RAM128.BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[1]_D/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF0[19].cell/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2914_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2914__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2926__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_2917_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_2926_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3077__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2917__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2998__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_3077_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_3075_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3075__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3004__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_3004_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_3007_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.BYTE[1].FLOATBUF0[8].__cell__/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3007__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_2980_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.BYTE[2].FLOATBUF0[20].__cell__/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2980__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2998_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_3001_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3001__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
@@ -10145,23 +9447,13 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2995_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2995__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_2929_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2929__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3079__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_3079_/S0 1.50 1.93 -0.43 (VIOLATED)
+mprj/u_sram0_2kb/addr0[2] 0.04 0.47 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2941__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_2941_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_3081_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2983__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_2983_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
@@ -10176,41 +9468,25 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[7]/D 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[4]_D/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[4]/D 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3081__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2950_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2950__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.BYTE[0].FLOATBUF0[0].__cell__/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_3035_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3035__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2953__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_2953_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2935_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2935__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2932_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2932__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2956__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_2956_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2944_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2944__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2947_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.BYTE[2].FLOATBUF0[21].cell/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
@@ -10218,8 +9494,9 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2947__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
+mprj/u_sram2_2kb/addr0[2] 0.04 0.47 -0.43 (VIOLATED)
+mprj/u_sram3_2kb/addr0[5] 0.04 0.47 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/ANTENNA_BANK128[1].RAM128.BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[4]_D/DIODE 1.50 1.93 -0.43 (VIOLATED)
@@ -10242,19 +9519,13 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2962__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2962_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/_2959_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2959__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2938_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2938__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
@@ -10264,11 +9535,10 @@
soc/core.RAM128/ANTENNA_BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[1]_D/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[1]/D 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_2965_/S0 1.50 1.93 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2965__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
+mprj/u_sram6_2kb/addr0[6] 0.04 0.47 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
@@ -10282,71 +9552,48 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_3039_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_3047_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3047__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/_3051_/S0 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3039__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3051__S0/DIODE 1.50 1.93 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.95 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.94 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.94 -0.43 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3029_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3029__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_2992_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2992__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_sram5_2kb/addr0[5] 0.04 0.46 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3033__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3033_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3037_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3037__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3049_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3049__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2974__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_2974_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_2920_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2920__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3043__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3043_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10354,7 +9601,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_sram5_2kb/addr0[2] 0.04 0.46 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10375,7 +9621,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_2977_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10385,7 +9630,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2977__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10407,6 +9651,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
+mprj/u_sram7_2kb/addr0[3] 0.04 0.46 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10433,6 +9678,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF0[16].cell/Z 1.52 1.94 -0.42 (VIOLATED)
+mprj/u_sram0_2kb/addr0[6] 0.04 0.46 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.BYTE[2].FLOATBUF0[23].__cell__/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[2]/D 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/ANTENNA_BANK128[0].RAM128.BLOCK[0].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[2]_D/DIODE 1.50 1.92 -0.42 (VIOLATED)
@@ -10445,7 +9691,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3057_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10460,7 +9705,6 @@
soc/core.RAM128/ANTENNA_BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[1].Do_FF[6]_D/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[1].Do_FF[6]/D 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3057__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10492,7 +9736,6 @@
soc/core.RAM256/ANTENNA_BANK128[1].RAM128.BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[4]_D/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3053_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10514,18 +9757,16 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
+mprj/u_sram7_2kb/addr0[6] 0.04 0.46 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2923__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_2923_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3053__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10553,7 +9794,6 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3045__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10569,7 +9809,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3045_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10582,7 +9821,6 @@
soc/core.RAM128/BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[2]/D 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_sram2_2kb/addr0[3] 0.04 0.46 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10593,6 +9831,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
+mprj/u_sram2_2kb/addr0[4] 0.04 0.46 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10605,14 +9844,8 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3041_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3041__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_2968_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3023_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3023__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2968__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[5]_D/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[2].Do_FF[5]/D 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10631,7 +9864,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_sram6_2kb/addr0[3] 0.04 0.46 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10664,16 +9896,11 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3055_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2986__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3059_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_2986_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3055__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10681,6 +9908,7 @@
soc/core.RAM128/BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[5]/D 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
+mprj/u_sram6_2kb/addr0[4] 0.04 0.46 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10691,13 +9919,11 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3031_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3031__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10716,52 +9942,19 @@
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2989__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3017__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3017_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3015_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3015__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3021__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3021_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3013__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3013_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3025__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_2989_/S0 1.50 1.92 -0.42 (VIOLATED)
+mprj/u_sram1_2kb/addr0[8] 0.04 0.46 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3025_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.BYTE[3].FLOATBUF0[31].cell/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3069__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3027__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3027_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3067_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3067__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3069_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3073_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3073__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3061_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3061__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3071__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3071_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2906__A/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_2905_/A 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_2906_/A 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2905__A/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3011_/S0 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3011__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3065__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
-mprj/u_wb_host/_3065_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3009__S0/DIODE 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
-mprj/u_wb_host/_3009_/S0 1.50 1.92 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.94 -0.42 (VIOLATED)
@@ -10785,30 +9978,13 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[2].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_wb_host/_3019_/S0 1.50 1.91 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3019__S0/DIODE 1.50 1.91 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3162__A1/DIODE 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/_3162_/A1 1.50 1.91 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3161__A/DIODE 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/_3161_/A 1.50 1.91 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[6]/D 1.50 1.91 -0.41 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[6]_D/DIODE 1.50 1.91 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2971__S0/DIODE 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/_2971_/S0 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/_3063_/S0 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3063__S0/DIODE 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3059__S0/DIODE 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3155__A1/DIODE 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/_3155_/A1 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/_3156_/A 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3156__A/DIODE 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3154__A/DIODE 1.50 1.91 -0.41 (VIOLATED)
-mprj/u_wb_host/_3154_/A 1.50 1.91 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[0]_D/DIODE 1.50 1.91 -0.41 (VIOLATED)
@@ -10857,7 +10033,6 @@
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_sram7_2kb/addr0[4] 0.04 0.45 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
@@ -10918,6 +10093,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
+mprj/u_sram4_2kb/addr0[5] 0.04 0.45 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
@@ -10947,7 +10123,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_sram4_2kb/addr0[3] 0.04 0.45 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
@@ -10969,7 +10144,6 @@
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_sram5_2kb/addr0[6] 0.04 0.45 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[2].RAM32.BYTE[0].FLOATBUF0[2].cell/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
@@ -10995,7 +10169,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_wb_host/_5494_/Q 1.51 1.91 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
@@ -11018,7 +10191,6 @@
soc/core.RAM256/ANTENNA_BANK128[0].RAM128.BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[2]_D/DIODE 1.50 1.91 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[2]/D 1.50 1.91 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
-mprj/u_sram1_2kb/addr0[4] 0.04 0.45 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
@@ -11077,6 +10249,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
+mprj/u_sram6_2kb/addr0[2] 0.04 0.45 -0.41 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[0].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.93 -0.41 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF0[15].cell/Z 1.52 1.93 -0.41 (VIOLATED)
@@ -11154,6 +10327,7 @@
soc/core.RAM128/BLOCK[1].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
+mprj/u_sram3_2kb/addr0[3] 0.04 0.44 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
@@ -11239,6 +10413,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM128/ANTENNA_BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[1]_D/DIODE 1.50 1.90 -0.40 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[1]/D 1.50 1.90 -0.40 (VIOLATED)
+mprj/u_sram5_2kb/addr0[7] 0.04 0.44 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
@@ -11318,10 +10493,10 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
+mprj/u_sram1_2kb/addr0[7] 0.04 0.44 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
-mprj/u_sram4_2kb/addr0[5] 0.04 0.44 -0.40 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
@@ -11330,7 +10505,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
-mprj/u_sram5_2kb/addr0[3] 0.04 0.44 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[4].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF0/Z 1.52 1.92 -0.40 (VIOLATED)
@@ -11616,6 +10790,7 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
+mprj/u_sram0_2kb/addr0[4] 0.04 0.43 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
@@ -11630,6 +10805,7 @@
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
+mprj/u_sram5_2kb/addr0[4] 0.04 0.43 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.BYTE[0].FLOATBUF0[0].cell/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
@@ -11797,6 +10973,7 @@
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
+mprj/u_sram7_2kb/addr0[4] 0.04 0.43 -0.39 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
@@ -11809,6 +10986,7 @@
soc/core.RAM128/BLOCK[2].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
+mprj/u_sram5_2kb/addr0[8] 0.04 0.43 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 1.91 -0.39 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[0]/D 1.50 1.89 -0.39 (VIOLATED)
@@ -11968,6 +11146,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
+mprj/u_sram7_2kb/addr0[8] 0.04 0.42 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
@@ -11975,6 +11154,8 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
+mprj/u_sram1_2kb/addr0[3] 0.04 0.42 -0.38 (VIOLATED)
+mprj/u_sram3_2kb/addr0[2] 0.04 0.42 -0.38 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.BYTE[2].FLOATBUF0[20].cell/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
@@ -12070,6 +11251,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
+mprj/u_sram5_2kb/addr0[6] 0.04 0.42 -0.38 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[1].RAM32.BYTE[3].FLOATBUF0[30].cell/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
@@ -12124,7 +11306,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
-mprj/u_sram5_2kb/addr0[7] 0.04 0.42 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[2].OBUF0/Z 1.52 1.90 -0.38 (VIOLATED)
@@ -12211,6 +11392,7 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
+mprj/u_sram3_2kb/addr0[7] 0.04 0.41 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
@@ -12220,6 +11402,9 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
+mprj/u_sram1_2kb/addr0[5] 0.04 0.41 -0.37 (VIOLATED)
+mprj/u_rp_north/ANTENNA__15__A/DIODE 1.50 1.87 -0.37 (VIOLATED)
+mprj/u_rp_north/_15_/A 1.50 1.87 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.BYTE[0].FLOATBUF0[0].__cell__/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
@@ -12228,10 +11413,10 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
-mprj/u_sram1_2kb/addr0[6] 0.04 0.41 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[3].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
+mprj/u_sram5_2kb/addr0[5] 0.04 0.41 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
@@ -12240,6 +11425,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
+mprj/u_sram5_2kb/addr0[2] 0.04 0.41 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
@@ -12257,7 +11443,9 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF0[23].cell/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
+mprj/u_sram3_2kb/addr0[6] 0.04 0.41 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
+mprj/u_sram7_2kb/addr0[2] 0.04 0.41 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.Do0_REG.OUTREG_BYTE[3].Do_FF[7]/D 1.50 1.87 -0.37 (VIOLATED)
@@ -12274,6 +11462,8 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
+mprj/u_mbist0/ANTENNA_hold45_A/DIODE 1.50 1.87 -0.37 (VIOLATED)
+mprj/u_mbist0/hold45/A 1.50 1.87 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
@@ -12409,6 +11599,7 @@
soc/core.RAM256/ANTENNA_BANK128[0].RAM128.BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[5]_D/DIODE 1.50 1.87 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.Do0_REG.OUTREG_BYTE[0].Do_FF[5]/D 1.50 1.87 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
+mprj/u_sram1_2kb/addr0[2] 0.04 0.41 -0.37 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.BYTE[0].FLOATBUF0[3].cell/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.89 -0.37 (VIOLATED)
@@ -12566,6 +11757,8 @@
soc/core.RAM128/BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[4].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
+mprj/u_sram1_2kb/addr0[4] 0.04 0.40 -0.36 (VIOLATED)
+mprj/u_sram3_2kb/addr0[8] 0.04 0.40 -0.36 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[3].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
@@ -12782,6 +11975,7 @@
soc/core.RAM128/BLOCK[2].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[6].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
+mprj/u_sram7_2kb/addr0[7] 0.04 0.40 -0.36 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[7].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 1.88 -0.36 (VIOLATED)
@@ -12865,6 +12059,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[2].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
+mprj/u_sram1_2kb/addr0[6] 0.04 0.39 -0.35 (VIOLATED)
soc/core.RAM128/BLOCK[2].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[1].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[6].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
@@ -12958,6 +12153,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[5].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
soc/core.RAM128/BLOCK[3].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
+mprj/u_sram3_2kb/addr0[4] 0.04 0.39 -0.35 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[1].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[5].OBUF0/Z 1.52 1.87 -0.35 (VIOLATED)
@@ -14271,7 +13467,7 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
-mprj/u_sram4_2kb/addr0[0] 0.04 0.31 -0.27 (VIOLATED)
+mprj/u_sram0_2kb/addr0[0] 0.04 0.31 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
@@ -14297,7 +13493,6 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
-mprj/u_sram6_2kb/addr0[1] 0.04 0.31 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.79 -0.27 (VIOLATED)
@@ -14307,349 +13502,71 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.BYTE[3].FLOATBUF0[28].cell/Z 1.52 1.78 -0.26 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.BYTE[3].FLOATBUF0[26].cell/Z 1.52 1.78 -0.26 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.78 -0.26 (VIOLATED)
+mprj/u_sram2_2kb/wmask0[0] 0.04 0.30 -0.26 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.78 -0.26 (VIOLATED)
-mprj/u_wb_host/_3709_/Y 1.49 1.75 -0.26 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[0].OBUF0/Z 1.52 1.78 -0.26 (VIOLATED)
-mprj/u_wb_host/_3790_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3788_/B1 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3788__B1/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3790__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3778__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3778_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3777__B1/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3777_/B1 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3825_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3786_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3825__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3824_/B1 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3824__B1/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3765_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3781_/B1 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3782_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3786__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3764_/B1 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3764__B1/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3782__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3765__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3781__B1/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3794_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3784_/B1 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3784__B1/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3794__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3833_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3833__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_sram0_2kb/addr0[1] 0.04 0.30 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3864__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3864_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3915_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3915__A2/DIODE 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3714_/A2 1.50 1.76 -0.26 (VIOLATED)
-mprj/u_wb_host/_3728_/B 1.50 1.76 -0.26 (VIOLATED)
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-mprj/u_wb_host/_3053_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3053__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3045__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3045_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3041_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3041__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_2968_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2968__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3023_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3023__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_2971_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2971__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3063_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3063__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3055_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3055__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2986__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_2986_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3059__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3059_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3155_/B1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3017__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3017_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3015_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3015__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3021_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3025_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3021__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3025__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3013_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3013__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3156_/B 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3069_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3069__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3011_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_2907_/A 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2907__A/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3155__B1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3011__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3156__B/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3071_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3009_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3073_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3067_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3073__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3071__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3061__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3061_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3065_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3065__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3031_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3027_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3031__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3027__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3067__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2989__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_2989_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3009__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3161__B/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_2686_/A 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__2686__A/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3161_/B 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3019__S1/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3019_/S1 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/ANTENNA__3162__A2/DIODE 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_3162_/A2 1.50 1.59 -0.09 (VIOLATED)
-mprj/u_wb_host/_5495_/Q 1.51 1.59 -0.09 (VIOLATED)
+mprj/u_sram5_2kb/addr0[1] 0.04 0.20 -0.16 (VIOLATED)
+mprj/u_sram1_2kb/wmask0[3] 0.04 0.20 -0.16 (VIOLATED)
+mprj/u_sram7_2kb/wmask0[3] 0.04 0.19 -0.15 (VIOLATED)
+mprj/u_sram1_2kb/wmask0[2] 0.04 0.18 -0.14 (VIOLATED)
+mprj/u_sram7_2kb/wmask0[2] 0.04 0.18 -0.14 (VIOLATED)
+mprj/u_sram3_2kb/wmask0[2] 0.04 0.18 -0.14 (VIOLATED)
+mprj/u_sram5_2kb/wmask0[2] 0.04 0.17 -0.13 (VIOLATED)
+mprj/u_rp_north/_11_/X 1.51 1.63 -0.12 (VIOLATED)
+mprj/u_rp_north/_05_/X 1.51 1.62 -0.11 (VIOLATED)
+mprj/u_rp_north/_02_/X 1.51 1.59 -0.08 (VIOLATED)
+mprj/u_rp_north/_38_/X 1.51 1.57 -0.05 (VIOLATED)
+mprj/u_rp_north/wire103/A 1.50 1.54 -0.04 (VIOLATED)
+mprj/u_rp_north/ANTENNA_wire103_A/DIODE 1.50 1.54 -0.04 (VIOLATED)
+mprj/u_rp_north/_35_/X 1.51 1.54 -0.03 (VIOLATED)
+mprj/u_rp_north/_32_/X 1.51 1.52 -0.01 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
-mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X 12 576 -564 (VIOLATED)
-mprj/u_pinmux/input67/X 12 386 -374 (VIOLATED)
-mprj/u_wb_host/_5494_/Q 12 152 -140 (VIOLATED)
-mprj/u_wb_host/_5495_/Q 12 150 -138 (VIOLATED)
-mprj/u_wb_host/_2910_/X 12 142 -130 (VIOLATED)
-mprj/u_wb_host/_4737_/X 12 138 -126 (VIOLATED)
-mprj/u_wb_host/_3365_/Y 12 136 -124 (VIOLATED)
-mprj/u_wb_host/_3299_/Y 12 122 -110 (VIOLATED)
-mprj/u_wb_host/_3709_/Y 12 88 -76 (VIOLATED)
-mprj/u_wb_host/_2787_/X 12 80 -68 (VIOLATED)
-mprj/u_wb_host/_2794_/X 12 76 -64 (VIOLATED)
-mprj/u_wb_host/max_length355/X 12 76 -64 (VIOLATED)
-mprj/u_wb_host/_4057_/Y 12 74 -62 (VIOLATED)
-mprj/u_wb_host/max_length360/X 12 74 -62 (VIOLATED)
-mprj/u_wb_host/max_length362/X 12 74 -62 (VIOLATED)
-mprj/u_pinmux/_322_/X 12 72 -60 (VIOLATED)
-mprj/u_pinmux/_333_/X 12 72 -60 (VIOLATED)
-mprj/u_pinmux/_370_/X 12 72 -60 (VIOLATED)
-mprj/u_wb_host/_3135_/Y 12 72 -60 (VIOLATED)
-mprj/u_wb_host/_2788_/Y 12 70 -58 (VIOLATED)
-mprj/u_wb_host/_2791_/X 12 70 -58 (VIOLATED)
-mprj/u_wb_host/max_length357/X 12 70 -58 (VIOLATED)
-mprj/u_wb_host/max_length368/X 12 70 -58 (VIOLATED)
-mprj/u_wb_host/max_length369/X 12 70 -58 (VIOLATED)
-mprj/u_wb_host/wire356/X 12 70 -58 (VIOLATED)
-mprj/u_wb_host/_2819_/X 12 68 -56 (VIOLATED)
-mprj/u_wb_host/_2899_/Y 12 68 -56 (VIOLATED)
-mprj/u_wb_host/_3134_/Y 12 68 -56 (VIOLATED)
-mprj/u_wb_host/_6527_/Q 12 68 -56 (VIOLATED)
-mprj/u_wb_host/max_length364/X 12 68 -56 (VIOLATED)
-mprj/u_wb_host/wire363/X 12 68 -56 (VIOLATED)
-mprj/u_pinmux/_320_/Y 12 66 -54 (VIOLATED)
-mprj/u_pinmux/_321_/Y 12 66 -54 (VIOLATED)
-mprj/u_wb_host/_3628_/Y 12 66 -54 (VIOLATED)
-mprj/u_wb_host/_4082_/Y 12 66 -54 (VIOLATED)
-mprj/u_wb_host/_4084_/Y 12 66 -54 (VIOLATED)
-mprj/u_wb_host/_5174_/Y 12 66 -54 (VIOLATED)
-mprj/u_wb_host/max_length374/X 12 66 -54 (VIOLATED)
-mprj/u_wb_host/_2742_/X 12 64 -52 (VIOLATED)
-mprj/u_wb_host/_3727_/Y 12 64 -52 (VIOLATED)
-mprj/u_wb_host/_3924_/X 12 64 -52 (VIOLATED)
-mprj/u_wb_host/_4160_/Y 12 64 -52 (VIOLATED)
-mprj/u_wb_host/_4355_/Y 12 64 -52 (VIOLATED)
-mprj/u_wb_host/_5356_/X 12 64 -52 (VIOLATED)
-mprj/u_wb_host/_5390_/X 12 64 -52 (VIOLATED)
-mprj/u_wb_host/_5410_/X 12 64 -52 (VIOLATED)
-mprj/u_wb_host/max_length359/X 12 64 -52 (VIOLATED)
-mprj/u_wb_host/wire337/X 12 64 -52 (VIOLATED)
-mprj/u_wb_host/wire341/X 12 64 -52 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.DIBUF[0].__cell__/X 12 64 -52 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.DIBUF[10].__cell__/X 12 64 -52 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.DIBUF[11].__cell__/X 12 64 -52 (VIOLATED)
@@ -15034,32 +13951,12 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.DIBUF[7].cell/X 12 64 -52 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.DIBUF[8].cell/X 12 64 -52 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.DIBUF[9].cell/X 12 64 -52 (VIOLATED)
-mprj/u_wb_host/_3342_/Y 12 62 -50 (VIOLATED)
-mprj/u_wb_host/max_length373/X 12 62 -50 (VIOLATED)
-mprj/u_wb_host/_3366_/X 12 60 -48 (VIOLATED)
-mprj/u_wb_host/max_length367/X 12 60 -48 (VIOLATED)
-mprj/u_wb_host/max_length371/X 12 58 -46 (VIOLATED)
-mprj/u_wb_host/max_length372/X 12 56 -44 (VIOLATED)
-mprj/u_wb_host/max_length376/X 12 54 -42 (VIOLATED)
-mprj/u_wb_host/max_length375/X 12 52 -40 (VIOLATED)
-mprj/u_wb_host/max_length377/X 12 52 -40 (VIOLATED)
-mprj/u_wb_host/_4062_/Y 12 50 -38 (VIOLATED)
-mprj/u_wb_host/_5053_/X 12 50 -38 (VIOLATED)
-mprj/u_wb_host/max_length334/X 12 50 -38 (VIOLATED)
-mprj/u_wb_host/max_length361/X 12 50 -38 (VIOLATED)
-mprj/u_wb_host/_4061_/X 12 48 -36 (VIOLATED)
soc/clkbuf_leaf_58_core_clk/X 12 48 -36 (VIOLATED)
-mprj/u_wb_host/_6420_/Q 12 46 -34 (VIOLATED)
-mprj/u_wb_host/wire332/X 12 46 -34 (VIOLATED)
-mprj/u_wb_host/wire339/X 12 46 -34 (VIOLATED)
soc/clkbuf_leaf_137_core_clk/X 12 46 -34 (VIOLATED)
soc/clkbuf_leaf_178_core_clk/X 12 46 -34 (VIOLATED)
soc/clkbuf_leaf_36_core_clk/X 12 46 -34 (VIOLATED)
soc/clkbuf_leaf_395_core_clk/X 12 46 -34 (VIOLATED)
soc/clkbuf_leaf_51_core_clk/X 12 46 -34 (VIOLATED)
-mprj/u_wb_host/_4058_/X 12 44 -32 (VIOLATED)
-mprj/u_wb_host/max_length370/X 12 44 -32 (VIOLATED)
-mprj/u_wb_host/wire333/X 12 44 -32 (VIOLATED)
soc/clkbuf_leaf_127_core_clk/X 12 44 -32 (VIOLATED)
soc/clkbuf_leaf_246_core_clk/X 12 44 -32 (VIOLATED)
soc/clkbuf_leaf_24_core_clk/X 12 44 -32 (VIOLATED)
@@ -15067,9 +13964,6 @@
soc/clkbuf_leaf_318_core_clk/X 12 44 -32 (VIOLATED)
soc/clkbuf_leaf_50_core_clk/X 12 44 -32 (VIOLATED)
soc/clkbuf_leaf_57_core_clk/X 12 44 -32 (VIOLATED)
-mprj/u_wb_host/_4905_/X 12 42 -30 (VIOLATED)
-mprj/u_wb_host/max_length331/X 12 42 -30 (VIOLATED)
-mprj/u_wb_host/max_length358/X 12 42 -30 (VIOLATED)
soc/clkbuf_leaf_106_core_clk/X 12 42 -30 (VIOLATED)
soc/clkbuf_leaf_177_core_clk/X 12 42 -30 (VIOLATED)
soc/clkbuf_leaf_220_core_clk/X 12 42 -30 (VIOLATED)
@@ -15077,15 +13971,6 @@
soc/clkbuf_leaf_250_core_clk/X 12 42 -30 (VIOLATED)
soc/clkbuf_leaf_360_core_clk/X 12 42 -30 (VIOLATED)
soc/fanout1424/X 12 41 -29 (VIOLATED)
-mprj/u_pinmux/_323_/X 12 40 -28 (VIOLATED)
-mprj/u_wb_host/_2766_/X 12 40 -28 (VIOLATED)
-mprj/u_wb_host/_3300_/X 12 40 -28 (VIOLATED)
-mprj/u_wb_host/_3343_/X 12 40 -28 (VIOLATED)
-mprj/u_wb_host/_4906_/Y 12 40 -28 (VIOLATED)
-mprj/u_wb_host/_5062_/Y 12 40 -28 (VIOLATED)
-mprj/u_wb_host/hold1/X 12 40 -28 (VIOLATED)
-mprj/u_wb_host/max_length340/X 12 40 -28 (VIOLATED)
-mprj/u_wb_host/max_length366/X 12 40 -28 (VIOLATED)
soc/_30413_/Q 12 40 -28 (VIOLATED)
soc/_30433_/Q 12 40 -28 (VIOLATED)
soc/_30440_/Q 12 40 -28 (VIOLATED)
@@ -15500,8 +14385,6 @@
soc/fanout975/X 12 40 -28 (VIOLATED)
soc/fanout990/X 12 40 -28 (VIOLATED)
soc/fanout993/X 12 40 -28 (VIOLATED)
-mprj/u_wb_host/_4060_/Y 12 38 -26 (VIOLATED)
-mprj/u_wb_host/max_length365/X 12 38 -26 (VIOLATED)
soc/_24390_/X 12 38 -26 (VIOLATED)
soc/_26020_/Y 12 38 -26 (VIOLATED)
soc/clkbuf_5_18_1_core_clk/X 12 38 -26 (VIOLATED)
@@ -15528,12 +14411,6 @@
soc/wire1792/X 12 38 -26 (VIOLATED)
soc/wire1833/X 12 38 -26 (VIOLATED)
soc/wire2305/X 12 38 -26 (VIOLATED)
-mprj/u_pinmux/load_slew126/X 12 36 -24 (VIOLATED)
-mprj/u_pinmux/wire125/X 12 36 -24 (VIOLATED)
-mprj/u_wb_host/_4063_/Y 12 36 -24 (VIOLATED)
-mprj/u_wb_host/max_length335/X 12 36 -24 (VIOLATED)
-mprj/u_wb_host/max_length336/X 12 36 -24 (VIOLATED)
-mprj/u_wb_host/max_length338/X 12 36 -24 (VIOLATED)
soc/_17488_/X 12 36 -24 (VIOLATED)
soc/_29337_/Q 12 36 -24 (VIOLATED)
soc/_30414_/Q 12 36 -24 (VIOLATED)
@@ -15565,10 +14442,7 @@
soc/wire3454/X 12 36 -24 (VIOLATED)
soc/wire3486/X 12 36 -24 (VIOLATED)
soc/wire3678/X 12 36 -24 (VIOLATED)
-mprj/u_pinmux/load_slew128/X 12 34 -22 (VIOLATED)
-mprj/u_wb_host/_4352_/Y 12 34 -22 (VIOLATED)
-mprj/u_wb_host/_5665_/Q 12 34 -22 (VIOLATED)
-mprj/u_wb_host/hold2/X 12 34 -22 (VIOLATED)
+mprj/u_wb_host/clkbuf_3_1__f_wbs_clk_i/X 12 34 -22 (VIOLATED)
soc/_14395_/X 12 34 -22 (VIOLATED)
soc/_17245_/X 12 34 -22 (VIOLATED)
soc/_17535_/X 12 34 -22 (VIOLATED)
@@ -15666,10 +14540,7 @@
mprj/u_intercon/clkbuf_leaf_7_clk_i/X 12 32 -20 (VIOLATED)
mprj/u_intercon/clkbuf_leaf_8_clk_i/X 12 32 -20 (VIOLATED)
mprj/u_intercon/clkbuf_leaf_9_clk_i/X 12 32 -20 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_0_phy_tx_clk/X 12 32 -20 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_14_app_clk/X 12 32 -20 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_47_app_clk/X 12 32 -20 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_86_app_clk/X 12 32 -20 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_33_app_clk/X 12 32 -20 (VIOLATED)
mprj/u_mbist0/clkbuf_leaf_0_wb_clk_i/X 12 32 -20 (VIOLATED)
mprj/u_mbist0/clkbuf_leaf_10_wb_clk_i/X 12 32 -20 (VIOLATED)
mprj/u_mbist0/clkbuf_leaf_11_wb_clk_i/X 12 32 -20 (VIOLATED)
@@ -15710,17 +14581,22 @@
mprj/u_mbist1/clkbuf_leaf_7_wb_clk_i/X 12 32 -20 (VIOLATED)
mprj/u_mbist1/clkbuf_leaf_8_wb_clk_i/X 12 32 -20 (VIOLATED)
mprj/u_mbist1/clkbuf_leaf_9_wb_clk_i/X 12 32 -20 (VIOLATED)
-mprj/u_pinmux/clkbuf_0_mclk/X 12 32 -20 (VIOLATED)
-mprj/u_wb_host/_3562_/X 12 32 -20 (VIOLATED)
-mprj/u_wb_host/_3648_/Y 12 32 -20 (VIOLATED)
-mprj/u_wb_host/_4081_/Y 12 32 -20 (VIOLATED)
-mprj/u_wb_host/_5392_/X 12 32 -20 (VIOLATED)
-mprj/u_wb_host/_5666_/Q 12 32 -20 (VIOLATED)
-mprj/u_wb_host/clkbuf_3_1__f_wbs_clk_i/X 12 32 -20 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_9_0_lbist_clk_int/X 12 32 -20 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_32_wbm_clk_i/X 12 32 -20 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_4_wbm_clk_i/X 12 32 -20 (VIOLATED)
-mprj/u_wb_host/input25/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_0_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_10_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_11_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_12_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_13_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_14_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_15_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_18_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_18_wbm_clk_i/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_3_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_40_wbm_clk_i/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_4_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_5_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_6_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_7_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_8_u_uart2wb.baud_clk_16x/X 12 32 -20 (VIOLATED)
soc/_14359_/Y 12 32 -20 (VIOLATED)
soc/_14393_/X 12 32 -20 (VIOLATED)
soc/_18159_/X 12 32 -20 (VIOLATED)
@@ -15787,19 +14663,13 @@
soc/wire3712/X 12 32 -20 (VIOLATED)
soc/wire847/X 12 32 -20 (VIOLATED)
mprj/u_mac_wrap/clkbuf_3_0_0_app_clk/X 12 30 -18 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_3_2_0_app_clk/X 12 30 -18 (VIOLATED)
-mprj/u_mbist0/clkbuf_1_1_3_wb_clk_i/X 12 30 -18 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_4_1_0_phy_tx_clk/X 12 30 -18 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_53_app_clk/X 12 30 -18 (VIOLATED)
mprj/u_mbist0/clkbuf_leaf_19_wb_clk_i/X 12 30 -18 (VIOLATED)
-mprj/u_mbist1/clkbuf_1_1_3_wb_clk_i/X 12 30 -18 (VIOLATED)
mprj/u_mbist1/clkbuf_leaf_19_wb_clk_i/X 12 30 -18 (VIOLATED)
-mprj/u_pinmux/max_length127/X 12 30 -18 (VIOLATED)
-mprj/u_wb_host/_3561_/Y 12 30 -18 (VIOLATED)
-mprj/u_wb_host/_3652_/X 12 30 -18 (VIOLATED)
-mprj/u_wb_host/_4306_/X 12 30 -18 (VIOLATED)
-mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/X 12 30 -18 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_10_0_lbist_clk_int/X 12 30 -18 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_15_0_lbist_clk_int/X 12 30 -18 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_8_0_lbist_clk_int/X 12 30 -18 (VIOLATED)
+mprj/u_pinmux/clkbuf_leaf_1_mclk/X 12 30 -18 (VIOLATED)
+mprj/u_wb_host/clkbuf_4_2_0_lbist_clk_int/X 12 30 -18 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_16_u_uart2wb.baud_clk_16x/X 12 30 -18 (VIOLATED)
soc/_17474_/X 12 30 -18 (VIOLATED)
soc/_17487_/Y 12 30 -18 (VIOLATED)
soc/_17877_/X 12 30 -18 (VIOLATED)
@@ -15880,16 +14750,13 @@
soc/wire749/X 12 30 -18 (VIOLATED)
soc/wire706/X 12 29 -17 (VIOLATED)
mprj/u_intercon/clkbuf_leaf_28_clk_i/X 12 28 -16 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_4_3_0_phy_tx_clk/X 12 28 -16 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_3_1_0_app_clk/X 12 28 -16 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_3_3_0_app_clk/X 12 28 -16 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_10_app_clk/X 12 28 -16 (VIOLATED)
mprj/u_mbist0/clkbuf_3_1__f_u_mbist.mem_no[3].u_mem_sel.mem_clk/X 12 28 -16 (VIOLATED)
mprj/u_mbist1/clkbuf_3_1__f_u_mbist.mem_no[3].u_mem_sel.mem_clk/X 12 28 -16 (VIOLATED)
-mprj/u_wb_host/_2789_/X 12 28 -16 (VIOLATED)
-mprj/u_wb_host/_3114_/Y 12 28 -16 (VIOLATED)
-mprj/u_wb_host/_3650_/Y 12 28 -16 (VIOLATED)
-mprj/u_wb_host/_5054_/Y 12 28 -16 (VIOLATED)
-mprj/u_wb_host/_5843_/Q 12 28 -16 (VIOLATED)
-mprj/u_wb_host/_5883_/Q 12 28 -16 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_0_0_lbist_clk_int/X 12 28 -16 (VIOLATED)
+mprj/u_wb_host/clkbuf_4_12_0_lbist_clk_int/X 12 28 -16 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_1_u_uart2wb.baud_clk_16x/X 12 28 -16 (VIOLATED)
soc/_13828_/Y 12 28 -16 (VIOLATED)
soc/_17456_/X 12 28 -16 (VIOLATED)
soc/_19503_/Y 12 28 -16 (VIOLATED)
@@ -15959,14 +14826,16 @@
soc/wire828/X 12 28 -16 (VIOLATED)
soc/fanout1421/X 12 27 -15 (VIOLATED)
mprj/u_intercon/clkbuf_leaf_23_clk_i/X 12 26 -14 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_3_4_0_app_clk/X 12 26 -14 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_3_2_0_app_clk/X 12 26 -14 (VIOLATED)
mprj/u_mbist0/clkbuf_3_3__f_u_mbist.mem_no[0].u_mem_sel.mem_clk/X 12 26 -14 (VIOLATED)
mprj/u_mbist0/clkbuf_leaf_22_wb_clk_i/X 12 26 -14 (VIOLATED)
mprj/u_mbist1/clkbuf_3_3__f_u_mbist.mem_no[0].u_mem_sel.mem_clk/X 12 26 -14 (VIOLATED)
mprj/u_mbist1/clkbuf_leaf_22_wb_clk_i/X 12 26 -14 (VIOLATED)
-mprj/u_wb_host/_3947_/Y 12 26 -14 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_11_0_lbist_clk_int/X 12 26 -14 (VIOLATED)
+mprj/u_wb_host/clkbuf_4_10_0_lbist_clk_int/X 12 26 -14 (VIOLATED)
+mprj/u_wb_host/clkbuf_4_13_0_lbist_clk_int/X 12 26 -14 (VIOLATED)
+mprj/u_wb_host/clkbuf_4_14_0_lbist_clk_int/X 12 26 -14 (VIOLATED)
mprj/u_wb_host/clkbuf_4_3_0_lbist_clk_int/X 12 26 -14 (VIOLATED)
+mprj/u_wb_host/wire2/X 12 26 -14 (VIOLATED)
soc/_14481_/X 12 26 -14 (VIOLATED)
soc/_18536_/X 12 26 -14 (VIOLATED)
soc/_20363_/X 12 26 -14 (VIOLATED)
@@ -16067,21 +14936,16 @@
clock_ctrl/fanout28/X 12 24 -12 (VIOLATED)
mprj/u_intercon/clkbuf_leaf_22_clk_i/X 12 24 -12 (VIOLATED)
mprj/u_intercon/clkbuf_leaf_36_clk_i/X 12 24 -12 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_3_1_0_app_clk/X 12 24 -12 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_3_5_0_app_clk/X 12 24 -12 (VIOLATED)
mprj/u_mac_wrap/clkbuf_3_7_0_app_clk/X 12 24 -12 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_87_app_clk/X 12 24 -12 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_88_app_clk/X 12 24 -12 (VIOLATED)
mprj/u_mbist0/clkbuf_leaf_20_wb_clk_i/X 12 24 -12 (VIOLATED)
mprj/u_mbist0/clkbuf_leaf_23_wb_clk_i/X 12 24 -12 (VIOLATED)
mprj/u_mbist1/clkbuf_leaf_20_wb_clk_i/X 12 24 -12 (VIOLATED)
mprj/u_mbist1/clkbuf_leaf_23_wb_clk_i/X 12 24 -12 (VIOLATED)
-mprj/u_wb_host/_3145_/Y 12 24 -12 (VIOLATED)
-mprj/u_wb_host/_5754_/Q 12 24 -12 (VIOLATED)
-mprj/u_wb_host/_6463_/Q 12 24 -12 (VIOLATED)
+mprj/u_pinmux/clkbuf_leaf_17_mclk/X 12 24 -12 (VIOLATED)
+mprj/u_wb_host/clkbuf_1_1_1_u_uart2wb.baud_clk_16x/X 12 24 -12 (VIOLATED)
+mprj/u_wb_host/clkbuf_3_0__f_wbs_clk_i/X 12 24 -12 (VIOLATED)
mprj/u_wb_host/clkbuf_3_2__f_wbs_clk_i/X 12 24 -12 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_12_0_lbist_clk_int/X 12 24 -12 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_14_0_lbist_clk_int/X 12 24 -12 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_8_wbm_clk_i/X 12 24 -12 (VIOLATED)
pll/ringosc.ibufp01/Y 12 24 -12 (VIOLATED)
soc/_14105_/Y 12 24 -12 (VIOLATED)
soc/_17450_/X 12 24 -12 (VIOLATED)
@@ -16244,26 +15108,20 @@
soc/wire1663/X 12 23 -11 (VIOLATED)
housekeeping/fanout359/X 12 22 -10 (VIOLATED)
housekeeping/fanout407/X 12 22 -10 (VIOLATED)
-mprj/u_intercon/clkbuf_3_3_1_clk_i/X 12 22 -10 (VIOLATED)
mprj/u_intercon/clkbuf_leaf_30_clk_i/X 12 22 -10 (VIOLATED)
mprj/u_intercon/clkbuf_leaf_31_clk_i/X 12 22 -10 (VIOLATED)
mprj/u_intercon/clkbuf_leaf_48_clk_i/X 12 22 -10 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_3_2_0_phy_rx_clk/X 12 22 -10 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_3_3_0_app_clk/X 12 22 -10 (VIOLATED)
mprj/u_mac_wrap/clkbuf_3_3_0_phy_rx_clk/X 12 22 -10 (VIOLATED)
-mprj/u_mbist0/clkbuf_1_0_3_wb_clk_i/X 12 22 -10 (VIOLATED)
-mprj/u_mbist0/clkbuf_3_7__f_u_mbist.mem_no[1].u_mem_sel.mem_clk/X 12 22 -10 (VIOLATED)
-mprj/u_mbist1/clkbuf_1_0_3_wb_clk_i/X 12 22 -10 (VIOLATED)
-mprj/u_mbist1/clkbuf_3_7__f_u_mbist.mem_no[1].u_mem_sel.mem_clk/X 12 22 -10 (VIOLATED)
-mprj/u_wb_host/_3115_/X 12 22 -10 (VIOLATED)
-mprj/u_wb_host/_4598_/X 12 22 -10 (VIOLATED)
-mprj/u_wb_host/_5475_/Q 12 22 -10 (VIOLATED)
-mprj/u_wb_host/_5715_/Q 12 22 -10 (VIOLATED)
-mprj/u_wb_host/_6368_/Q 12 22 -10 (VIOLATED)
-mprj/u_wb_host/clkbuf_3_0__f_wbs_clk_i/X 12 22 -10 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_13_0_lbist_clk_int/X 12 22 -10 (VIOLATED)
-mprj/u_wb_host/clkbuf_4_2_0_lbist_clk_int/X 12 22 -10 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_8_wbm_clk_i/X 12 22 -10 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_3_4_0_app_clk/X 12 22 -10 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_3_6_0_app_clk/X 12 22 -10 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_4_3_0_phy_tx_clk/X 12 22 -10 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_4_7_0_phy_tx_clk/X 12 22 -10 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_20_app_clk/X 12 22 -10 (VIOLATED)
+mprj/u_mbist0/wire21/X 12 22 -10 (VIOLATED)
+mprj/u_mbist1/wire21/X 12 22 -10 (VIOLATED)
+mprj/u_pinmux/clkbuf_1_0__f_mclk/X 12 22 -10 (VIOLATED)
+mprj/u_pinmux/clkbuf_1_1__f_mclk/X 12 22 -10 (VIOLATED)
+mprj/u_pinmux/clkbuf_leaf_9_mclk/X 12 22 -10 (VIOLATED)
soc/_13827_/Y 12 22 -10 (VIOLATED)
soc/_14394_/X 12 22 -10 (VIOLATED)
soc/_17486_/X 12 22 -10 (VIOLATED)
@@ -16626,209 +15484,205 @@
mprj/u_intercon/fanout993/X 12 20 -8 (VIOLATED)
mprj/u_intercon/fanout996/X 12 20 -8 (VIOLATED)
mprj/u_intercon/fanout997/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_04817_/Y 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_05117_/Y 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_05598_/Y 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_05760_/Y 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_06710_/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_08923_/Q 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_08961_/Q 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_08962_/Q 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_09084_/Q 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_09423_/Q 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/_09841_/Q 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/_05138_/Y 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/_05653_/Y 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/_05817_/Y 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/_06767_/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/_06769_/Y 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/_09011_/Q 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/_09012_/Q 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/_09473_/Q 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_3_0_0_phy_rx_clk/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_3_5_0_app_clk/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/clkbuf_4_0_0_phy_tx_clk/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/clkbuf_4_6_0_phy_tx_clk/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_59_app_clk/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_80_app_clk/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout238/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout240/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout242/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout246/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout239/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout241/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout243/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout245/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout247/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout254/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout255/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout251/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout258/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout260/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout261/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout262/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout263/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout264/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout265/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout267/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout266/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout268/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout269/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout271/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout273/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout275/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout278/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout280/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout282/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout284/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout277/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout279/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout281/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout283/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout285/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout286/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout288/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout290/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout291/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout292/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout294/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout296/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout287/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout289/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout293/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout295/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout297/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout298/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout299/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout301/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout307/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout303/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout305/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout306/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout308/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout309/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout310/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout311/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout312/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout313/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout314/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout315/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout316/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout317/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout319/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout321/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout323/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout322/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout324/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout325/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout326/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout328/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout329/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout330/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout332/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout334/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout333/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout335/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout336/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout337/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout338/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout340/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout341/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout342/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout343/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout344/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout345/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout347/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout348/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout350/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout351/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout353/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout358/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout359/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout361/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout355/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout362/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout363/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout366/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout364/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout365/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout367/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout369/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout371/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout373/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout375/X 12 20 -8 (VIOLATED)
+mprj/u_mac_wrap/fanout374/X 12 20 -8 (VIOLATED)
mprj/u_mac_wrap/fanout376/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout377/X 12 20 -8 (VIOLATED)
-mprj/u_mac_wrap/fanout379/X 12 20 -8 (VIOLATED)
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@@ -16850,47 +15704,221 @@
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@@ -17374,7 +16420,6 @@
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@@ -17425,109 +16470,164 @@
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+mprj/u_wb_host/_4474_/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_4476_/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_4478_/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_4482_/Y 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_4499_/Y 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_4806_/Y 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_4824_/Y 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_4844_/Y 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_5678_/Q 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_5680_/Q 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_5681_/Q 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_5714_/Q 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_5715_/Q 12 16 -4 (VIOLATED)
+mprj/u_wb_host/_6442_/Q 12 16 -4 (VIOLATED)
+mprj/u_wb_host/clkbuf_1_0_1_u_uart2wb.baud_clk_16x/X 12 16 -4 (VIOLATED)
mprj/u_wb_host/clkbuf_3_4_0_wbm_clk_i/X 12 16 -4 (VIOLATED)
-mprj/u_wb_host/clkbuf_3_7_0_wbm_clk_i/X 12 16 -4 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_36_wbm_clk_i/X 12 16 -4 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_54_wbm_clk_i/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/clkbuf_4_0_0_lbist_clk_int/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_10_wbm_clk_i/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_34_wbm_clk_i/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_37_wbm_clk_i/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_9_u_uart2wb.baud_clk_16x/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout347/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout368/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout422/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout452/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout457/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout461/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout465/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout468/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout514/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout552/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout584/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/fanout706/X 12 16 -4 (VIOLATED)
mprj/u_wb_host/output136/X 12 16 -4 (VIOLATED)
mprj/u_wb_host/output139/X 12 16 -4 (VIOLATED)
mprj/u_wb_host/output152/X 12 16 -4 (VIOLATED)
mprj/u_wb_host/output162/X 12 16 -4 (VIOLATED)
-mprj/u_wb_host/wire344/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/output166/X 12 16 -4 (VIOLATED)
+mprj/u_wb_host/wire495/X 12 16 -4 (VIOLATED)
soc/_14258_/Y 12 16 -4 (VIOLATED)
soc/_14296_/X 12 16 -4 (VIOLATED)
soc/_14307_/X 12 16 -4 (VIOLATED)
@@ -18389,16 +17489,12 @@
housekeeping/fanout446/X 12 15 -3 (VIOLATED)
housekeeping/fanout454/X 12 15 -3 (VIOLATED)
housekeeping/fanout469/X 12 15 -3 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_31_phy_rx_clk/X 12 15 -3 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_90_app_clk/X 12 15 -3 (VIOLATED)
-mprj/u_pinmux/clkbuf_4_7_0_mclk/X 12 15 -3 (VIOLATED)
-mprj/u_pinmux/clkbuf_4_8_0_mclk/X 12 15 -3 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_15_wbm_clk_i/X 12 15 -3 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_16_wbm_clk_i/X 12 15 -3 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_22_wbm_clk_i/X 12 15 -3 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_26_wbm_clk_i/X 12 15 -3 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_2_wbm_clk_i/X 12 15 -3 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_30_wbm_clk_i/X 12 15 -3 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_75_app_clk/X 12 15 -3 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_95_app_clk/X 12 15 -3 (VIOLATED)
+mprj/u_wb_host/clkbuf_4_9_0_lbist_clk_int/X 12 15 -3 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_33_wbm_clk_i/X 12 15 -3 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_35_wbm_clk_i/X 12 15 -3 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_5_wbm_clk_i/X 12 15 -3 (VIOLATED)
soc/_29730_/Q 12 15 -3 (VIOLATED)
soc/max_length1638/X 12 15 -3 (VIOLATED)
soc/wire1142/X 12 15 -3 (VIOLATED)
@@ -18449,7 +17545,6 @@
mprj/u_intercon/fanout1097/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout1109/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout1136/X 12 14 -2 (VIOLATED)
-mprj/u_intercon/fanout1155/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout1156/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout642/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout654/X 12 14 -2 (VIOLATED)
@@ -18458,89 +17553,102 @@
mprj/u_intercon/fanout785/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout796/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout806/X 12 14 -2 (VIOLATED)
+mprj/u_intercon/fanout811/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout819/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout831/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout862/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout936/X 12 14 -2 (VIOLATED)
mprj/u_intercon/fanout943/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/_04571_/Y 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/_04593_/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/_06709_/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/_09845_/Q 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/_04425_/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/_04912_/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/_09137_/Q 12 14 -2 (VIOLATED)
mprj/u_mac_wrap/clkbuf_3_6_0_phy_rx_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_24_app_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_63_app_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_6_app_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_84_app_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_96_app_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout266/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout268/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout274/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout283/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout289/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout314/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout362/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout365/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout368/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout370/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout372/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_40_phy_rx_clk/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_51_app_clk/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_70_app_clk/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_89_app_clk/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout237/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout278/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout284/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout310/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout379/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout384/X 12 14 -2 (VIOLATED)
mprj/u_mac_wrap/fanout406/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout424/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout433/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout489/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout517/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout522/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout570/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout576/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout596/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout425/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout455/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout475/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout481/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout504/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout514/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout533/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout569/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout594/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout598/X 12 14 -2 (VIOLATED)
mprj/u_mac_wrap/fanout623/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout647/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout683/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout701/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout707/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout713/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout746/X 12 14 -2 (VIOLATED)
-mprj/u_mac_wrap/fanout765/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout679/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout680/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout724/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout745/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout755/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout761/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/fanout773/X 12 14 -2 (VIOLATED)
mprj/u_mac_wrap/input2/X 12 14 -2 (VIOLATED)
mprj/u_mac_wrap/input52/X 12 14 -2 (VIOLATED)
mprj/u_mac_wrap/input53/X 12 14 -2 (VIOLATED)
+mprj/u_mac_wrap/max_length6/X 12 14 -2 (VIOLATED)
mprj/u_mbist0/clkbuf_3_0__f_u_mbist.mem_no[0].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mbist0/clkbuf_3_0__f_u_mbist.mem_no[1].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist0/clkbuf_3_2__f_u_mbist.mem_no[1].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist0/clkbuf_3_4__f_u_mbist.mem_no[2].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist0/clkbuf_3_4__f_u_mbist.mem_no[3].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mbist0/clkbuf_3_5__f_u_mbist.mem_no[1].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist0/clkbuf_3_6__f_u_mbist.mem_no[0].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist0/clkbuf_leaf_25_wb_clk_i/X 12 14 -2 (VIOLATED)
+mprj/u_mbist0/wire16/X 12 14 -2 (VIOLATED)
+mprj/u_mbist0/wire19/X 12 14 -2 (VIOLATED)
mprj/u_mbist1/clkbuf_3_0__f_u_mbist.mem_no[0].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mbist1/clkbuf_3_0__f_u_mbist.mem_no[1].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist1/clkbuf_3_2__f_u_mbist.mem_no[1].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist1/clkbuf_3_4__f_u_mbist.mem_no[2].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist1/clkbuf_3_4__f_u_mbist.mem_no[3].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
-mprj/u_mbist1/clkbuf_3_5__f_u_mbist.mem_no[1].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist1/clkbuf_3_6__f_u_mbist.mem_no[0].u_mem_sel.mem_clk/X 12 14 -2 (VIOLATED)
mprj/u_mbist1/clkbuf_leaf_25_wb_clk_i/X 12 14 -2 (VIOLATED)
-mprj/u_pinmux/clkbuf_4_11_0_mclk/X 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_2810_/X 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_2829_/Y 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_3151_/Y 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_3301_/Y 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_3395_/Y 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_3396_/Y 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_5013_/X 12 14 -2 (VIOLATED)
+mprj/u_mbist1/wire16/X 12 14 -2 (VIOLATED)
+mprj/u_mbist1/wire19/X 12 14 -2 (VIOLATED)
+mprj/u_pinmux/fanout154/X 12 14 -2 (VIOLATED)
+mprj/u_pinmux/fanout162/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_2806_/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_3342_/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_3387_/Y 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_3388_/Y 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_3734_/Y 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_3932_/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_5003_/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_5114_/Y 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_5677_/Q 12 14 -2 (VIOLATED)
mprj/u_wb_host/_5683_/Q 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_5684_/Q 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_5689_/Q 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_5717_/Q 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_6276_/Q 12 14 -2 (VIOLATED)
-mprj/u_wb_host/_6445_/Q 12 14 -2 (VIOLATED)
-mprj/u_wb_host/clkbuf_3_6_0_wbm_clk_i/X 12 14 -2 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_23_wbm_clk_i/X 12 14 -2 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_52_wbm_clk_i/X 12 14 -2 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_57_wbm_clk_i/X 12 14 -2 (VIOLATED)
-mprj/u_wb_host/wire346/X 12 14 -2 (VIOLATED)
-mprj/u_wb_host/wire350/X 12 14 -2 (VIOLATED)
-mprj/u_wb_host/wire353/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/_5711_/Q 12 14 -2 (VIOLATED)
+mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/clkbuf_3_7_0_wbm_clk_i/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/clkbuf_4_11_0_lbist_clk_int/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/clkbuf_4_8_0_lbist_clk_int/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_2_wbm_clk_i/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout337/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout390/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout397/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout428/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout434/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout438/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout440/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout448/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout506/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout593/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout613/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout653/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout655/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout663/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout696/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout704/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/fanout709/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/wire502/X 12 14 -2 (VIOLATED)
+mprj/u_wb_host/wire504/X 12 14 -2 (VIOLATED)
pll/_390_/X 12 14 -2 (VIOLATED)
soc/_13830_/Y 12 14 -2 (VIOLATED)
soc/_13831_/Y 12 14 -2 (VIOLATED)
@@ -18883,17 +17991,21 @@
housekeeping/hold42/X 12 13 (VIOLATED)
housekeeping/hold666/X 12 13 (VIOLATED)
housekeeping/max_cap362/X 12 13 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_4_1_0_phy_tx_clk/X 12 13 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_4_app_clk/X 12 13 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_4_phy_rx_clk/X 12 13 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_13_app_clk/X 12 13 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_29_app_clk/X 12 13 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_45_phy_rx_clk/X 12 13 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_47_app_clk/X 12 13 (VIOLATED)
mprj/u_mac_wrap/clkbuf_leaf_53_phy_rx_clk/X 12 13 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_55_phy_rx_clk/X 12 13 (VIOLATED)
-mprj/u_mac_wrap/clkbuf_leaf_8_app_clk/X 12 13 (VIOLATED)
-mprj/u_pinmux/clkbuf_4_6_0_mclk/X 12 13 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_11_wbm_clk_i/X 12 13 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_13_wbm_clk_i/X 12 13 (VIOLATED)
-mprj/u_wb_host/clkbuf_leaf_18_wbm_clk_i/X 12 13 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_57_app_clk/X 12 13 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_5_app_clk/X 12 13 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_6_app_clk/X 12 13 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_92_app_clk/X 12 13 (VIOLATED)
+mprj/u_mac_wrap/clkbuf_leaf_93_app_clk/X 12 13 (VIOLATED)
+mprj/u_pinmux/clkbuf_leaf_0_mclk/X 12 13 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_12_wbm_clk_i/X 12 13 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_15_wbm_clk_i/X 12 13 (VIOLATED)
mprj/u_wb_host/clkbuf_leaf_27_wbm_clk_i/X 12 13 (VIOLATED)
+mprj/u_wb_host/clkbuf_leaf_56_wbm_clk_i/X 12 13 (VIOLATED)
soc/_19597_/Y 12 13 (VIOLATED)
soc/clkbuf_leaf_227_core_clk/X 12 13 (VIOLATED)
soc/wire1326/X 12 13 (VIOLATED)
@@ -18909,8 +18021,6 @@
Pin Limit Cap Slack
------------------------------------------------------------
-mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X 0.93 1.41 -0.48 (VIOLATED)
-mprj/u_wb_host/_5494_/Q 0.55 0.70 -0.15 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.BYTE[3].FLOATBUF0[26].__cell__/Z 0.22 0.37 -0.15 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF0/Z 0.22 0.37 -0.15 (VIOLATED)
soc/core.RAM128/BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF0/Z 0.22 0.37 -0.15 (VIOLATED)
@@ -19571,7 +18681,6 @@
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF0/Z 0.22 0.33 -0.11 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF0/Z 0.22 0.33 -0.11 (VIOLATED)
soc/core.RAM128/BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF0/Z 0.22 0.33 -0.11 (VIOLATED)
-mprj/u_wb_host/output135/X 0.32 0.43 -0.11 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF0[8].cell/Z 0.22 0.33 -0.11 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF0/Z 0.22 0.33 -0.11 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF0/Z 0.22 0.33 -0.11 (VIOLATED)
@@ -21915,7 +21024,6 @@
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[6].OBUF0/Z 0.22 0.32 -0.10 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[6].OBUF0/Z 0.22 0.32 -0.10 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[6].OBUF0/Z 0.22 0.32 -0.10 (VIOLATED)
-mprj/u_wb_host/_4057_/Y 0.22 0.32 -0.10 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.BYTE[2].FLOATBUF0[20].cell/Z 0.22 0.32 -0.10 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF0/Z 0.22 0.32 -0.10 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[4].OBUF0/Z 0.22 0.32 -0.10 (VIOLATED)
@@ -31519,7 +30627,7 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[4].OBUF0/Z 0.22 0.27 -0.05 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF0/Z 0.22 0.27 -0.05 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[4].OBUF0/Z 0.22 0.27 -0.05 (VIOLATED)
-mprj/u_wb_host/_3709_/Y 0.22 0.27 -0.05 (VIOLATED)
+mprj/u_wb_host/output135/X 0.32 0.36 -0.05 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.BYTE[3].FLOATBUF0[26].cell/Z 0.22 0.26 -0.05 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF0/Z 0.22 0.26 -0.05 (VIOLATED)
soc/core.RAM256/BANK128[1].RAM128.BLOCK[3].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF0/Z 0.22 0.26 -0.05 (VIOLATED)
@@ -31586,157 +30694,160 @@
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF0/Z 0.22 0.26 -0.04 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF0/Z 0.22 0.26 -0.04 (VIOLATED)
soc/core.RAM256/BANK128[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF0/Z 0.22 0.26 -0.04 (VIOLATED)
-mprj/u_wb_host/_5495_/Q 0.55 0.58 -0.03 (VIOLATED)
-mprj/u_sram0_2kb/dout0[0] 0.03 0.05 -0.03 (VIOLATED)
-mprj/u_sram6_2kb/dout0[2] 0.03 0.05 -0.02 (VIOLATED)
-mprj/u_sram1_2kb/dout0[31] 0.03 0.05 -0.02 (VIOLATED)
-mprj/u_sram4_2kb/dout0[0] 0.03 0.05 -0.02 (VIOLATED)
-mprj/u_sram6_2kb/dout0[4] 0.03 0.05 -0.02 (VIOLATED)
-mprj/u_sram6_2kb/dout0[3] 0.03 0.05 -0.02 (VIOLATED)
-mprj/u_sram7_2kb/dout0[31] 0.03 0.05 -0.02 (VIOLATED)
-mprj/u_sram2_2kb/dout0[4] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_pinmux/output70/X 0.32 0.35 -0.04 (VIOLATED)
+mprj/u_sram4_2kb/dout0[0] 0.03 0.05 -0.03 (VIOLATED)
+mprj/u_rp_north/_11_/X 0.32 0.34 -0.02 (VIOLATED)
+mprj/u_rp_north/_05_/X 0.32 0.34 -0.02 (VIOLATED)
+mprj/u_sram0_2kb/dout0[0] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram7_2kb/dout0[29] 0.03 0.05 -0.02 (VIOLATED)
mprj/u_sram6_2kb/dout0[0] 0.03 0.05 -0.02 (VIOLATED)
-mprj/u_sram0_2kb/dout0[4] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram4_2kb/dout0[3] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram3_2kb/dout0[30] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram0_2kb/dout0[3] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram7_2kb/dout0[30] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram7_2kb/dout0[29] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram2_2kb/dout0[2] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram4_2kb/dout0[2] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram0_2kb/dout0[2] 0.03 0.04 -0.02 (VIOLATED)
+mprj/u_sram0_2kb/dout0[3] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram5_2kb/dout0[31] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram4_2kb/dout0[3] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram7_2kb/dout0[30] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram6_2kb/dout0[2] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram3_2kb/dout0[27] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram1_2kb/dout0[31] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram3_2kb/dout0[26] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram3_2kb/dout0[30] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram3_2kb/dout0[28] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_rp_north/_02_/X 0.32 0.33 -0.02 (VIOLATED)
+mprj/u_sram2_2kb/dout0[2] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram2_2kb/dout0[0] 0.03 0.05 -0.02 (VIOLATED)
+mprj/u_sram5_2kb/dout0[30] 0.03 0.04 -0.02 (VIOLATED)
+mprj/u_sram1_2kb/dout0[30] 0.03 0.04 -0.02 (VIOLATED)
+mprj/u_sram0_2kb/dout0[1] 0.03 0.04 -0.02 (VIOLATED)
+mprj/u_sram7_2kb/dout0[27] 0.03 0.04 -0.02 (VIOLATED)
+mprj/u_sram5_2kb/dout0[28] 0.03 0.04 -0.02 (VIOLATED)
mprj/u_sram3_2kb/dout0[29] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram2_2kb/dout0[0] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram7_2kb/dout0[28] 0.03 0.04 -0.02 (VIOLATED)
+mprj/u_sram4_2kb/dout0[2] 0.03 0.04 -0.02 (VIOLATED)
+mprj/u_sram6_2kb/dout0[3] 0.03 0.04 -0.02 (VIOLATED)
+mprj/u_sram7_2kb/dout0[26] 0.03 0.04 -0.02 (VIOLATED)
+mprj/u_sram7_2kb/dout0[31] 0.03 0.04 -0.02 (VIOLATED)
mprj/u_sram4_2kb/dout0[1] 0.03 0.04 -0.02 (VIOLATED)
-mprj/u_sram2_2kb/dout0[6] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram3_2kb/dout0[26] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram2_2kb/dout0[3] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram0_2kb/dout0[6] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram3_2kb/dout0[27] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram7_2kb/dout0[27] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram0_2kb/dout0[5] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram0_2kb/dout0[1] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram4_2kb/dout0[5] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram7_2kb/dout0[0] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram6_2kb/dout0[4] 0.03 0.04 -0.02 (VIOLATED)
mprj/u_sram6_2kb/dout0[1] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram1_2kb/dout0[30] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram3_2kb/dout0[31] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram6_2kb/dout0[7] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram2_2kb/dout0[1] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram7_2kb/dout0[24] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram1_2kb/dout0[29] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram6_2kb/dout0[31] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram4_2kb/dout0[4] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram6_2kb/dout0[6] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram3_2kb/dout0[0] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram2_2kb/dout0[5] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram1_2kb/dout0[28] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram2_2kb/dout0[7] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram4_2kb/dout0[5] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram0_2kb/dout0[2] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram7_2kb/dout0[28] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram2_2kb/dout0[3] 0.03 0.04 -0.01 (VIOLATED)
mprj/u_sram7_2kb/dout0[25] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram1_2kb/dout0[26] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram0_2kb/dout0[7] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram3_2kb/dout0[28] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram1_2kb/dout0[27] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram2_2kb/dout0[8] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram5_2kb/dout0[30] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram6_2kb/dout0[5] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram4_2kb/dout0[6] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram0_2kb/dout0[29] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram7_2kb/dout0[23] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram6_2kb/dout0[30] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram0_2kb/dout0[6] 0.03 0.04 -0.01 (VIOLATED)
mprj/u_sram5_2kb/dout0[27] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram5_2kb/dout0[31] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram0_2kb/dout0[31] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram7_2kb/dout0[4] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram3_2kb/dout0[25] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram3_2kb/dout0[31] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram5_2kb/dout0[26] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram3_2kb/dout0[24] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram2_2kb/dout0[1] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram2_2kb/dout0[6] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram1_2kb/dout0[27] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_rp_north/_38_/X 0.32 0.33 -0.01 (VIOLATED)
+mprj/u_sram1_2kb/dout0[29] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram1_2kb/dout0[26] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram6_2kb/dout0[5] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram3_2kb/dout0[23] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram0_2kb/dout0[5] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram7_2kb/dout0[23] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram1_2kb/dout0[25] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram2_2kb/dout0[4] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram2_2kb/dout0[7] 0.03 0.04 -0.01 (VIOLATED)
mprj/u_sram6_2kb/dout0[8] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram5_2kb/dout0[28] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram4_2kb/dout0[7] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram2_2kb/dout0[5] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram4_2kb/dout0[6] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram0_2kb/dout0[4] 0.03 0.04 -0.01 (VIOLATED)
mprj/u_sram5_2kb/dout0[29] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram5_2kb/dout0[2] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram0_2kb/dout0[30] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram1_2kb/dout0[1] 0.03 0.04 -0.01 (VIOLATED)
-mprj/u_sram7_2kb/dout0[2] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram6_2kb/dout0[27] 0.03 0.03 -0.01 (VIOLATED)
+mprj/u_sram7_2kb/dout0[24] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram1_2kb/dout0[28] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram2_2kb/dout0[31] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram7_2kb/dout0[21] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram4_2kb/dout0[4] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram3_2kb/dout0[0] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram7_2kb/dout0[0] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram6_2kb/dout0[31] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram3_2kb/dout0[21] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram6_2kb/dout0[9] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram2_2kb/dout0[8] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram6_2kb/dout0[7] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram2_2kb/dout0[9] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram4_2kb/dout0[8] 0.03 0.04 -0.01 (VIOLATED)
+mprj/u_sram4_2kb/dout0[7] 0.03 0.03 -0.01 (VIOLATED)
+mprj/u_sram0_2kb/dout0[7] 0.03 0.03 -0.01 (VIOLATED)
+mprj/u_sram6_2kb/dout0[6] 0.03 0.03 -0.01 (VIOLATED)
mprj/u_sram7_2kb/dout0[1] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram2_2kb/dout0[9] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram7_2kb/dout0[26] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram6_2kb/dout0[28] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram4_2kb/dout0[8] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram6_2kb/dout0[9] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram3_2kb/dout0[23] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram0_2kb/dout0[8] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram7_2kb/dout0[20] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram0_2kb/dout0[9] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram3_2kb/dout0[25] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram1_2kb/dout0[0] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram3_2kb/dout0[1] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram5_2kb/dout0[0] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram3_2kb/dout0[24] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram7_2kb/dout0[3] 0.03 0.03 -0.01 (VIOLATED)
-mprj/u_sram2_2kb/dout0[27] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram1_2kb/dout0[2] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram2_2kb/dout0[31] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[2] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram7_2kb/dout0[5] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram2_2kb/dout0[10] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[3] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram6_2kb/dout0[10] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram2_2kb/dout0[11] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram0_2kb/dout0[27] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[5] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[24] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[29] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram6_2kb/dout0[12] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[6] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram7_2kb/dout0[21] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[30] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram1_2kb/dout0[4] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[10] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[4] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram6_2kb/dout0[26] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram0_2kb/dout0[11] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[9] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[27] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[31] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram2_2kb/dout0[26] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram0_2kb/dout0[13] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram5_2kb/dout0[23] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram1_2kb/dout0[24] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[21] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram0_2kb/dout0[24] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[22] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram2_2kb/dout0[30] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram2_2kb/dout0[28] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram0_2kb/dout0[23] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[17] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram5_2kb/dout0[26] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram1_2kb/dout0[25] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram7_2kb/dout0[7] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[11] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[9] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[16] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram0_2kb/dout0[28] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[8] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram7_2kb/dout0[6] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram5_2kb/dout0[4] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram5_2kb/dout0[25] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram7_2kb/dout0[17] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram5_2kb/dout0[22] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram1_2kb/dout0[3] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram2_2kb/dout0[12] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram0_2kb/dout0[10] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram1_2kb/dout0[23] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[23] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram6_2kb/dout0[11] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram1_2kb/dout0[21] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram7_2kb/dout0[8] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram0_2kb/dout0[26] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram3_2kb/dout0[20] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[28] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram6_2kb/dout0[29] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_rp_north/_35_/X 0.32 0.32 -0.01 (VIOLATED)
+mprj/u_sram7_2kb/dout0[5] 0.03 0.03 -0.01 (VIOLATED)
+mprj/u_sram5_2kb/dout0[25] 0.03 0.03 -0.01 (VIOLATED)
+mprj/u_sram4_2kb/dout0[24] 0.03 0.03 -0.01 (VIOLATED)
+mprj/u_sram7_2kb/dout0[22] 0.03 0.03 -0.01 (VIOLATED)
mprj/u_sram0_2kb/dout0[22] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram7_2kb/dout0[20] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram6_2kb/dout0[10] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram3_2kb/dout0[20] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram6_2kb/dout0[27] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram2_2kb/dout0[27] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[31] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[31] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram1_2kb/dout0[22] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[24] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram2_2kb/dout0[10] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram3_2kb/dout0[17] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram1_2kb/dout0[0] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram5_2kb/dout0[21] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[8] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram7_2kb/dout0[19] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram2_2kb/dout0[30] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram5_2kb/dout0[20] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_rp_north/_32_/X 0.32 0.32 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[30] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram1_2kb/dout0[18] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram3_2kb/dout0[22] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram3_2kb/dout0[1] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[11] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram6_2kb/dout0[28] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram1_2kb/dout0[24] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[29] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram7_2kb/dout0[17] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[23] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[22] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram5_2kb/dout0[24] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram7_2kb/dout0[2] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram2_2kb/dout0[28] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[27] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[10] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[27] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram5_2kb/dout0[18] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[29] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram7_2kb/dout0[16] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram6_2kb/dout0[30] 0.03 0.03 -0.00 (VIOLATED)
mprj/u_sram1_2kb/dout0[20] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram6_2kb/dout0[25] 0.03 0.03 -0.00 (VIOLATED)
-mprj/u_sram4_2kb/dout0[26] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[13] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[11] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[10] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[9] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram1_2kb/dout0[23] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram5_2kb/dout0[23] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[23] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram3_2kb/dout0[5] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram3_2kb/dout0[2] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[9] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram6_2kb/dout0[11] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram5_2kb/dout0[22] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[13] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram2_2kb/dout0[11] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram2_2kb/dout0[26] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram7_2kb/dout0[3] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram1_2kb/dout0[19] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram2_2kb/dout0[12] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram4_2kb/dout0[20] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram6_2kb/dout0[26] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[20] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram7_2kb/dout0[18] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[28] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram5_2kb/dout0[16] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram7_2kb/dout0[4] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram0_2kb/dout0[30] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram1_2kb/dout0[17] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram1_2kb/dout0[21] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram6_2kb/dout0[12] 0.03 0.03 -0.00 (VIOLATED)
+mprj/u_sram3_2kb/dout0[16] 0.03 0.03 -0.00 (VIOLATED)
diff --git a/sta/sta.log b/sta/sta.log
index d7fd6fd..84b3a13 100644
--- a/sta/sta.log
+++ b/sta/sta.log
@@ -104,70 +104,94 @@
Warning: /home/dinesha/workarea/efabless/MPW-7/caravel/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.min.spef line 2096, zero not connected to net gpio_control_in_2\[7\]/zero.
Warning: /home/dinesha/workarea/efabless/MPW-7/caravel/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.min.spef line 2088, zero not connected to net gpio_control_in_2\[0\]/zero.
Warning: /home/dinesha/workarea/efabless/MPW-7/caravel/signoff/gpio_control_block/openlane-signoff/spef/gpio_control_block.min.spef line 2096, zero not connected to net gpio_control_in_2\[0\]/zero.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 50466, pin m1_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 52797, pin m1_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 52799, pin m1_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 52800, pin m1_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 52801, pin m1_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 52803, pin m1_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 52990, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55293, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55295, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55296, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55297, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55298, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55299, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55300, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55301, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55302, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55303, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55304, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 55306, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 88503, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 89737, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 90848, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 149538, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 180240, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 187103, pin m1_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 249209, pin m1_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 255158, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 284049, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 285442, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 286051, pin m2_wbd_err_o not found.
-Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 46699, pin wbm_err_o not found.
-Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 46833, pin wbm_err_o not found.
-Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 46835, pin wbm_err_o not found.
-Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 46836, pin wbm_err_o not found.
-Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 46838, pin wbm_err_o not found.
-Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 194117, pin wbm_err_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 51903, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54433, pin wb_err_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54435, pin wb_err_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54435, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54437, pin wb_err_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54445, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54447, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54448, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54449, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54450, pin wb_err_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54450, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54452, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 216993, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 218379, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 51903, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54433, pin wb_err_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54435, pin wb_err_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54435, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54437, pin wb_err_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54445, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54447, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54448, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54449, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54450, pin wb_err_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54450, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54452, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 216993, pin wb_lack_o not found.
-Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 218379, pin wb_lack_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 51231, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53150, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53794, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53796, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53797, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53798, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53799, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53800, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53801, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53802, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53803, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53804, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53805, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53806, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53807, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53808, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53809, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53810, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 53812, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 54023, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 54147, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 54368, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56764, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56766, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56767, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56768, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56769, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56770, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56771, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56772, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56773, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56774, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56775, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 56777, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 89461, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 90116, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 90367, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 116311, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 138393, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 174423, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 177729, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 177730, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 186213, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 194180, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 223430, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 224335, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 262505, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 275176, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 275177, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 295878, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 297473, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 297474, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 298073, pin m2_wbd_err_o not found.
+Warning: ../signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.min.spef line 298294, pin m1_wbd_err_o not found.
+Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 44838, pin wbm_err_o not found.
+Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 45548, pin wbm_err_o not found.
+Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 45679, pin wbm_err_o not found.
+Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 45681, pin wbm_err_o not found.
+Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 45682, pin wbm_err_o not found.
+Warning: ../signoff/wb_host/openlane-signoff/spef/wb_host.min.spef line 45684, pin wbm_err_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 52061, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54489, pin wb_err_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54491, pin wb_err_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54491, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54493, pin wb_err_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54501, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54503, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54504, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54505, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54506, pin wb_err_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54506, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54508, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 219956, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 221392, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 52061, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54489, pin wb_err_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54491, pin wb_err_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54491, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54493, pin wb_err_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54501, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54503, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54504, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54505, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54506, pin wb_err_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54506, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 54508, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 219956, pin wb_lack_o not found.
+Warning: ../signoff/mbist_wrapper/openlane-signoff/spef/mbist_wrapper.min.spef line 221392, pin wb_lack_o not found.
### Caravel Signoff SDC
### Rev 3
### Date: 28/10/2022
@@ -182,9 +206,13 @@
create_clock -name wbs_clk_i -period 10.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
create_clock -name lbist_clk -period 10.0000 [get_pins {mprj/u_wb_host/clkbuf_0_u_lbist.lbist_clk/X}]
create_clock -name uart_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+create_clock -name mdio_refclk -period 10.0000 [get_pins {mprj/u_pinmux/u_clkgen.u_mdio_ref_mux.u_mux_l10/X}]
# Mac Tx and RX clock is 25Mhx-40ns
-create_clock -name mac_tx_clk -period 40.0000 [get_ports {mprj_io[5]}]
-create_clock -name mac_rx_clk -period 40.0000 [get_ports {mprj_io[12]}]
+create_clock -name pad_mac_tx_clk -period 40.0000 [get_ports {mprj_io[5]}]
+create_clock -name pad_mac_rx_clk -period 40.0000 [get_ports {mprj_io[12]}]
+create_clock -name mdio_clk -period 100.0000 [get_pins {mprj/u_pinmux/u_clkgen.u_mdio_clkbuf.u_buf/X}]
+create_generated_clock -name mac_tx_clk -add -source [get_ports {mprj_io[5]}] -master_clock [get_clocks pad_mac_tx_clk] -divide_by 1 -comment {mac tx clock} [get_pins {mprj/u_pinmux/mac_tx_clk}]
+create_generated_clock -name mac_rx_clk -add -source [get_ports {mprj_io[12]}] -master_clock [get_clocks pad_mac_rx_clk] -divide_by 1 -comment {mac rx clock} [get_pins {mprj/u_pinmux/mac_rx_clk}]
set_clock_uncertainty -setup 0.2500 [all_clocks]
set_clock_uncertainty -hold 0.1000 [all_clocks]
set_clock_groups \
@@ -194,8 +222,10 @@
-group [get_clocks {wbs_clk_i}]\
-group [get_clocks {uart_clk}]\
-group [get_clocks {lbist_clk}]\
- -group [get_clocks {mac_tx_clk}]\
- -group [get_clocks {mac_rx_clk}]\
+ -group [get_clocks {mac_tx_clk pad_mac_tx_clk}]\
+ -group [get_clocks {mac_rx_clk pad_mac_rx_clk}]\
+ -group [get_clocks {mdio_refclk}]\
+ -group [get_clocks {mdio_clk}]\
-group [get_clocks {hk_serial_clk}]\
-group [get_clocks {hk_serial_load}]\
-group [get_clocks {hkspi_clk}]
@@ -254,6 +284,38 @@
set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}]
set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}]
# set_output_delay $output_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}]
+########################################
+# phy_rx_clk Clock Domain
+########################################
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay -max 20.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[13]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay -min 2.0000 -clock [get_clocks {pad_mac_rx_clk}] -add_delay [get_ports {mprj_io[13]}]
+########################################
+# phy_tx_clk Clock Domain
+########################################
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[6]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[7]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[8]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[9]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[10]}]
+set_output_delay -max 20.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[11]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[6]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[7]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[8]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[9]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[10]}]
+set_output_delay -min -2.0000 -clock [get_clocks {pad_mac_tx_clk}] -add_delay [get_ports {mprj_io[11]}]
set_max_fanout 12 [current_design]
# synthesis max fanout should be less than 12 (7 maybe)
## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
@@ -283,13 +345,13 @@
set_case_analysis 0 [get_pins {mprj/u_mac_wrap/cfg_cska_mac[1]}]
set_case_analysis 0 [get_pins {mprj/u_mac_wrap/cfg_cska_mac[0]}]
set_case_analysis 0 [get_pins {mprj/u_mbist1/cfg_cska_mbist[3]}]
-set_case_analysis 1 [get_pins {mprj/u_mbist1/cfg_cska_mbist[2]}]
+set_case_analysis 0 [get_pins {mprj/u_mbist1/cfg_cska_mbist[2]}]
set_case_analysis 1 [get_pins {mprj/u_mbist1/cfg_cska_mbist[1]}]
-set_case_analysis 1 [get_pins {mprj/u_mbist1/cfg_cska_mbist[0]}]
+set_case_analysis 0 [get_pins {mprj/u_mbist1/cfg_cska_mbist[0]}]
set_case_analysis 0 [get_pins {mprj/u_mbist0/cfg_cska_mbist[3]}]
set_case_analysis 1 [get_pins {mprj/u_mbist0/cfg_cska_mbist[2]}]
-set_case_analysis 1 [get_pins {mprj/u_mbist0/cfg_cska_mbist[1]}]
-set_case_analysis 1 [get_pins {mprj/u_mbist0/cfg_cska_mbist[0]}]
+set_case_analysis 0 [get_pins {mprj/u_mbist0/cfg_cska_mbist[1]}]
+set_case_analysis 0 [get_pins {mprj/u_mbist0/cfg_cska_mbist[0]}]
set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_lbist[3]}]
set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_lbist[2]}]
set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_lbist[1]}]
@@ -300,7 +362,7 @@
set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}]
set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
-set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
@@ -353,6 +415,8 @@
set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]]
set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
set_false_path -from [get_ports gpio]
+#### LA Input to wb_host are false path
+set_false_path -through [get_pins mprj/u_wb_host/la_data_in[*] ]
# add loads for output ports (pads)
set min_cap 5
set max_cap 10
@@ -392,674 +456,2969 @@
# puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
# }
# -filter not supported in PT read_sdc ^
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6349_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5482_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.00 1.15 ^ mprj/u_wb_host/_6349_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/_5482_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 4.95 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6349_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.13 4.10 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 mprj/u_wb_host/clknet_3_7__leaf_wbs_clk_i (net)
+ 0.03 0.00 4.10 ^ mprj/u_wb_host/wire2/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.22 0.26 4.36 ^ mprj/u_wb_host/wire2/X (sky130_fd_sc_hd__clkbuf_4)
+ 26 0.07 mprj/u_wb_host/net853 (net)
+ 0.22 0.01 4.37 ^ mprj/u_wb_host/_5482_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.47 clock uncertainty
+ -0.29 4.18 clock reconvergence pessimism
+ 0.39 4.58 library removal time
+ 4.58 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.58 data required time
+ -4.95 data arrival time
-----------------------------------------------------------------------------
- 0.10 slack (MET)
+ 0.37 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6287_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_6545_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.00 1.15 ^ mprj/u_wb_host/_6287_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/_6545_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 4.95 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6287_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.13 4.10 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 mprj/u_wb_host/clknet_3_7__leaf_wbs_clk_i (net)
+ 0.03 0.00 4.10 ^ mprj/u_wb_host/wire2/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.22 0.26 4.36 ^ mprj/u_wb_host/wire2/X (sky130_fd_sc_hd__clkbuf_4)
+ 26 0.07 mprj/u_wb_host/net853 (net)
+ 0.22 0.01 4.37 ^ mprj/u_wb_host/_6545_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.47 clock uncertainty
+ -0.29 4.18 clock reconvergence pessimism
+ 0.39 4.58 library removal time
+ 4.58 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.58 data required time
+ -4.95 data arrival time
-----------------------------------------------------------------------------
- 0.10 slack (MET)
+ 0.37 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6286_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5471_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.00 1.15 ^ mprj/u_wb_host/_6286_/RESET_B (sky130_fd_sc_hd__dfrtp_2)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/_5471_/RESET_B (sky130_fd_sc_hd__dfrtp_2)
+ 4.95 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6286_/CLK (sky130_fd_sc_hd__dfrtp_2)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.13 4.10 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 mprj/u_wb_host/clknet_3_7__leaf_wbs_clk_i (net)
+ 0.03 0.00 4.10 ^ mprj/u_wb_host/wire2/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.22 0.26 4.36 ^ mprj/u_wb_host/wire2/X (sky130_fd_sc_hd__clkbuf_4)
+ 26 0.07 mprj/u_wb_host/net853 (net)
+ 0.22 0.01 4.37 ^ mprj/u_wb_host/_5471_/CLK (sky130_fd_sc_hd__dfrtp_2)
+ 0.10 4.47 clock uncertainty
+ -0.29 4.18 clock reconvergence pessimism
+ 0.40 4.58 library removal time
+ 4.58 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.58 data required time
+ -4.95 data arrival time
-----------------------------------------------------------------------------
- 0.10 slack (MET)
+ 0.37 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6288_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5508_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.15 ^ mprj/u_wb_host/_6288_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/_5508_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 4.95 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6288_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.13 4.10 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 mprj/u_wb_host/clknet_3_7__leaf_wbs_clk_i (net)
+ 0.03 0.00 4.10 ^ mprj/u_wb_host/wire2/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.22 0.26 4.36 ^ mprj/u_wb_host/wire2/X (sky130_fd_sc_hd__clkbuf_4)
+ 26 0.07 mprj/u_wb_host/net853 (net)
+ 0.22 0.01 4.37 ^ mprj/u_wb_host/_5508_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.47 clock uncertainty
+ -0.29 4.18 clock reconvergence pessimism
+ 0.39 4.58 library removal time
+ 4.58 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.58 data required time
+ -4.95 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.37 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6423_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5496_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.15 ^ mprj/u_wb_host/_6423_/RESET_B (sky130_fd_sc_hd__dfrtp_2)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/_5496_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 4.74 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6423_/CLK (sky130_fd_sc_hd__dfrtp_2)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_5__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.08 0.18 4.15 ^ mprj/u_wb_host/clkbuf_3_5__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 18 0.06 mprj/u_wb_host/clknet_3_5__leaf_wbs_clk_i (net)
+ 0.08 0.01 4.16 ^ mprj/u_wb_host/_5496_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.26 clock uncertainty
+ -0.29 3.97 clock reconvergence pessimism
+ 0.35 4.33 library removal time
+ 4.33 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.33 data required time
+ -4.74 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.41 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6523_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5489_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.15 ^ mprj/u_wb_host/_6523_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/fanout603/A (sky130_fd_sc_hd__buf_4)
+ 0.14 0.21 5.16 ^ mprj/u_wb_host/fanout603/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net603 (net)
+ 0.14 0.00 5.16 ^ mprj/u_wb_host/_5489_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 5.16 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6523_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.13 4.10 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 mprj/u_wb_host/clknet_3_7__leaf_wbs_clk_i (net)
+ 0.03 0.00 4.10 ^ mprj/u_wb_host/wire2/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.22 0.26 4.36 ^ mprj/u_wb_host/wire2/X (sky130_fd_sc_hd__clkbuf_4)
+ 26 0.07 mprj/u_wb_host/net853 (net)
+ 0.22 0.01 4.37 ^ mprj/u_wb_host/_5489_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.47 clock uncertainty
+ -0.29 4.18 clock reconvergence pessimism
+ 0.39 4.58 library removal time
+ 4.58 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.58 data required time
+ -5.16 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.58 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6422_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5483_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.15 ^ mprj/u_wb_host/_6422_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/fanout603/A (sky130_fd_sc_hd__buf_4)
+ 0.14 0.21 5.16 ^ mprj/u_wb_host/fanout603/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net603 (net)
+ 0.14 0.00 5.16 ^ mprj/u_wb_host/_5483_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 5.16 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6422_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.13 4.10 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 mprj/u_wb_host/clknet_3_7__leaf_wbs_clk_i (net)
+ 0.03 0.00 4.10 ^ mprj/u_wb_host/wire2/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.22 0.26 4.36 ^ mprj/u_wb_host/wire2/X (sky130_fd_sc_hd__clkbuf_4)
+ 26 0.07 mprj/u_wb_host/net853 (net)
+ 0.22 0.01 4.37 ^ mprj/u_wb_host/_5483_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.47 clock uncertainty
+ -0.29 4.18 clock reconvergence pessimism
+ 0.39 4.58 library removal time
+ 4.58 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.58 data required time
+ -5.16 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.58 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6424_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_6544_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.15 ^ mprj/u_wb_host/_6424_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/fanout603/A (sky130_fd_sc_hd__buf_4)
+ 0.14 0.21 5.16 ^ mprj/u_wb_host/fanout603/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net603 (net)
+ 0.14 0.00 5.16 ^ mprj/u_wb_host/_6544_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 5.16 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6424_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.13 4.10 ^ mprj/u_wb_host/clkbuf_3_7__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 mprj/u_wb_host/clknet_3_7__leaf_wbs_clk_i (net)
+ 0.03 0.00 4.10 ^ mprj/u_wb_host/wire2/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.22 0.26 4.36 ^ mprj/u_wb_host/wire2/X (sky130_fd_sc_hd__clkbuf_4)
+ 26 0.07 mprj/u_wb_host/net853 (net)
+ 0.22 0.01 4.37 ^ mprj/u_wb_host/_6544_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.47 clock uncertainty
+ -0.29 4.18 clock reconvergence pessimism
+ 0.39 4.58 library removal time
+ 4.58 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.58 data required time
+ -5.16 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.58 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6425_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5494_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.15 ^ mprj/u_wb_host/_6425_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/_5494_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 4.95 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6425_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_5__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.08 0.18 4.15 ^ mprj/u_wb_host/clkbuf_3_5__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 18 0.06 mprj/u_wb_host/clknet_3_5__leaf_wbs_clk_i (net)
+ 0.08 0.00 4.16 ^ mprj/u_wb_host/_5494_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.26 clock uncertainty
+ -0.29 3.97 clock reconvergence pessimism
+ 0.36 4.33 library removal time
+ 4.33 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.33 data required time
+ -4.95 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.62 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6525_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5472_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.15 ^ mprj/u_wb_host/_6525_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/_5472_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 4.95 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.18 0.18 ^ mprj/u_wb_host/_6525_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.28 clock uncertainty
- 0.00 0.28 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_6__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.08 0.18 4.15 ^ mprj/u_wb_host/clkbuf_3_6__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 20 0.06 mprj/u_wb_host/clknet_3_6__leaf_wbs_clk_i (net)
+ 0.08 0.00 4.16 ^ mprj/u_wb_host/_5472_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.26 clock uncertainty
+ -0.29 3.97 clock reconvergence pessimism
+ 0.36 4.33 library removal time
+ 4.33 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.33 data required time
+ -4.95 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.62 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6524_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5491_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.15 ^ mprj/u_wb_host/_6524_/RESET_B (sky130_fd_sc_hd__dfrtp_2)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/_5491_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 4.95 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.19 0.19 ^ mprj/u_wb_host/_6524_/CLK (sky130_fd_sc_hd__dfrtp_2)
- 0.10 0.29 clock uncertainty
- 0.00 0.29 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_5__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.08 0.18 4.15 ^ mprj/u_wb_host/clkbuf_3_5__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 18 0.06 mprj/u_wb_host/clknet_3_5__leaf_wbs_clk_i (net)
+ 0.08 0.00 4.16 ^ mprj/u_wb_host/_5491_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.26 clock uncertainty
+ -0.29 3.97 clock reconvergence pessimism
+ 0.36 4.33 library removal time
+ 4.33 data required time
-----------------------------------------------------------------------------
- 1.04 data required time
- -1.15 data arrival time
+ 4.33 data required time
+ -4.95 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.62 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6346_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5484_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.00 1.15 ^ mprj/u_wb_host/_6346_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/_5484_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 4.95 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.18 0.18 ^ mprj/u_wb_host/_6346_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.28 clock uncertainty
- 0.00 0.28 clock reconvergence pessimism
- 0.76 1.03 library removal time
- 1.03 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_6__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.08 0.18 4.15 ^ mprj/u_wb_host/clkbuf_3_6__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 20 0.06 mprj/u_wb_host/clknet_3_6__leaf_wbs_clk_i (net)
+ 0.08 0.00 4.16 ^ mprj/u_wb_host/_5484_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.10 4.26 clock uncertainty
+ -0.29 3.97 clock reconvergence pessimism
+ 0.36 4.33 library removal time
+ 4.33 data required time
-----------------------------------------------------------------------------
- 1.03 data required time
- -1.15 data arrival time
+ 4.33 data required time
+ -4.95 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.62 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6344_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5951_
+ (rising edge-triggered flip-flop clocked by wbs_clk_i)
+Endpoint: mprj/u_wb_host/_5488_
+ (removal check against rising-edge clock wbs_clk_i)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.00 1.15 ^ mprj/u_wb_host/_6344_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.40 0.40 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.40 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.51 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.10 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.61 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.69 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.79 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.88 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.02 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.12 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.14 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.27 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.11 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.48 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.59 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.13 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.09 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.81 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.13 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 1.94 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.04 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.15 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.09 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.24 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.12 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.36 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.46 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.11 2.56 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.56 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.15 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.71 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.12 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 2.83 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.11 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 2.94 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.27 3.21 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.22 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.26 3.47 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.47 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.21 3.68 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.69 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.07 0.16 3.84 ^ mprj/u_wb_host/clkbuf_3_4__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 14 0.05 mprj/u_wb_host/clknet_3_4__leaf_wbs_clk_i (net)
+ 0.07 0.00 3.85 ^ mprj/u_wb_host/_5951_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.31 4.16 ^ mprj/u_wb_host/_5951_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_async_wb.u_cmd_if.rd_reset_n (net)
+ 0.04 0.00 4.16 ^ mprj/u_wb_host/hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 4.74 ^ mprj/u_wb_host/hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net856 (net)
+ 0.13 0.00 4.74 ^ mprj/u_wb_host/fanout604/A (sky130_fd_sc_hd__buf_4)
+ 0.15 0.21 4.95 ^ mprj/u_wb_host/fanout604/X (sky130_fd_sc_hd__buf_4)
+ 10 0.05 mprj/u_wb_host/net604 (net)
+ 0.15 0.00 4.95 ^ mprj/u_wb_host/_5488_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
+ 4.95 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wbs_clk_i (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.18 0.18 ^ mprj/u_wb_host/_6344_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.28 clock uncertainty
- 0.00 0.28 clock reconvergence pessimism
- 0.76 1.03 library removal time
- 1.03 data required time
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/output291/X (sky130_fd_sc_hd__clkbuf_1)
+ 12 0.08 mprj/wbd_clk_int (net)
+ 0.87 0.00 0.00 ^ mprj/u_wb_host/input40/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.17 0.43 0.43 ^ mprj/u_wb_host/input40/X (sky130_fd_sc_hd__clkbuf_4)
+ 4 0.05 mprj/u_wb_host/net40 (net)
+ 0.17 0.00 0.43 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_1.X1 (net)
+ 0.05 0.00 0.55 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.11 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d1 (net)
+ 0.07 0.00 0.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.09 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_2.X1 (net)
+ 0.04 0.00 0.74 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d2 (net)
+ 0.08 0.00 0.85 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_3.X1 (net)
+ 0.05 0.00 0.95 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.15 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d3 (net)
+ 0.13 0.00 1.10 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.13 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_4.X1 (net)
+ 0.08 0.00 1.23 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.14 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d4 (net)
+ 0.10 0.00 1.37 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_5.X1 (net)
+ 0.05 0.00 1.47 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.06 0.12 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d5 (net)
+ 0.06 0.00 1.60 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.clkbuf_6.X1 (net)
+ 0.09 0.00 1.72 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_2)
+ 0.07 0.14 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_2)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d6 (net)
+ 0.07 0.00 1.86 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.10 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_7.X1 (net)
+ 0.06 0.00 1.96 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.11 0.14 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d7 (net)
+ 0.11 0.00 2.09 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.11 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_8.X1 (net)
+ 0.05 0.00 2.20 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.11 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d8 (net)
+ 0.08 0.00 2.32 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_9.X1 (net)
+ 0.05 0.00 2.42 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.10 0.13 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_9.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d9 (net)
+ 0.10 0.00 2.54 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.10 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.clkbuf_10.X1 (net)
+ 0.05 0.00 2.65 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.09 0.12 2.76 ^ mprj/u_wb_host/u_skew_wh.clkbuf_10.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
+ 2 0.01 mprj/u_wb_host/u_skew_wh.clk_d10 (net)
+ 0.09 0.00 2.76 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.07 0.16 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_05.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 mprj/u_wb_host/u_skew_wh.d05 (net)
+ 0.07 0.00 2.92 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.13 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d12 (net)
+ 0.04 0.00 3.05 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.12 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.00 mprj/u_wb_host/u_skew_wh.d21 (net)
+ 0.05 0.00 3.17 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.21 0.29 3.46 ^ mprj/u_wb_host/u_skew_wh.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 2 0.07 mprj/u_wb_host/net223 (net)
+ 0.22 0.00 3.47 ^ mprj/u_wb_host/output223/A (sky130_fd_sc_hd__buf_2)
+ 0.19 0.28 3.74 ^ mprj/u_wb_host/output223/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/wbd_clk_wh (net)
+ 0.19 0.00 3.74 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.10 0.23 3.97 ^ mprj/u_wb_host/clkbuf_0_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 8 0.08 mprj/u_wb_host/clknet_0_wbs_clk_i (net)
+ 0.10 0.00 3.97 ^ mprj/u_wb_host/clkbuf_3_6__f_wbs_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.08 0.18 4.15 ^ mprj/u_wb_host/clkbuf_3_6__f_wbs_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 20 0.06 mprj/u_wb_host/clknet_3_6__leaf_wbs_clk_i (net)
+ 0.08 0.00 4.16 ^ mprj/u_wb_host/_5488_/CLK (sky130_fd_sc_hd__dfrtp_4)
+ 0.10 4.26 clock uncertainty
+ -0.29 3.97 clock reconvergence pessimism
+ 0.36 4.33 library removal time
+ 4.33 data required time
-----------------------------------------------------------------------------
- 1.03 data required time
- -1.15 data arrival time
+ 4.33 data required time
+ -4.95 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.62 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6348_
- (removal check against rising-edge clock uart_clk)
+Startpoint: mprj/u_wb_host/_5949_
+ (rising edge-triggered flip-flop clocked by wb_clk)
+Endpoint: mprj/u_wb_host/_5843_ (removal check against rising-edge clock wb_clk)
Path Group: **async_default**
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wb_clk (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.00 1.15 ^ mprj/u_wb_host/_6348_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.15 data arrival time
+ 1.00 0.00 0.00 ^ clock (in)
+ 1 1.12 clock (net)
+ 1.00 0.00 0.00 ^ padframe/clock_pad/PAD (sky130_ef_io__gpiov2_pad_wrapped)
+ 0 1.12 clock (net)
+ 0.07 1.33 1.33 ^ padframe/clock_pad/IN (sky130_ef_io__gpiov2_pad_wrapped)
+ 1 0.00 clock_core (net)
+ 0.07 0.00 1.33 ^ flash_clkrst_buffers/BUF[2]/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.04 0.12 1.46 ^ flash_clkrst_buffers/BUF[2]/X (sky130_fd_sc_hd__clkbuf_8)
+ 4 0.01 clock_core_buf (net)
+ 0.04 0.00 1.46 ^ clock_ctrl/clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.12 1.57 ^ clock_ctrl/clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
+ 2 0.02 clock_ctrl/clknet_0_ext_clk (net)
+ 0.04 0.00 1.57 ^ clock_ctrl/clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.10 1.68 ^ clock_ctrl/clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 clock_ctrl/clknet_1_1__leaf_ext_clk (net)
+ 0.03 0.00 1.68 ^ clock_ctrl/_205_/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.10 0.15 1.83 ^ clock_ctrl/_205_/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 clock_ctrl/_037_ (net)
+ 0.10 0.00 1.83 ^ clock_ctrl/clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.14 1.97 ^ clock_ctrl/clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
+ 2 0.02 clock_ctrl/clknet_0__037_ (net)
+ 0.04 0.00 1.97 ^ clock_ctrl/clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.10 2.07 ^ clock_ctrl/clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 clock_ctrl/clknet_1_0__leaf__037_ (net)
+ 0.03 0.00 2.07 ^ clock_ctrl/_206_/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.09 0.14 2.22 ^ clock_ctrl/_206_/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 clock_ctrl/net10 (net)
+ 0.09 0.00 2.22 ^ clock_ctrl/clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.13 2.35 ^ clock_ctrl/clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
+ 2 0.02 clock_ctrl/clknet_0_net10 (net)
+ 0.04 0.00 2.35 ^ clock_ctrl/clkbuf_1_0__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.05 0.12 2.47 ^ clock_ctrl/clkbuf_1_0__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
+ 4 0.02 caravel_clk (net)
+ 0.05 0.00 2.47 ^ flash_clkrst_buffers/BUF[14]/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.04 0.12 2.59 ^ flash_clkrst_buffers/BUF[14]/X (sky130_fd_sc_hd__clkbuf_8)
+ 4 0.01 caravel_clk_buf (net)
+ 0.04 0.00 2.59 ^ soc/input1/A (sky130_fd_sc_hd__buf_6)
+ 0.13 0.15 2.74 ^ soc/input1/X (sky130_fd_sc_hd__buf_6)
+ 2 0.06 soc/net1 (net)
+ 0.13 0.01 2.76 ^ soc/wire4208/A (sky130_fd_sc_hd__buf_6)
+ 0.17 0.20 2.96 ^ soc/wire4208/X (sky130_fd_sc_hd__buf_6)
+ 2 0.08 soc/net4208 (net)
+ 0.17 0.02 2.98 ^ soc/_32597_/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.15 0.18 3.15 ^ soc/_32597_/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 soc/net216 (net)
+ 0.15 0.00 3.16 ^ soc/output216/A (sky130_fd_sc_hd__buf_12)
+ 0.02 0.11 3.26 ^ soc/output216/X (sky130_fd_sc_hd__buf_12)
+ 2 0.00 clk_passthru (net)
+ 0.02 0.00 3.26 ^ mgmt_buffers/input1/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.06 0.13 3.39 ^ mgmt_buffers/input1/X (sky130_fd_sc_hd__clkbuf_4)
+ 1 0.01 mgmt_buffers/net1 (net)
+ 0.06 0.00 3.39 ^ mgmt_buffers/_296_/B (sky130_fd_sc_hd__and2_4)
+ 0.13 0.20 3.59 ^ mgmt_buffers/_296_/X (sky130_fd_sc_hd__and2_4)
+ 2 0.04 mgmt_buffers/net955 (net)
+ 0.13 0.00 3.60 ^ mgmt_buffers/wire1455/A (sky130_fd_sc_hd__buf_6)
+ 0.12 0.18 3.77 ^ mgmt_buffers/wire1455/X (sky130_fd_sc_hd__buf_6)
+ 2 0.06 mgmt_buffers/net1455 (net)
+ 0.12 0.01 3.78 ^ mgmt_buffers/wire1454/A (sky130_fd_sc_hd__buf_6)
+ 0.13 0.18 3.96 ^ mgmt_buffers/wire1454/X (sky130_fd_sc_hd__buf_6)
+ 2 0.06 mgmt_buffers/net1454 (net)
+ 0.13 0.01 3.97 ^ mgmt_buffers/wire1453/A (sky130_fd_sc_hd__buf_6)
+ 0.10 0.16 4.13 ^ mgmt_buffers/wire1453/X (sky130_fd_sc_hd__buf_6)
+ 2 0.05 mgmt_buffers/net1453 (net)
+ 0.10 0.01 4.14 ^ mgmt_buffers/output955/A (sky130_fd_sc_hd__buf_8)
+ 0.02 0.09 4.23 ^ mgmt_buffers/output955/X (sky130_fd_sc_hd__buf_8)
+ 2 0.00 mprj_clock (net)
+ 0.02 0.00 4.23 ^ mprj/u_rp_south/u_rp[0].u_buf/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.30 0.27 4.50 ^ mprj/u_rp_south/u_rp[0].u_buf/X (sky130_fd_sc_hd__clkbuf_4)
+ 2 0.10 mprj/u_rp_south/net100 (net)
+ 0.30 0.03 4.54 ^ mprj/u_rp_south/wire100/A (sky130_fd_sc_hd__buf_6)
+ 0.52 0.37 4.91 ^ mprj/u_rp_south/wire100/X (sky130_fd_sc_hd__buf_6)
+ 2 0.27 mprj/ch_out_south[0] (net)
+ 0.65 0.20 5.11 ^ mprj/u_wb_host/wire1/A (sky130_fd_sc_hd__buf_2)
+ 0.22 0.35 5.45 ^ mprj/u_wb_host/wire1/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/u_wb_host/net852 (net)
+ 0.22 0.01 5.46 ^ mprj/u_wb_host/clkbuf_0_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.06 0.19 5.65 ^ mprj/u_wb_host/clkbuf_0_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 4 0.04 mprj/u_wb_host/clknet_0_wbm_clk_i (net)
+ 0.06 0.00 5.65 ^ mprj/u_wb_host/clkbuf_1_1_0_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.06 0.14 5.79 ^ mprj/u_wb_host/clkbuf_1_1_0_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_8)
+ 4 0.03 mprj/u_wb_host/clknet_1_1_0_wbm_clk_i (net)
+ 0.06 0.00 5.79 ^ mprj/u_wb_host/clkbuf_2_2_0_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.06 0.14 5.92 ^ mprj/u_wb_host/clkbuf_2_2_0_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_8)
+ 2 0.02 mprj/u_wb_host/clknet_2_2_0_wbm_clk_i (net)
+ 0.06 0.00 5.92 ^ mprj/u_wb_host/clkbuf_3_4_0_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.19 0.23 6.16 ^ mprj/u_wb_host/clkbuf_3_4_0_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_8)
+ 16 0.11 mprj/u_wb_host/clknet_3_4_0_wbm_clk_i (net)
+ 0.19 0.00 6.16 ^ mprj/u_wb_host/clkbuf_leaf_48_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.06 0.18 6.34 ^ mprj/u_wb_host/clkbuf_leaf_48_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 11 0.04 mprj/u_wb_host/clknet_leaf_48_wbm_clk_i (net)
+ 0.06 0.00 6.34 ^ mprj/u_wb_host/_5949_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.04 0.30 6.65 ^ mprj/u_wb_host/_5949_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_arb.rstn (net)
+ 0.04 0.00 6.65 ^ mprj/u_wb_host/hold4/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.13 0.58 7.23 ^ mprj/u_wb_host/hold4/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 2 0.01 mprj/u_wb_host/net858 (net)
+ 0.13 0.00 7.23 ^ mprj/u_wb_host/fanout653/A (sky130_fd_sc_hd__buf_8)
+ 0.20 0.23 7.45 ^ mprj/u_wb_host/fanout653/X (sky130_fd_sc_hd__buf_8)
+ 14 0.13 mprj/u_wb_host/net653 (net)
+ 0.21 0.01 7.46 ^ mprj/u_wb_host/_5843_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
+ 7.46 data arrival time
- 0.00 0.00 clock uart_clk (rise edge)
+ 0.00 0.00 clock wb_clk (rise edge)
0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.18 0.18 ^ mprj/u_wb_host/_6348_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.28 clock uncertainty
- 0.00 0.28 clock reconvergence pessimism
- 0.76 1.03 library removal time
- 1.03 data required time
+ 4.00 0.00 0.00 ^ clock (in)
+ 1 1.12 clock (net)
+ 4.00 0.00 0.00 ^ padframe/clock_pad/PAD (sky130_ef_io__gpiov2_pad_wrapped)
+ 0 1.12 clock (net)
+ 0.07 2.19 2.19 ^ padframe/clock_pad/IN (sky130_ef_io__gpiov2_pad_wrapped)
+ 1 0.00 clock_core (net)
+ 0.07 0.00 2.19 ^ flash_clkrst_buffers/BUF[2]/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.04 0.13 2.32 ^ flash_clkrst_buffers/BUF[2]/X (sky130_fd_sc_hd__clkbuf_8)
+ 4 0.01 clock_core_buf (net)
+ 0.04 0.00 2.32 ^ clock_ctrl/clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.13 2.45 ^ clock_ctrl/clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
+ 2 0.02 clock_ctrl/clknet_0_ext_clk (net)
+ 0.04 0.00 2.45 ^ clock_ctrl/clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.11 2.56 ^ clock_ctrl/clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 clock_ctrl/clknet_1_1__leaf_ext_clk (net)
+ 0.03 0.00 2.56 ^ clock_ctrl/_205_/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.10 0.16 2.72 ^ clock_ctrl/_205_/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 clock_ctrl/_037_ (net)
+ 0.10 0.00 2.72 ^ clock_ctrl/clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.15 2.87 ^ clock_ctrl/clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
+ 2 0.02 clock_ctrl/clknet_0__037_ (net)
+ 0.04 0.00 2.87 ^ clock_ctrl/clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.11 2.98 ^ clock_ctrl/clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 clock_ctrl/clknet_1_0__leaf__037_ (net)
+ 0.03 0.00 2.98 ^ clock_ctrl/_206_/A0 (sky130_fd_sc_hd__mux2_1)
+ 0.09 0.15 3.14 ^ clock_ctrl/_206_/X (sky130_fd_sc_hd__mux2_1)
+ 1 0.01 clock_ctrl/net10 (net)
+ 0.09 0.00 3.14 ^ clock_ctrl/clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.15 3.28 ^ clock_ctrl/clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
+ 2 0.02 clock_ctrl/clknet_0_net10 (net)
+ 0.04 0.00 3.28 ^ clock_ctrl/clkbuf_1_0__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.05 0.13 3.41 ^ clock_ctrl/clkbuf_1_0__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
+ 4 0.02 caravel_clk (net)
+ 0.05 0.00 3.41 ^ flash_clkrst_buffers/BUF[14]/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.04 0.13 3.54 ^ flash_clkrst_buffers/BUF[14]/X (sky130_fd_sc_hd__clkbuf_8)
+ 4 0.01 caravel_clk_buf (net)
+ 0.04 0.00 3.54 ^ soc/input1/A (sky130_fd_sc_hd__buf_6)
+ 0.13 0.16 3.71 ^ soc/input1/X (sky130_fd_sc_hd__buf_6)
+ 2 0.06 soc/net1 (net)
+ 0.13 0.01 3.72 ^ soc/wire4208/A (sky130_fd_sc_hd__buf_6)
+ 0.17 0.22 3.94 ^ soc/wire4208/X (sky130_fd_sc_hd__buf_6)
+ 2 0.08 soc/net4208 (net)
+ 0.17 0.02 3.96 ^ soc/_32597_/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.15 0.19 4.15 ^ soc/_32597_/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 soc/net216 (net)
+ 0.15 0.00 4.15 ^ soc/output216/A (sky130_fd_sc_hd__buf_12)
+ 0.02 0.11 4.27 ^ soc/output216/X (sky130_fd_sc_hd__buf_12)
+ 2 0.00 clk_passthru (net)
+ 0.02 0.00 4.27 ^ mgmt_buffers/input1/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.06 0.14 4.40 ^ mgmt_buffers/input1/X (sky130_fd_sc_hd__clkbuf_4)
+ 1 0.01 mgmt_buffers/net1 (net)
+ 0.06 0.00 4.40 ^ mgmt_buffers/_296_/B (sky130_fd_sc_hd__and2_4)
+ 0.13 0.22 4.62 ^ mgmt_buffers/_296_/X (sky130_fd_sc_hd__and2_4)
+ 2 0.04 mgmt_buffers/net955 (net)
+ 0.13 0.00 4.63 ^ mgmt_buffers/wire1455/A (sky130_fd_sc_hd__buf_6)
+ 0.12 0.19 4.82 ^ mgmt_buffers/wire1455/X (sky130_fd_sc_hd__buf_6)
+ 2 0.06 mgmt_buffers/net1455 (net)
+ 0.12 0.01 4.83 ^ mgmt_buffers/wire1454/A (sky130_fd_sc_hd__buf_6)
+ 0.13 0.19 5.02 ^ mgmt_buffers/wire1454/X (sky130_fd_sc_hd__buf_6)
+ 2 0.06 mgmt_buffers/net1454 (net)
+ 0.13 0.01 5.03 ^ mgmt_buffers/wire1453/A (sky130_fd_sc_hd__buf_6)
+ 0.10 0.17 5.20 ^ mgmt_buffers/wire1453/X (sky130_fd_sc_hd__buf_6)
+ 2 0.05 mgmt_buffers/net1453 (net)
+ 0.10 0.01 5.21 ^ mgmt_buffers/output955/A (sky130_fd_sc_hd__buf_8)
+ 0.02 0.10 5.31 ^ mgmt_buffers/output955/X (sky130_fd_sc_hd__buf_8)
+ 2 0.00 mprj_clock (net)
+ 0.02 0.00 5.31 ^ mprj/u_rp_south/u_rp[0].u_buf/A (sky130_fd_sc_hd__clkbuf_4)
+ 0.30 0.30 5.61 ^ mprj/u_rp_south/u_rp[0].u_buf/X (sky130_fd_sc_hd__clkbuf_4)
+ 2 0.10 mprj/u_rp_south/net100 (net)
+ 0.30 0.03 5.64 ^ mprj/u_rp_south/wire100/A (sky130_fd_sc_hd__buf_6)
+ 0.52 0.40 6.04 ^ mprj/u_rp_south/wire100/X (sky130_fd_sc_hd__buf_6)
+ 2 0.27 mprj/ch_out_south[0] (net)
+ 0.65 0.21 6.26 ^ mprj/u_wb_host/wire1/A (sky130_fd_sc_hd__buf_2)
+ 0.22 0.37 6.63 ^ mprj/u_wb_host/wire1/X (sky130_fd_sc_hd__buf_2)
+ 2 0.04 mprj/u_wb_host/net852 (net)
+ 0.22 0.01 6.63 ^ mprj/u_wb_host/clkbuf_0_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.06 0.20 6.84 ^ mprj/u_wb_host/clkbuf_0_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 4 0.04 mprj/u_wb_host/clknet_0_wbm_clk_i (net)
+ 0.06 0.00 6.84 ^ mprj/u_wb_host/clkbuf_1_1_0_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.06 0.15 6.99 ^ mprj/u_wb_host/clkbuf_1_1_0_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_8)
+ 4 0.03 mprj/u_wb_host/clknet_1_1_0_wbm_clk_i (net)
+ 0.06 0.00 6.99 ^ mprj/u_wb_host/clkbuf_2_2_0_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.06 0.15 7.14 ^ mprj/u_wb_host/clkbuf_2_2_0_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_8)
+ 2 0.02 mprj/u_wb_host/clknet_2_2_0_wbm_clk_i (net)
+ 0.06 0.00 7.14 ^ mprj/u_wb_host/clkbuf_3_5_0_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.16 0.23 7.36 ^ mprj/u_wb_host/clkbuf_3_5_0_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_8)
+ 10 0.09 mprj/u_wb_host/clknet_3_5_0_wbm_clk_i (net)
+ 0.16 0.00 7.36 ^ mprj/u_wb_host/clkbuf_leaf_45_wbm_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.17 7.53 ^ mprj/u_wb_host/clkbuf_leaf_45_wbm_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
+ 5 0.02 mprj/u_wb_host/clknet_leaf_45_wbm_clk_i (net)
+ 0.04 0.00 7.54 ^ mprj/u_wb_host/_5843_/CLK (sky130_fd_sc_hd__dfrtp_4)
+ 0.10 7.64 clock uncertainty
+ -1.21 6.42 clock reconvergence pessimism
+ 0.36 6.79 library removal time
+ 6.79 data required time
-----------------------------------------------------------------------------
- 1.03 data required time
- -1.15 data arrival time
+ 6.79 data required time
+ -7.46 data arrival time
-----------------------------------------------------------------------------
- 0.11 slack (MET)
+ 0.67 slack (MET)
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6522_
- (removal check against rising-edge clock uart_clk)
-Path Group: **async_default**
-Path Type: min
-
-Fanout Cap Slew Delay Time Description
------------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.16 ^ mprj/u_wb_host/_6522_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.16 data arrival time
-
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.18 0.18 ^ mprj/u_wb_host/_6522_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.28 clock uncertainty
- 0.00 0.28 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
------------------------------------------------------------------------------
- 1.04 data required time
- -1.16 data arrival time
------------------------------------------------------------------------------
- 0.12 slack (MET)
-
-
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6345_
- (removal check against rising-edge clock uart_clk)
-Path Group: **async_default**
-Path Type: min
-
-Fanout Cap Slew Delay Time Description
------------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.16 ^ mprj/u_wb_host/_6345_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.16 data arrival time
-
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.18 0.18 ^ mprj/u_wb_host/_6345_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.28 clock uncertainty
- 0.00 0.28 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
------------------------------------------------------------------------------
- 1.04 data required time
- -1.16 data arrival time
------------------------------------------------------------------------------
- 0.12 slack (MET)
-
-
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6427_
- (removal check against rising-edge clock uart_clk)
-Path Group: **async_default**
-Path Type: min
-
-Fanout Cap Slew Delay Time Description
------------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.16 ^ mprj/u_wb_host/_6427_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.16 data arrival time
-
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.18 0.18 ^ mprj/u_wb_host/_6427_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.28 clock uncertainty
- 0.00 0.28 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
------------------------------------------------------------------------------
- 1.04 data required time
- -1.16 data arrival time
------------------------------------------------------------------------------
- 0.12 slack (MET)
-
-
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6350_
- (removal check against rising-edge clock uart_clk)
-Path Group: **async_default**
-Path Type: min
-
-Fanout Cap Slew Delay Time Description
------------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.16 ^ mprj/u_wb_host/_6350_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.16 data arrival time
-
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.18 0.18 ^ mprj/u_wb_host/_6350_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.28 clock uncertainty
- 0.00 0.28 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
------------------------------------------------------------------------------
- 1.04 data required time
- -1.16 data arrival time
------------------------------------------------------------------------------
- 0.12 slack (MET)
-
-
-Startpoint: mprj/u_wb_host/_6420_
- (rising edge-triggered flip-flop clocked by uart_clk)
-Endpoint: mprj/u_wb_host/_6347_
- (removal check against rising-edge clock uart_clk)
-Path Group: **async_default**
-Path Type: min
-
-Fanout Cap Slew Delay Time Description
------------------------------------------------------------------------------
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.16 0.16 ^ mprj/u_wb_host/_6420_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.43 0.98 1.14 ^ mprj/u_wb_host/_6420_/Q (sky130_fd_sc_hd__dfrtp_4)
- 46 0.15 mprj/u_wb_host/u_uart2wb.line_reset_n (net)
- 0.43 0.01 1.16 ^ mprj/u_wb_host/_6347_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
- 1.16 data arrival time
-
- 0.00 0.00 clock uart_clk (rise edge)
- 0.00 0.00 clock source latency
- 2.27 0.00 0.00 ^ mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_8)
- 576 1.41 mprj/u_wb_host/u_uart2wb.baud_clk_16x (net)
- 2.29 0.18 0.18 ^ mprj/u_wb_host/_6347_/CLK (sky130_fd_sc_hd__dfrtp_1)
- 0.10 0.28 clock uncertainty
- 0.00 0.28 clock reconvergence pessimism
- 0.76 1.04 library removal time
- 1.04 data required time
------------------------------------------------------------------------------
- 1.04 data required time
- -1.16 data arrival time
------------------------------------------------------------------------------
- 0.12 slack (MET)
-
-
-Startpoint: mprj/u_wb_host/_5883_
+Startpoint: mprj/u_wb_host/_5877_
(rising edge-triggered flip-flop clocked by lbist_clk)
-Endpoint: mprj/u_wb_host/_5713_
+Endpoint: mprj/u_wb_host/_5669_
(removal check against rising-edge clock lbist_clk)
Path Group: **async_default**
Path Type: min
@@ -1071,115 +3430,154 @@
0.04 0.00 0.00 ^ mprj/u_wb_host/clkbuf_0_u_lbist.lbist_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 mprj/u_wb_host/clknet_0_u_lbist.lbist_clk (net)
0.04 0.00 0.00 ^ mprj/u_wb_host/clkbuf_1_0__f_u_lbist.lbist_clk/A (sky130_fd_sc_hd__clkbuf_16)
- 0.04 0.12 0.12 ^ mprj/u_wb_host/clkbuf_1_0__f_u_lbist.lbist_clk/X (sky130_fd_sc_hd__clkbuf_16)
- 2 0.02 mprj/u_wb_host/clknet_1_0__leaf_u_lbist.lbist_clk (net)
- 0.04 0.00 0.12 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
- 0.08 0.21 0.33 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
+ 0.04 0.11 0.11 ^ mprj/u_wb_host/clkbuf_1_0__f_u_lbist.lbist_clk/X (sky130_fd_sc_hd__clkbuf_16)
+ 2 0.01 mprj/u_wb_host/clknet_1_0__leaf_u_lbist.lbist_clk (net)
+ 0.04 0.00 0.12 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.07 0.19 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_lbist.clkbuf_1.X1 (net)
+ 0.04 0.00 0.19 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.14 0.14 0.33 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
1 0.01 mprj/u_wb_host/u_skew_lbist.clk_d1 (net)
- 0.08 0.00 0.33 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d1/A (sky130_fd_sc_hd__clkbuf_16)
- 0.04 0.13 0.46 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d1/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.14 0.00 0.33 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d1/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.16 0.49 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d1/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 mprj/u_wb_host/clknet_0_u_skew_lbist.clk_d1 (net)
- 0.04 0.00 0.46 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d1/A (sky130_fd_sc_hd__clkbuf_16)
- 0.03 0.10 0.57 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d1/X (sky130_fd_sc_hd__clkbuf_16)
- 1 0.00 mprj/u_wb_host/clknet_1_0__leaf_u_skew_lbist.clk_d1 (net)
- 0.03 0.00 0.57 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_2/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
- 0.07 0.20 0.77 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_2/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
+ 0.04 0.00 0.49 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d1/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.11 0.60 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d1/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.01 mprj/u_wb_host/clknet_1_0__leaf_u_skew_lbist.clk_d1 (net)
+ 0.03 0.00 0.60 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_2.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.06 0.08 0.68 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_2.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_lbist.clkbuf_2.X1 (net)
+ 0.06 0.00 0.68 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_2.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.17 0.17 0.85 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_2.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
1 0.01 mprj/u_wb_host/u_skew_lbist.clk_d2 (net)
- 0.07 0.00 0.77 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d2/A (sky130_fd_sc_hd__clkbuf_16)
- 0.04 0.13 0.90 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d2/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.17 0.00 0.85 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d2/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.16 1.01 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d2/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 mprj/u_wb_host/clknet_0_u_skew_lbist.clk_d2 (net)
- 0.04 0.00 0.90 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d2/A (sky130_fd_sc_hd__clkbuf_16)
- 0.03 0.10 1.00 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d2/X (sky130_fd_sc_hd__clkbuf_16)
- 1 0.00 mprj/u_wb_host/clknet_1_0__leaf_u_skew_lbist.clk_d2 (net)
- 0.03 0.00 1.00 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_3/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
- 0.07 0.20 1.20 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_3/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
+ 0.04 0.00 1.01 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d2/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.10 1.11 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d2/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 mprj/u_wb_host/clknet_1_1__leaf_u_skew_lbist.clk_d2 (net)
+ 0.03 0.00 1.11 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_3.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.09 1.21 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_3.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_lbist.clkbuf_3.X1 (net)
+ 0.08 0.00 1.21 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_3.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.15 0.16 1.37 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_3.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
1 0.01 mprj/u_wb_host/u_skew_lbist.clk_d3 (net)
- 0.07 0.00 1.20 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d3/A (sky130_fd_sc_hd__clkbuf_16)
- 0.04 0.13 1.34 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d3/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.15 0.00 1.37 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d3/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.15 1.52 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d3/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 mprj/u_wb_host/clknet_0_u_skew_lbist.clk_d3 (net)
- 0.04 0.00 1.34 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d3/A (sky130_fd_sc_hd__clkbuf_16)
- 0.03 0.11 1.44 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d3/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.00 1.52 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d3/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.11 1.63 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d3/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 mprj/u_wb_host/clknet_1_1__leaf_u_skew_lbist.clk_d3 (net)
- 0.03 0.00 1.44 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_4/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
- 0.07 0.20 1.64 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_4/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
+ 0.03 0.00 1.63 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_4.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.07 0.09 1.72 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_4.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_lbist.clkbuf_4.X1 (net)
+ 0.07 0.00 1.72 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_4.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.15 0.16 1.88 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_4.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
1 0.01 mprj/u_wb_host/u_skew_lbist.clk_d4 (net)
- 0.07 0.00 1.64 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d4/A (sky130_fd_sc_hd__clkbuf_16)
- 0.04 0.13 1.77 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d4/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.15 0.00 1.88 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d4/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.16 2.04 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d4/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 mprj/u_wb_host/clknet_0_u_skew_lbist.clk_d4 (net)
- 0.04 0.00 1.77 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d4/A (sky130_fd_sc_hd__clkbuf_16)
- 0.03 0.10 1.88 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d4/X (sky130_fd_sc_hd__clkbuf_16)
- 1 0.00 mprj/u_wb_host/clknet_1_0__leaf_u_skew_lbist.clk_d4 (net)
- 0.03 0.00 1.88 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_5/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
- 0.06 0.20 2.07 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_5/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
+ 0.04 0.00 2.04 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d4/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.11 2.14 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d4/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.01 mprj/u_wb_host/clknet_1_1__leaf_u_skew_lbist.clk_d4 (net)
+ 0.03 0.00 2.14 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_5.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.13 2.27 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_5.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_lbist.clkbuf_5.X1 (net)
+ 0.13 0.00 2.27 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_5.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.16 2.43 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_5.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
1 0.01 mprj/u_wb_host/u_skew_lbist.clk_d5 (net)
- 0.06 0.00 2.07 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d5/A (sky130_fd_sc_hd__clkbuf_16)
- 0.04 0.13 2.20 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d5/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.13 0.00 2.43 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d5/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.15 2.59 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d5/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 mprj/u_wb_host/clknet_0_u_skew_lbist.clk_d5 (net)
- 0.04 0.00 2.20 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d5/A (sky130_fd_sc_hd__clkbuf_16)
- 0.03 0.11 2.31 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d5/X (sky130_fd_sc_hd__clkbuf_16)
- 1 0.00 mprj/u_wb_host/clknet_1_1__leaf_u_skew_lbist.clk_d5 (net)
- 0.03 0.00 2.31 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_6/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
- 0.06 0.20 2.50 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_6/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
+ 0.04 0.00 2.59 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d5/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.11 2.69 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d5/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.01 mprj/u_wb_host/clknet_1_1__leaf_u_skew_lbist.clk_d5 (net)
+ 0.03 0.00 2.69 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_6.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.13 2.82 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_6.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_lbist.clkbuf_6.X1 (net)
+ 0.13 0.00 2.82 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_6.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.16 2.98 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_6.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
1 0.01 mprj/u_wb_host/u_skew_lbist.clk_d6 (net)
- 0.06 0.00 2.50 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d6/A (sky130_fd_sc_hd__clkbuf_16)
- 0.04 0.13 2.63 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d6/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.13 0.00 2.98 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d6/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.15 3.13 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d6/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 mprj/u_wb_host/clknet_0_u_skew_lbist.clk_d6 (net)
- 0.04 0.00 2.63 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d6/A (sky130_fd_sc_hd__clkbuf_16)
- 0.03 0.11 2.74 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d6/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.00 3.13 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d6/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.11 3.24 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d6/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 mprj/u_wb_host/clknet_1_0__leaf_u_skew_lbist.clk_d6 (net)
- 0.03 0.00 2.74 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_7/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
- 0.06 0.20 2.94 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_7/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
+ 0.03 0.00 3.24 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_7.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.05 0.08 3.32 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_7.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.00 mprj/u_wb_host/u_skew_lbist.clkbuf_7.X1 (net)
+ 0.05 0.00 3.32 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_7.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.13 0.14 3.45 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_7.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
1 0.01 mprj/u_wb_host/u_skew_lbist.clk_d7 (net)
- 0.06 0.00 2.94 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d7/A (sky130_fd_sc_hd__clkbuf_16)
- 0.04 0.13 3.06 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d7/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.13 0.00 3.45 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d7/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.15 3.60 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d7/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 mprj/u_wb_host/clknet_0_u_skew_lbist.clk_d7 (net)
- 0.04 0.00 3.06 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d7/A (sky130_fd_sc_hd__clkbuf_16)
- 0.03 0.10 3.17 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d7/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.00 3.60 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d7/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.10 3.71 ^ mprj/u_wb_host/clkbuf_1_1__f_u_skew_lbist.clk_d7/X (sky130_fd_sc_hd__clkbuf_16)
1 0.00 mprj/u_wb_host/clknet_1_1__leaf_u_skew_lbist.clk_d7 (net)
- 0.03 0.00 3.17 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_8/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
- 0.06 0.19 3.36 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_8/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
+ 0.03 0.00 3.71 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_8.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.08 0.10 3.80 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_8.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
+ 1 0.01 mprj/u_wb_host/u_skew_lbist.clkbuf_8.X1 (net)
+ 0.08 0.00 3.81 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_8.u_dly1/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.12 0.14 3.94 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_8.u_dly1/X (sky130_fd_sc_hd__clkbuf_1)
1 0.01 mprj/u_wb_host/u_skew_lbist.clk_d8 (net)
- 0.06 0.00 3.36 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d8/A (sky130_fd_sc_hd__clkbuf_16)
- 0.04 0.12 3.49 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d8/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.12 0.00 3.94 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d8/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.15 4.09 ^ mprj/u_wb_host/clkbuf_0_u_skew_lbist.clk_d8/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 mprj/u_wb_host/clknet_0_u_skew_lbist.clk_d8 (net)
- 0.04 0.00 3.49 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d8/A (sky130_fd_sc_hd__clkbuf_16)
- 0.03 0.11 3.59 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d8/X (sky130_fd_sc_hd__clkbuf_16)
- 1 0.01 mprj/u_wb_host/clknet_1_0__leaf_u_skew_lbist.clk_d8 (net)
- 0.03 0.00 3.59 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_04/A0 (sky130_fd_sc_hd__mux2_1)
- 0.07 0.13 3.72 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_04/X (sky130_fd_sc_hd__mux2_1)
+ 0.04 0.00 4.09 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d8/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.03 0.11 4.19 ^ mprj/u_wb_host/clkbuf_1_0__f_u_skew_lbist.clk_d8/X (sky130_fd_sc_hd__clkbuf_16)
+ 1 0.00 mprj/u_wb_host/clknet_1_0__leaf_u_skew_lbist.clk_d8 (net)
+ 0.03 0.00 4.19 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_04.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_2)
+ 0.05 0.14 4.33 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_04.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_2)
1 0.01 mprj/u_wb_host/u_skew_lbist.d04 (net)
- 0.07 0.00 3.72 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_12/A0 (sky130_fd_sc_hd__mux2_1)
- 0.06 0.13 3.85 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_12/X (sky130_fd_sc_hd__mux2_1)
- 1 0.01 mprj/u_wb_host/u_skew_lbist.d12 (net)
- 0.06 0.00 3.85 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_21/A0 (sky130_fd_sc_hd__mux2_1)
- 0.05 0.12 3.98 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_21/X (sky130_fd_sc_hd__mux2_1)
+ 0.05 0.00 4.33 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_12.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_2)
+ 0.05 0.14 4.47 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_12.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_2)
+ 1 0.00 mprj/u_wb_host/u_skew_lbist.d12 (net)
+ 0.05 0.00 4.47 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_21.genblk1.u_mux/A0 (sky130_fd_sc_hd__mux2_2)
+ 0.04 0.13 4.61 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_21.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_2)
1 0.00 mprj/u_wb_host/u_skew_lbist.d21 (net)
- 0.05 0.00 3.98 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_30/A1 (sky130_fd_sc_hd__mux2_4)
- 0.04 0.13 4.11 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_30/X (sky130_fd_sc_hd__mux2_4)
- 1 0.00 mprj/u_wb_host/net208 (net)
- 0.04 0.00 4.11 ^ mprj/u_wb_host/output208/A (sky130_fd_sc_hd__clkbuf_1)
- 0.88 0.62 4.73 ^ mprj/u_wb_host/output208/X (sky130_fd_sc_hd__clkbuf_1)
- 2 0.08 mprj/lbist_clk (net)
- 0.88 0.01 4.74 ^ mprj/u_wb_host/clkbuf_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_16)
- 0.08 0.29 5.03 ^ mprj/u_wb_host/clkbuf_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_16)
+ 0.04 0.00 4.61 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_30.genblk1.u_mux/A1 (sky130_fd_sc_hd__mux2_4)
+ 0.04 0.13 4.74 ^ mprj/u_wb_host/u_skew_lbist.u_mux_level_30.genblk1.u_mux/X (sky130_fd_sc_hd__mux2_4)
+ 1 0.01 mprj/u_wb_host/net208 (net)
+ 0.04 0.00 4.74 ^ mprj/u_wb_host/output208/A (sky130_fd_sc_hd__buf_6)
+ 0.09 0.13 4.87 ^ mprj/u_wb_host/output208/X (sky130_fd_sc_hd__buf_6)
+ 2 0.04 mprj/lbist_clk (net)
+ 0.09 0.00 4.87 ^ mprj/u_wb_host/wire3/A (sky130_fd_sc_hd__buf_2)
+ 0.24 0.25 5.12 ^ mprj/u_wb_host/wire3/X (sky130_fd_sc_hd__buf_2)
+ 2 0.05 mprj/u_wb_host/net854 (net)
+ 0.24 0.00 5.12 ^ mprj/u_wb_host/clkbuf_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_16)
+ 0.06 0.19 5.32 ^ mprj/u_wb_host/clkbuf_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_16)
4 0.04 mprj/u_wb_host/clknet_0_lbist_clk_int (net)
- 0.08 0.00 5.03 ^ mprj/u_wb_host/clkbuf_1_1_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_8)
- 0.05 0.13 5.17 ^ mprj/u_wb_host/clkbuf_1_1_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_8)
- 2 0.02 mprj/u_wb_host/clknet_1_1_0_lbist_clk_int (net)
- 0.05 0.00 5.17 ^ mprj/u_wb_host/clkbuf_2_3_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_8)
- 0.05 0.13 5.30 ^ mprj/u_wb_host/clkbuf_2_3_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_8)
+ 0.06 0.00 5.32 ^ mprj/u_wb_host/clkbuf_1_1_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.03 0.11 5.43 ^ mprj/u_wb_host/clkbuf_1_1_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_8)
+ 1 0.01 mprj/u_wb_host/clknet_1_1_0_lbist_clk_int (net)
+ 0.03 0.00 5.43 ^ mprj/u_wb_host/clkbuf_1_1_1_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.05 0.12 5.55 ^ mprj/u_wb_host/clkbuf_1_1_1_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_8)
+ 2 0.02 mprj/u_wb_host/clknet_1_1_1_lbist_clk_int (net)
+ 0.05 0.00 5.55 ^ mprj/u_wb_host/clkbuf_2_3_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.05 0.13 5.68 ^ mprj/u_wb_host/clkbuf_2_3_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_8)
2 0.02 mprj/u_wb_host/clknet_2_3_0_lbist_clk_int (net)
- 0.05 0.00 5.30 ^ mprj/u_wb_host/clkbuf_3_6_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_8)
- 0.04 0.12 5.41 ^ mprj/u_wb_host/clkbuf_3_6_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_8)
+ 0.05 0.00 5.68 ^ mprj/u_wb_host/clkbuf_3_6_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.04 0.12 5.80 ^ mprj/u_wb_host/clkbuf_3_6_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_8)
2 0.01 mprj/u_wb_host/clknet_3_6_0_lbist_clk_int (net)
- 0.04 0.00 5.41 ^ mprj/u_wb_host/clkbuf_4_13_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_8)
- 0.11 0.17 5.58 ^ mprj/u_wb_host/clkbuf_4_13_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_8)
- 22 0.06 mprj/u_wb_host/clknet_4_13_0_lbist_clk_int (net)
- 0.11 0.00 5.58 ^ mprj/u_wb_host/_5883_/CLK (sky130_fd_sc_hd__dfrtp_4)
- 0.32 0.61 6.19 ^ mprj/u_wb_host/_5883_/Q (sky130_fd_sc_hd__dfrtp_4)
- 28 0.11 mprj/u_wb_host/u_lbist.lbist_rst_n (net)
- 0.32 0.00 6.20 ^ mprj/u_wb_host/_5713_/SET_B (sky130_fd_sc_hd__dfstp_1)
- 6.20 data arrival time
+ 0.04 0.00 5.80 ^ mprj/u_wb_host/clkbuf_4_13_0_lbist_clk_int/A (sky130_fd_sc_hd__clkbuf_8)
+ 0.12 0.17 5.97 ^ mprj/u_wb_host/clkbuf_4_13_0_lbist_clk_int/X (sky130_fd_sc_hd__clkbuf_8)
+ 26 0.06 mprj/u_wb_host/clknet_4_13_0_lbist_clk_int (net)
+ 0.12 0.00 5.98 ^ mprj/u_wb_host/_5877_/CLK (sky130_fd_sc_hd__dfrtp_1)
+ 0.05 0.33 6.31 ^ mprj/u_wb_host/_5877_/Q (sky130_fd_sc_hd__dfrtp_1)
+ 1 0.00 mprj/u_wb_host/u_lbist.lbist_rst_n (net)
+ 0.05 0.00 6.31 ^ mprj/u_wb_host/hold7/A (sky130_fd_sc_hd__dlygate4sd3_1)
+ 0.05 0.51 6.82 ^ mprj/u_wb_host/hold7/X (sky130_fd_sc_hd__dlygate4sd3_1)
+ 1 0.00 mprj/u_wb_host/net861 (net)
+ 0.05 0.00 6.82 ^ mprj/u_wb_host/fanout679/A (sky130_fd_sc_hd__buf_2)
+ 0.23 0.23 7.06 ^ mprj/u_wb_host/fanout679/X (sky130_fd_sc_hd__buf_2)
+ 10 0.05 mprj/u_wb_host/net679 (net)
+ 0.23 0.00 7.06 ^ mprj/u_wb_host/fanout678/A (sky130_fd_sc_hd__buf_2)
+ 0.16 0.24 7.30 ^ mprj/u_wb_host/fanout678/X (sky130_fd_sc_hd__buf_2)
+ 6 0.03 mprj/u_wb_host/net678 (net)
+ 0.16 0.00 7.30 ^ mprj/u_wb_host/_5669_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
+ 7.30 data arrival time
0.00 0.00 clock lbist_clk (rise edge)
0.00 0.00 clock source latency
@@ -1187,7305 +3585,2702 @@
2 0.02 mprj/u_wb_host/clknet_0_u_lbist.lbist_clk (net)
0.04 0.00 0.00 ^ mprj/u_wb_host/clkbuf_1_0__f_u_lbist.lbist_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.12 0.12 ^ mprj/u_wb_host/clkbuf_1_0__f_u_lbist.lbist_clk/X (sky130_fd_sc_hd__clkbuf_16)
- 2 0.02 mprj/u_wb_host/clknet_1_0__leaf_u_lbist.lbist_clk (net)
- 0.04 0.00 0.13 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
- 0.08 0.23 0.35 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
+ 2 0.01 mprj/u_wb_host/clknet_1_0__leaf_u_lbist.lbist_clk (net)
+ 0.04 0.00 0.12 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1.u_dly0/A (sky130_fd_sc_hd__clkbuf_1)
+ 0.04 0.08 0.20 ^ mprj/u_wb_host/u_skew_lbist.clkbuf_1.u_dly0/X (sky130_fd_sc_hd__clkbuf_1)
