openlane/mac_wrapper/base.sdc

###############################################################################
# Created by write_sdc
# Thu Dec 22 09:17:52 2022
###############################################################################
current_design mac_wrapper
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name  app_clk -period 10.0000 [get_ports {app_clk}]
create_clock -name  phy_tx_clk -period 40.0000 [get_ports {phy_tx_clk}]
create_clock -name  phy_rx_clk -period 40.0000 [get_ports {phy_rx_clk}]
create_clock -name  mdio_clk -period 100.0000 [get_ports {mdio_clk}]

set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set_propagated_clock [all_clocks]


set ::env(SYNTH_TIMING_DERATE) 0.05
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]

set_clock_groups -name async_clock -asynchronous \
 -group [get_clocks {app_clk}]      \
 -group [get_clocks {phy_tx_clk}]     \
 -group [get_clocks {phy_rx_clk}]     \
 -group [get_clocks {mdio_clk}] \
 -comment {Async Clock group}

### ClkSkew Adjust
set_case_analysis 0 [get_ports {cfg_cska_mac[0]}]
set_case_analysis 0 [get_ports {cfg_cska_mac[1]}]
set_case_analysis 0 [get_ports {cfg_cska_mac[2]}]
set_case_analysis 0 [get_ports {cfg_cska_mac[3]}]

# Set max delay for clock skew
set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
set_max_delay   2 -to   [get_ports {wbd_clk_skew}]
set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_skew


set_false_path -from [get_ports {reset_n}]

########################################
# mdio Clock Domain
########################################
set_input_delay  -max 6.0000  -clock [get_clocks {mdio_clk}] -add_delay [get_ports {mdio_in}]
set_input_delay  -min -2.0000  -clock [get_clocks {mdio_clk}] -add_delay [get_ports {mdio_in}]


set_output_delay -max 6.0000 -clock [get_clocks {mdio_clk}] -add_delay [get_ports {mdio_out}]
set_output_delay -max 6.0000 -clock [get_clocks {mdio_clk}] -add_delay [get_ports {mdio_out_en}]
set_output_delay -min -2.0000 -clock [get_clocks {mdio_clk}] -add_delay [get_ports {mdio_out}]
set_output_delay -min -2.0000 -clock [get_clocks {mdio_clk}] -add_delay [get_ports {mdio_out_en}]

########################################
# phy_rx_clk Clock Domain
########################################
set_input_delay -max 20.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_crs}]
set_input_delay -max 20.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rx_dv}]
set_input_delay -max 20.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rx_er}]
set_input_delay -max 20.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rxd[*]}]

set_input_delay -min -2.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_crs}]
set_input_delay -min -2.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rx_dv}]
set_input_delay -min -2.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rx_er}]
set_input_delay -min -2.0000 -clock [get_clocks {phy_rx_clk}] -add_delay [get_ports {phy_rxd[*]}]


########################################
# phy_tx_clk Clock Domain
########################################

set_output_delay -max 20.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_en}]
set_output_delay -max 20.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_er}]
set_output_delay -max 20.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_txd[*]}]

set_output_delay -min -2.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_en}]
set_output_delay -min -2.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_tx_er}]
set_output_delay -min -2.0000 -clock [get_clocks {phy_tx_clk}] -add_delay [get_ports {phy_txd[*]}]

########################################
# APP Clock Domain
########################################
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_ack_i}]
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_dat_i[*]}]
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_ack_i}]
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_dat_i[*]}]
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_adr_i[*]}]
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_cyc_i}]
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_dat_i[*]}]
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_sel_i[*]}]
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_stb_i}]
set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_we_i}]

set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_ack_i}]
set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_dat_i[*]}]
set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_ack_i}]
set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_dat_i[*]}]
set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_adr_i[*]}]
set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_cyc_i}]
set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_dat_i[*]}]
set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_sel_i[*]}]
set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_stb_i}]
set_input_delay  -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_we_i}]

set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_adr_o[*]}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_cyc_o}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_dat_o[*]}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_sel_o[*]}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_stb_o}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_we_o}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_adr_o[*]}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_cyc_o}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_dat_o[*]}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_sel_o[*]}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_stb_o}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_we_o}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_ack_o}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_dat_o[*]}]

set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_adr_o[*]}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_cyc_o}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_dat_o[*]}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_sel_o[*]}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_stb_o}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_grx_we_o}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_adr_o[*]}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_cyc_o}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_dat_o[*]}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_sel_o[*]}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_stb_o}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbm_gtx_we_o}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_ack_o}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {wbs_grg_dat_o[*]}]

set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {cfg_rx_qbase_addr[*]}]
set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {cfg_tx_qbase_addr[*]}]

set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {cfg_rx_qbase_addr[*]}]
set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {cfg_tx_qbase_addr[*]}]

set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {mac_rx_qcnt_dec}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {mac_rx_qcnt_inc}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {mac_tx_qcnt_dec}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {mac_tx_qcnt_inc}]

set_input_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {mac_rx_qcnt_dec}]
set_input_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {mac_rx_qcnt_inc}]
set_input_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {mac_tx_qcnt_dec}]
set_input_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {mac_tx_qcnt_inc}]

###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {mdio_out}]
set_load -pin_load 0.0334 [get_ports {mdio_out_en}]
set_load -pin_load 0.0334 [get_ports {phy_tx_en}]
set_load -pin_load 0.0334 [get_ports {phy_tx_er}]
set_load -pin_load 0.0334 [get_ports {wbd_clk_skew}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_cyc_o}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_stb_o}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_we_o}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_cyc_o}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_stb_o}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_we_o}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_ack_o}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[9]}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[8]}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[7]}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[6]}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[5]}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[4]}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[3]}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[2]}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[1]}]
set_load -pin_load 0.0334 [get_ports {cfg_rx_qbase_addr[0]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[9]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[8]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[7]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[6]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[5]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[4]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[3]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[2]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[1]}]
set_load -pin_load 0.0334 [get_ports {cfg_tx_qbase_addr[0]}]
set_load -pin_load 0.0334 [get_ports {phy_txd[7]}]
set_load -pin_load 0.0334 [get_ports {phy_txd[6]}]
set_load -pin_load 0.0334 [get_ports {phy_txd[5]}]
set_load -pin_load 0.0334 [get_ports {phy_txd[4]}]
set_load -pin_load 0.0334 [get_ports {phy_txd[3]}]
set_load -pin_load 0.0334 [get_ports {phy_txd[2]}]
set_load -pin_load 0.0334 [get_ports {phy_txd[1]}]
set_load -pin_load 0.0334 [get_ports {phy_txd[0]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[15]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[14]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[13]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[12]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[11]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[10]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[9]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[8]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[7]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[6]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[5]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[4]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_adr_o[0]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_dat_o[0]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_sel_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_sel_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_sel_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbm_grx_sel_o[0]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[15]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[14]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[13]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[12]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[11]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[10]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[9]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[8]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[7]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[6]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[5]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[4]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_adr_o[0]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_dat_o[0]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_sel_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_sel_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_sel_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbm_gtx_sel_o[0]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbs_grg_dat_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {app_clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qcnt_dec}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_rx_qcnt_inc}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qcnt_dec}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mac_tx_qcnt_inc}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mdio_clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mdio_in}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_crs}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rx_clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rx_dv}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rx_er}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_tx_clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_ack_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_ack_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_stb_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_mac[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_mac[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_mac[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_mac[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rxd[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rxd[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rxd[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rxd[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rxd[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rxd[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rxd[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {phy_rxd[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_grx_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_gtx_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_grg_sel_i[0]}]
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 10.0000 [current_design]