Add submodule

.gitmodules

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..7fa816d
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "verilog/rtl/leorv-fpga"]
+	path = verilog/rtl/leorv-fpga
+	url = git@codeberg.org:mole99/leorv32-fpga.git

verilog/rtl/leorv-fpga

diff --git a/verilog/rtl/leorv-fpga b/verilog/rtl/leorv-fpga
new file mode 160000
index 0000000..28cec17
--- /dev/null
+++ b/verilog/rtl/leorv-fpga
@@ -0,0 +1 @@
+Subproject commit 28cec1753d7f99b702b8869a70b130cac502e77e