openlane/soc/config.json

{
    "DESIGN_NAME": "soc",
    "DESIGN_IS_CORE": false,
    "FP_PDN_CORE_RING": false,
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/leorv-fpga/soc/rtl/dual_soc_svga.sv",
        "dir::../../verilog/rtl/leorv-fpga/sram/rtl/sram.sv",
        "dir::../../verilog/rtl/leorv-fpga/svga/rtl/svga_gen.sv",
        "dir::../../verilog/rtl/leorv-fpga/svga/rtl/svga_gen_top.sv",
        "dir::../../verilog/rtl/leorv-fpga/uart/rtl/my_uart_rx.sv",
        "dir::../../verilog/rtl/leorv-fpga/uart/rtl/my_uart_tx.sv",
        "dir::../../verilog/rtl/leorv-fpga/util/rtl/synchronizer.sv"
    ],
    "CLOCK_PORT": "clk",
    "FP_PDN_MACRO_HOOKS": [
        "leorv32_core0 vccd1 vssd1 vccd1 vssd1,",
        "leorv32_core1 vccd1 vssd1 vccd1 vssd1"
    ],
    "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
    "VERILOG_FILES_BLACKBOX": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/gl/leorv32.v",
        "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
    ],
    "EXTRA_LEFS": [
        "dir::../../lef/leorv32.lef",
        "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef"
    ],
    "EXTRA_GDS_FILES": [
        "dir::../../gds/leorv32.gds",
        "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds"
    ],
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 2350 1400",
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "PL_BASIC_PLACEMENT": 0,
    "PL_TARGET_DENSITY": 0.55,
    "VDD_NETS": ["vccd1"],
    "GND_NETS": ["vssd1"],
    "DIODE_INSERTION_STRATEGY": 4,
    "RUN_CVC": 1,
    "pdk::sky130*": {
        "FP_CORE_UTIL": 45,
        "RT_MAX_LAYER": "met4",
        "CLOCK_PERIOD": 20
    },
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "CLOCK_PERIOD": 24.0,
        "FP_CORE_UTIL": 40,
        "RT_MAX_LAYER": "Metal4",
        "SYNTH_MAX_FANOUT": 4,
        "PL_TARGET_DENSITY": 0.45
    },
    
    "LVS_CONNECT_BY_LABEL": 1,
    "MAGIC_DRC_USE_GDS": 0,
    "RUN_MAGIC_DRC": 0,
    "QUIT_ON_MAGIC_DRC": 0,
    "RUN_KLAYOUT_XOR": 0,
    "ROUTING_CORES": 6,
    "FP_PDN_VWIDTH": 3.1,
    "FP_PDN_HWIDTH": 3.1,
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "FP_PDN_VPITCH": 180,
    "FP_PDN_HPITCH": 180,
    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_VWIDTH)",
    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_HWIDTH)"
}