.gitmodules

[submodule "verilog/rtl/usb_cdc"]
	path = verilog/rtl/usb_cdc
	url = https://github.com/ulixxe/usb_cdc
[submodule "verilog/rtl/verilog-uart"]
	path = verilog/rtl/verilog-uart
	url = https://github.com/alexforencich/verilog-uart