add usb2uart test and fix io_in
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 43a4149..cc97ad8 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -20,7 +20,7 @@
.SILENT: clean all
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
+PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus usb2uart
all: ${PATTERNS}
diff --git a/verilog/dv/usb2uart/Makefile b/verilog/dv/usb2uart/Makefile
new file mode 100644
index 0000000..3fd0b56
--- /dev/null
+++ b/verilog/dv/usb2uart/Makefile
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
+
diff --git a/verilog/dv/usb2uart/usb2uart.c b/verilog/dv/usb2uart/usb2uart.c
new file mode 100644
index 0000000..059752a
--- /dev/null
+++ b/verilog/dv/usb2uart/usb2uart.c
@@ -0,0 +1,118 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+//#include <stub.c>
+
+// --------------------------------------------------------
+
+void main()
+{
+ // The upper GPIO pins are configured to be output
+ // and accessble to the management SoC.
+ // Used to flag the start/end of a test
+ // The lower GPIO pins are configured to be output
+ // and accessible to the user project. They show
+ // the project count value, although this test is
+ // designed to read the project count through the
+ // logic analyzer probes.
+ // I/O 6 is configured for the UART Tx line
+
+ // User USB
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
+
+ // User UART
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+ // MGMT GPIO
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ //User COUNTER
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ //reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;//mgmt_uart_tx
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUT_MONITORED;
+
+ // Set UART clock to 64 kbaud (enable before I/O configuration)
+ // reg_uart_clkdiv = 625;
+ //reg_uart_enable = 1;
+
+ /* Apply configuration */
+ //reg_mprj_xfer = 1;
+ //while (reg_mprj_xfer == 1);
+
+ // Configure LA probes [31:0], [127:64] as inputs to the cpu
+ // Configure LA probes [63:32] as outputs from the cpu
+ //reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ //reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
+ //reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ //reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
+
+ // Flag start of the test
+ //reg_mprj_datal = 0xAB400000;
+
+ // Set Counter value to zero through LA probes [63:32]
+ //reg_la1_data = 0x00000000;
+
+ // Configure LA probes from [63:32] as inputs to disable counter write
+ //reg_la1_oenb = reg_la1_iena = 0x00000000;
+
+ //reg_mprj_datal = 0xAB410000;
+
+ //print("Test\n\n");
+ //print("\n");
+ //print("\n");
+
+ // Flag end of the test
+ //reg_mprj_datal = 0xAB510000;
+
+ //TODO: Turn on PLL for clock2
+}
diff --git a/verilog/dv/usb2uart/usb2uart_tb.v b/verilog/dv/usb2uart/usb2uart_tb.v
new file mode 100644
index 0000000..0693bca
--- /dev/null
+++ b/verilog/dv/usb2uart/usb2uart_tb.v
@@ -0,0 +1,286 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ps
+
+module usb2uart_tb;
+
+ // Testbench uses a 48 MHz clock
+ // Want to interface to 115200 baud UART
+ parameter c_CLOCK_MHZ = 48;
+ parameter c_UART_SPEED = 115200;
+
+ parameter c_CLOCK_PERIOD_NS = 1000/c_CLOCK_MHZ;
+ parameter c_CLKS_PER_BIT = c_CLOCK_MHZ*1000000/c_UART_SPEED;
+ parameter c_BIT_PERIOD = c_CLKS_PER_BIT*c_CLOCK_PERIOD_NS;
+
+ integer i;
+ integer j;
+ integer k;
+
+ // Signals declaration
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+ reg CSB;
+ wire gpio;
+ wire [37:0] mprj_io;
+
+ reg user_uart_rx;
+/*
+ wire mgmt_uart_tx;
+ assign mgmt_uart_tx = mprj_io[6];
+*/
+ // Signals Assignment
+ assign mprj_io[34] = user_uart_rx;
+
+ always #(c_CLOCK_PERIOD_NS/2) clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ `ifdef ENABLE_SDF
+ initial begin
+ $sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj.mprj) ;
+ $sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
+ $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
+ $sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
+ $sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
+ $sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
+ $sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
+ $sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
+ $sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
+ $sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
+ $sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
+ $sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
+ $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
+ $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
+ end
+ `endif
+
+ initial begin
+ $dumpfile("usb2uart.vcd");
+ $dumpvars(0, usb2uart_tb);
+ //$monitor("usb2uart.in_data: 0x%x", uut.mprj.mprj.usb2uart.in_data);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (100) begin
+ repeat (1000) @(posedge clock);
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Project USB (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Project USB (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ // Write a byte to RX pin
+ task UART_WRITE_RX_AND_RCV;
+ input [7:0] i_Data;
+ integer ii;
+ begin
+ wait(uut.mprj.mprj.usb2uart.in_ready == 1);
+
+ // Write Start Bit
+ #(c_BIT_PERIOD) user_uart_rx <= 1'b0;
+
+ // Write Data
+ for (ii=0; ii<8; ii=ii+1)
+ begin
+ #(c_BIT_PERIOD) user_uart_rx <= i_Data[ii];
+ end
+
+ // Write Stop Bit
+ #(c_BIT_PERIOD) user_uart_rx <= 1'b1;
+
+ //@(posedge uut.mprj.mprj.usb2uart.in_valid);
+ wait(uut.mprj.mprj.usb2uart.in_valid == 1);
+ end
+ endtask
+
+ initial begin
+ // Exercise Rx
+ j=0;
+ for (i=0; i<8; i=i+1)
+ begin
+ UART_WRITE_RX_AND_RCV(i);
+ k = uut.mprj.mprj.usb2uart.in_data;
+ if (k == i)
+ j=j+1;
+ else
+ $display("RX Test Failed - Incorrect Byte Received 0x%x", k);
+ end
+ if (j == 8)
+ $display("RX Test Passed - Correct Bytes Received");
+
+ $finish;
+ end
+
+ // Reset Operation
+ initial begin
+ CSB <= 1'b1;
+ RSTB <= 1'b0;
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #1_300_000;
+ CSB <= 1'b0; // Stop driving CSB
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("usb2uart.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+/*
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(mgmt_uart_tx)
+ );
+*/
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 065fed0..671871d 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -134,18 +134,18 @@
assign io_out[`MPRJ_IO_PADS-5] = uart_tx;
// io_out[34] input uart_rx
assign io_oeb[`MPRJ_IO_PADS-4] = 1'b1;
- assign uart_rx = io_out[`MPRJ_IO_PADS-4];
+ assign uart_rx = io_in[`MPRJ_IO_PADS-4];
// io_out[35] output usb_pu
assign io_oeb[`MPRJ_IO_PADS-3] = 1'b0;
assign io_out[`MPRJ_IO_PADS-3] = usb_pu;
// io_out[36] inout usb_n
assign io_oeb[`MPRJ_IO_PADS-2] = ~usb_tx_en;
assign io_out[`MPRJ_IO_PADS-2] = /* usb_tx_en ? */ usb_n;
- assign usb_n = io_out[`MPRJ_IO_PADS-2];
+ assign usb_n = io_in[`MPRJ_IO_PADS-2];
// io_out[37] inout usb_p
assign io_oeb[`MPRJ_IO_PADS-1] = ~usb_tx_en;
assign io_out[`MPRJ_IO_PADS-1] = /* usb_tx_en ? */ usb_p;
- assign usb_p = io_out[`MPRJ_IO_PADS-1];
+ assign usb_p = io_in[`MPRJ_IO_PADS-1];
usb2uart usb2uart (
.clk48(user_clock2),
