| commit | 080e49aba0dd2603ca7957045655ec9e34f38517 | [log] [tgz] |
|---|---|---|
| author | roman3017 <rbacik@hotmail.com> | Thu Dec 29 17:10:13 2022 -0800 |
| committer | roman3017 <rbacik@hotmail.com> | Thu Dec 29 17:10:13 2022 -0800 |
| tree | 0a1ec1d5edb09401a027d773b26e6315d65285c5 | |
| parent | 852e8efa322183e4c5ab6f1bf922c185bbd5c265 [diff] |
add usb2uart test and fix io_in
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify make SIM=GL verify #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress