MPW shuttle

USB2UART

Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.

See verilog/rtl/fpga folder for FPGA tests.

mkdir -p dependencies
export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src
export PDK_ROOT=$(pwd)/dependencies/pdks
export PDK=sky130A
make setup

make user_proj_example
klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds

make user_project_wrapper
klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds

make verify-usb2uart-rtl
make verify-usb2uart-gl

#make extract-parasitics
make create-spef-mapping
#make caravel-sta

rm -rf ~/mpw_precheck/
make precheck
make run-precheck
#make compress

References

• MPW-8 Shuttle projects (project 1758)
• USB IP taken from ulixxe
• UART IP taken from alexforencich
• Harness Harness specification
• OpenLane OpenLane documentation
• Board Test board
• PLL PLL registers calculator
• QSG Quick start guide
• README A sample project documentation