dineshannayya | 7495ef3 | 2022-04-10 12:43:31 +0530 | [diff] [blame] | 1 | # Caravel user project includes |
| 2 | +define+UNIT_DELAY=#0.1 |
| 3 | +incdir+$(USER_PROJECT_VERILOG)/rtl/ |
| 4 | +incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes |
| 5 | +incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes |
| 6 | +incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes |
dineshannayya | faae6c0 | 2022-09-18 08:28:46 +0530 | [diff] [blame] | 7 | +incdir+$(USER_PROJECT_VERILOG)/dv/common/bfm |
| 8 | +incdir+$(USER_PROJECT_VERILOG)/dv/common/model |
| 9 | +incdir+$(USER_PROJECT_VERILOG)/dv/common/agents |
dineshannayya | 7495ef3 | 2022-04-10 12:43:31 +0530 | [diff] [blame] | 10 | $(USER_PROJECT_VERILOG)/rtl/user_reg_map.v |
dineshannayya | 7495ef3 | 2022-04-10 12:43:31 +0530 | [diff] [blame] | 11 | |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 12 | ################################################## |
| 13 | ### USER PROJECT RTL |
| 14 | ################################################## |
| 15 | #ifdef USER_RTL |
| 16 | #-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v |
| 17 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_top_wb.sv |
| 18 | #else |
| 19 | $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v |
| 20 | #endif |
| 21 | |
| 22 | ################################################## |
| 23 | ### YCR INTERFACE |
| 24 | ################################################## |
| 25 | #ifdef YCR_INTF_RTL |
| 26 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv |
| 27 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv |
| 28 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv |
| 29 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv |
| 30 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv |
| 31 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 32 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/sync_fifo2.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 33 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv |
| 34 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_intf.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 35 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 36 | #else |
| 37 | $(USER_PROJECT_VERILOG)/gl/ycr_intf.v |
| 38 | #endif |
| 39 | ################################################## |
| 40 | ### YCR INTER CONNECT |
| 41 | ################################################## |
| 42 | #ifdef YCR_ICONNECT_RTL |
| 43 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_iconnect.sv |
| 44 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_cross_bar.sv |
| 45 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_router.sv |
| 46 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv |
| 47 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_tcm.sv |
| 48 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_timer.sv |
| 49 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_arb.sv |
| 50 | #else |
| 51 | $(USER_PROJECT_VERILOG)/gl/ycr2_iconnect.v |
| 52 | #endif |
| 53 | |
| 54 | |
| 55 | ################################################## |
| 56 | ### YCR CORE |
| 57 | ################################################## |
| 58 | #ifdef YCR_CORE_RTL |
| 59 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv |
| 60 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_core_top.sv |
| 61 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_dm.sv |
| 62 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc_synchronizer.sv |
| 63 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_clk_ctrl.sv |
| 64 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_scu.sv |
| 65 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc.sv |
| 66 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc_shift_reg.sv |
| 67 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_dmi.sv |
| 68 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ifu.sv |
| 69 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_idu.sv |
| 70 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_exu.sv |
| 71 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mprf.sv |
| 72 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_csr.sv |
| 73 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ialu.sv |
| 74 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mul.sv |
| 75 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_div.sv |
| 76 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_lsu.sv |
| 77 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv |
| 78 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv |
| 79 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 80 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv |
| 81 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 82 | #else |
| 83 | $(USER_PROJECT_VERILOG)/gl/ycr_core_top.v |
| 84 | #endif |
| 85 | ################################################## |
| 86 | ### QSPIM |
| 87 | ################################################## |
| 88 | #ifdef QSPIM_RTL |
| 89 | #-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv |
| 90 | #-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv |
| 91 | #-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_regs.sv |
| 92 | #-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv |
| 93 | #-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_clkgen.sv |
| 94 | #-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_ctrl.sv |
| 95 | #-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_rx.sv |
| 96 | #-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_tx.sv |
| 97 | #else |
| 98 | $(USER_PROJECT_VERILOG)/gl/qspim_top.v |
| 99 | #endif |
| 100 | |
| 101 | |
| 102 | ################################################## |
| 103 | ### WB_HOST |
| 104 | ################################################## |
| 105 | #ifdef WB_HOST_RTL |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 106 | #-v $(USER_PROJECT_VERILOG)/rtl/clk_skew_adjust/src/clk_skew_adjust.v |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 107 | #-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 108 | #-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_reset_fsm.sv |
| 109 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv |
| 110 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv |
| 111 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v |
| 112 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv |
| 113 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v |
| 114 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv |
| 115 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv |
| 116 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v |
| 117 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_div8.v |
| 118 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv |
| 119 | #-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv |
| 120 | #-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv |
| 121 | #-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 122 | #-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv |
| 123 | #-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv |
| 124 | #-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 125 | #-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_top.sv |
| 126 | #-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_if.sv |
| 127 | #-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/spi2wb.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 128 | #else |
| 129 | $(USER_PROJECT_VERILOG)/gl/wb_host.v |
| 130 | #endif |
| 131 | |
| 132 | ################################################## |
| 133 | ### PINMUX |
| 134 | ################################################## |
| 135 | #ifdef PINMUX_RTL |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 136 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_top.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 137 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 138 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_reg.sv |
| 139 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_top.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 140 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 141 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_reg.sv |
| 142 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_top.sv |
| 143 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_reg.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 144 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 145 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_top.sv |
| 146 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_reg.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 147 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 148 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/semaphore_reg.sv |
| 149 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_top.sv |
| 150 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_driver.sv |
| 151 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_reg.sv |
| 152 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/strap_ctrl.sv |
| 153 | #-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_rst_reg.sv |
| 154 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv |
| 155 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv |
| 156 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v |
| 157 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv |
| 158 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv |
| 159 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv |
| 160 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v |
| 161 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 162 | #else |
dineshannayya | 9f6a151 | 2022-08-18 14:11:43 +0530 | [diff] [blame] | 163 | $(USER_PROJECT_VERILOG)/gl/pinmux_top.v |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 164 | #endif |
| 165 | |
| 166 | ################################################## |
| 167 | ### UART |
| 168 | ################################################## |
| 169 | #ifdef UART_RTL |
| 170 | #-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_core.sv |
| 171 | #-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_cfg.sv |
| 172 | #-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_bit_ctrl.v |
| 173 | #-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_byte_ctrl.v |
| 174 | #-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_top.v |
| 175 | #-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_core.sv |
| 176 | #-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc16.sv |
| 177 | #-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc5.sv |
| 178 | #-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_fifo.sv |
| 179 | #-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_sie.sv |
| 180 | #-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_fs_phy.v |
| 181 | #-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_transceiver.v |
| 182 | #-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/top/usb1_host.sv |
| 183 | #-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_top.sv |
| 184 | #-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv |
| 185 | #-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv |
| 186 | #-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 187 | #-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_clkgen.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 188 | #-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv |
| 189 | #else |
| 190 | $(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v |
| 191 | #endif |
| 192 | |
| 193 | ################################################## |
| 194 | ### WISHBONE INTERCONNECT |
| 195 | ################################################## |
| 196 | #ifdef WB_INTER_RTL |
| 197 | #-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv |
| 198 | #-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv |
dineshannayya | 260499b | 2022-09-03 21:17:46 +0530 | [diff] [blame] | 199 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv |
dineshannayya | 75cebb1 | 2022-05-26 18:36:42 +0530 | [diff] [blame] | 200 | #else |
| 201 | $(USER_PROJECT_VERILOG)/gl/wb_interconnect.v |
| 202 | #endif |
| 203 | |
| 204 | #-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv |
| 205 | #-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv |
| 206 | #-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv |
| 207 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv |
| 208 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv |
| 209 | #-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv |
| 210 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv |
| 211 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo2.sv |
| 212 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv |
| 213 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv |
| 214 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv |
| 215 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv |
| 216 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv |
| 217 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv |
| 218 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv |
| 219 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v |
| 220 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v |
| 221 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v |
| 222 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv |
| 223 | #-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv |
dineshannayya | 47fa184 | 2022-11-14 08:22:27 +0530 | [diff] [blame] | 224 | |
dineshannayya | 1300185 | 2022-11-29 22:53:40 +0530 | [diff] [blame] | 225 | $(USER_PROJECT_VERILOG)/gl/aes_top.v |
| 226 | $(USER_PROJECT_VERILOG)/gl/fpu_wrapper.v |
dineshannayya | 77a24bc | 2022-12-06 08:43:20 +0530 | [diff] [blame] | 227 | $(USER_PROJECT_VERILOG)/gl/bus_rep_south.v |
| 228 | $(USER_PROJECT_VERILOG)/gl/bus_rep_north.v |
| 229 | $(USER_PROJECT_VERILOG)/gl/bus_rep_east.v |
| 230 | $(USER_PROJECT_VERILOG)/gl/bus_rep_west.v |
dineshannayya | ac1171f | 2022-12-10 22:11:59 +0530 | [diff] [blame^] | 231 | $(USER_PROJECT_VERILOG)/gl/peri_top.v |
dineshannayya | 47fa184 | 2022-11-14 08:22:27 +0530 | [diff] [blame] | 232 | |
| 233 | -v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v |
| 234 | |
| 235 | -v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v |