timing clean-up with bus repeater
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index d7c52cc..35d26f5 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -224,6 +224,10 @@
$(USER_PROJECT_VERILOG)/gl/aes_top.v
$(USER_PROJECT_VERILOG)/gl/fpu_wrapper.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_south.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_north.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_east.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_west.v
-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
