| commit | ac1171fcdd17d57f16bdadd3cd5a8d35a1fb87d8 | [log] [tgz] |
|---|---|---|
| author | dineshannayya <dinesh.annayya@gmail.com> | Sat Dec 10 22:11:59 2022 +0530 |
| committer | dineshannayya <dinesh.annayya@gmail.com> | Sat Dec 10 22:11:59 2022 +0530 |
| tree | 32b545be06736756ceabdfafadd8d67d7b1f3905 | |
| parent | ee90a108ea3975e443263f1b3ba5ee3937c7c80f [diff] [blame] |
rtc integration
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index 35d26f5..7a843f5 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -228,6 +228,7 @@ $(USER_PROJECT_VERILOG)/gl/bus_rep_north.v $(USER_PROJECT_VERILOG)/gl/bus_rep_east.v $(USER_PROJECT_VERILOG)/gl/bus_rep_west.v +$(USER_PROJECT_VERILOG)/gl/peri_top.v -v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v