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Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +02001// SPDX-FileCopyrightText: 2020 Efabless Corporation
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14// SPDX-License-Identifier: Apache-2.0
15
16`default_nettype none
17/*
18 *-------------------------------------------------------------
19 *
20 * user_proj_example
21 *
22 * This is an example of a (trivially simple) user project,
23 * showing how the user project can connect to the logic
24 * analyzer, the wishbone bus, and the I/O pads.
25 *
26 * This project generates an integer count, which is output
27 * on the user area GPIO pads (digital output only). The
28 * wishbone connection allows the project to be controlled
29 * (start and stop) from the management SoC program.
30 *
31 * See the testbenches in directory "mprj_counter" for the
32 * example programs that drive this user project. The three
33 * testbenches are "io_ports", "la_test1", and "la_test2".
34 *
35 *-------------------------------------------------------------
36 */
37
38module user_proj_example #(
39 parameter BITS = 32
40)(
41`ifdef USE_POWER_PINS
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020042 inout vccd1, // User area 1 1.8V supply
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020043 inout vssd1, // User area 1 digital ground
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020044`endif
45
46 // Wishbone Slave ports (WB MI A)
47 input wb_clk_i,
48 input wb_rst_i,
49 input wbs_stb_i,
50 input wbs_cyc_i,
51 input wbs_we_i,
52 input [3:0] wbs_sel_i,
53 input [31:0] wbs_dat_i,
54 input [31:0] wbs_adr_i,
55 output wbs_ack_o,
56 output [31:0] wbs_dat_o,
57
58 // Logic Analyzer Signals
59 input [127:0] la_data_in,
60 output [127:0] la_data_out,
Tim Edwardsc89cfac2021-04-23 15:16:09 -040061 input [127:0] la_oenb,
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020062
63 // IOs
64 input [`MPRJ_IO_PADS-1:0] io_in,
65 output [`MPRJ_IO_PADS-1:0] io_out,
Tim Edwards694bfd32021-04-23 10:55:41 -040066 output [`MPRJ_IO_PADS-1:0] io_oeb,
67
68 // IRQ
69 output [2:0] irq
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020070);
71 wire clk;
72 wire rst;
73
74 wire [`MPRJ_IO_PADS-1:0] io_in;
75 wire [`MPRJ_IO_PADS-1:0] io_out;
76 wire [`MPRJ_IO_PADS-1:0] io_oeb;
77
78 wire [31:0] rdata;
79 wire [31:0] wdata;
80 wire [BITS-1:0] count;
81
82 wire valid;
83 wire [3:0] wstrb;
84 wire [31:0] la_write;
85
86 // WB MI A
87 assign valid = wbs_cyc_i && wbs_stb_i;
88 assign wstrb = wbs_sel_i & {4{wbs_we_i}};
89 assign wbs_dat_o = rdata;
90 assign wdata = wbs_dat_i;
91
92 // IO
93 assign io_out = count;
94 assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
95
Tim Edwards694bfd32021-04-23 10:55:41 -040096 // IRQ
manarabdelaty401a14d2021-04-23 17:20:56 +020097 assign irq = 3'b000; // Unused
Tim Edwards694bfd32021-04-23 10:55:41 -040098
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020099 // LA
100 assign la_data_out = {{(127-BITS){1'b0}}, count};
101 // Assuming LA probes [63:32] are for controlling the count register
Tim Edwardsc89cfac2021-04-23 15:16:09 -0400102 assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +0200103 // Assuming LA probes [65:64] are for controlling the count clk & reset
Tim Edwardsc89cfac2021-04-23 15:16:09 -0400104 assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
105 assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +0200106
107 counter #(
108 .BITS(BITS)
109 ) counter(
110 .clk(clk),
111 .reset(rst),
112 .ready(wbs_ack_o),
113 .valid(valid),
114 .rdata(rdata),
115 .wdata(wbs_dat_i),
116 .wstrb(wstrb),
117 .la_write(la_write),
118 .la_input(la_data_in[63:32]),
119 .count(count)
120 );
121
122endmodule
123
124module counter #(
125 parameter BITS = 32
126)(
127 input clk,
128 input reset,
129 input valid,
130 input [3:0] wstrb,
131 input [BITS-1:0] wdata,
132 input [BITS-1:0] la_write,
133 input [BITS-1:0] la_input,
134 output ready,
135 output [BITS-1:0] rdata,
136 output [BITS-1:0] count
137);
138 reg ready;
139 reg [BITS-1:0] count;
140 reg [BITS-1:0] rdata;
141
142 always @(posedge clk) begin
143 if (reset) begin
144 count <= 0;
145 ready <= 0;
146 end else begin
147 ready <= 1'b0;
148 if (~|la_write) begin
149 count <= count + 1;
150 end
151 if (valid && !ready) begin
152 ready <= 1'b1;
153 rdata <= count;
154 if (wstrb[0]) count[7:0] <= wdata[7:0];
155 if (wstrb[1]) count[15:8] <= wdata[15:8];
156 if (wstrb[2]) count[23:16] <= wdata[23:16];
157 if (wstrb[3]) count[31:24] <= wdata[31:24];
manarabdelatya63e2e62021-04-08 20:32:40 +0200158 end else if (|la_write) begin
159 count <= la_write & la_input;
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +0200160 end
161 end
162 end
163
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +0200164endmodule
165`default_nettype wire