Update to coincide with the most recent commit to the caravel
project. Added C code to control the input enable lines for
inputs coming from the user project. Since the example code assumes
one-way traffic, the output enable is just the inverse of the input
enable.
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b949583..b33e032 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -64,7 +64,7 @@
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
- input [127:0] la_oen,
+ input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
@@ -105,10 +105,10 @@
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
// Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
+ assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
+ assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+ assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
counter #(
.BITS(BITS)
