power: remove excess power pins

There were leftover power pins that shouldn't be used. They were causing
LVS issues.

Signed-off-by: Sean Cross <sean@xobs.io>

openlane/wb_pio/config.json

diff --git a/openlane/wb_pio/config.json b/openlane/wb_pio/config.json
index 4bf8a2f..e26a079 100644
--- a/openlane/wb_pio/config.json
+++ b/openlane/wb_pio/config.json
@@ -18,8 +18,8 @@
     "pdk::sky130*": {
         "FP_CORE_UTIL": 35,
         "PL_TARGET_DENSITY": 0.30,
-        "VDD_NETS": ["vccd1", "vccd2","vdda1","vdda2"],
-        "GND_NETS": ["vssd1", "vssd2","vssa1","vssa2"],
+        "VDD_NETS": ["vccd1"],
+        "GND_NETS": ["vssd1"],
         "RT_MAX_LAYER": "met4",
         "scl::sky130_fd_sc_hd": {
             "CLOCK_PERIOD": 12

verilog/rtl/wb_pio_top.v

diff --git a/verilog/rtl/wb_pio_top.v b/verilog/rtl/wb_pio_top.v
index aa464cc..9faaea5 100644
--- a/verilog/rtl/wb_pio_top.v
+++ b/verilog/rtl/wb_pio_top.v
@@ -42,13 +42,9 @@
     // SKY130
     inout vccd1,	// User area 1 1.8V supply
     inout vssd1,	// User area 1 digital ground
-    inout vdda1,	// User area 1 3.3V supply
-    inout vssa2,	// User area 2 analog ground
-    inout vdda2,	// User area 2 3.3V supply
-    inout vssd2,	// User area 2 digital ground
-    // GF180
-    inout vdd,	    // User area 1 1.8V supply
-    inout vss,    	// User area 1 digital ground
+    // // GF180
+    // inout vdd,	    // User area 1 1.8V supply
+    // inout vss,    	// User area 1 digital ground
 `endif
 
     // Wishbone Slave ports (WB MI A)