| { |
| "DESIGN_NAME": "wb_pio", |
| "DESIGN_IS_CORE": 0, |
| "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/wb_pio_top.v", "dir::../../verilog/rtl/fpga_pio/src/*.v"], |
| "CLOCK_PERIOD": 10, |
| "CLOCK_PORT": "wb_clk_i", |
| "CLOCK_NET": "pio_1.clk", |
| "FP_SIZING": "absolute", |
| "DIE_AREA": "0 0 1300 1400", |
| "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", |
| "DIODE_INSERTION_STRATEGY": 4, |
| "RUN_CVC": 0, |
| "RUN_MAGIC": 1, |
| "RUN_KLAYOUT": 0, |
| "SYNTH_STRATEGY": "AREA 3", |
| "SYNTH_AUTONAME": "1", |
| "ROUTING_CORES": 20, |
| "pdk::sky130*": { |
| "FP_CORE_UTIL": 35, |
| "PL_TARGET_DENSITY": 0.30, |
| "VDD_NETS": ["vccd1"], |
| "GND_NETS": ["vssd1"], |
| "RT_MAX_LAYER": "met4", |
| "scl::sky130_fd_sc_hd": { |
| "CLOCK_PERIOD": 12 |
| }, |
| "scl::sky130_fd_sc_hdll": { |
| "CLOCK_PERIOD": 12 |
| }, |
| "scl::sky130_fd_sc_hs": { |
| "CLOCK_PERIOD": 10 |
| }, |
| "scl::sky130_fd_sc_ls": { |
| "CLOCK_PERIOD": 12, |
| "SYNTH_MAX_FANOUT": 5 |
| }, |
| "scl::sky130_fd_sc_ms": { |
| "CLOCK_PERIOD": 12 |
| } |
| }, |
| "pdk::gf180mcuC": { |
| "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", |
| "CLOCK_PERIOD": 200, |
| "FP_CORE_UTIL": 35, |
| "PL_TARGET_DENSITY": 0.30, |
| "RT_MAX_LAYER": "Metal4", |
| "SYNTH_MAX_FANOUT": 4, |
| "VDD_NETS": ["vdd"], |
| "GND_NETS": ["vss"] |
| } |
| } |
