blob: 551fe41e7a61bd4a9f42630975c1e043b53b1e92 [file] [log] [blame]
/root/prga-test/openlane/prga/constraint.sdc
/root/prga-test/openlane/prga/gen_placement.py
/root/prga-test/openlane/prga/hackflow.sh
/root/prga-test/openlane/prga/pdn_cfg.tcl
/root/prga-test/openlane/tile_clb/constraint.sdc
/root/prga-test/openlane/tile_clb/pdn_cfg.tcl
/root/prga-test/openlane/user_proj_example/config.json
/root/prga-test/openlane/user_project_wrapper/config.json
/root/prga-test/verilog/dv/prga/bcd2bin.v
/root/prga-test/verilog/dv/prga/bcd2bin_test_basic.v
/root/prga-test/verilog/dv/prga/checker.v
/root/prga-test/verilog/dv/prga/prga_bitstream_loader.v
/root/prga-test/verilog/includes/includes.gl+sdf.caravel_user_project
/root/prga-test/verilog/includes/includes.gl.caravel_user_project
/root/prga-test/verilog/includes/includes.rtl.caravel_user_project
/root/prga-test/verilog/rtl/tile_clb.bb.v
/root/prga-test/verilog/rtl/tile_clb.pickled.reduced.v
/root/prga-test/verilog/rtl/tile_clb.pickled.v
/root/prga-test/verilog/rtl/top.bb.v
/root/prga-test/verilog/rtl/top.pickled.v
/root/prga-test/verilog/rtl/user_project_wrapper.v