initial commit

Signed-off-by: vijayank88 <>

	modified:   Makefile
	renamed:    gds/user_project_wrapper.gds -> gds/openGFX430.gds.gz
	new file:   gds/user_proj_example.gds.gz
	new file:   gds/user_project_wrapper.gds.gz
	new file:   gfx430_architecture.png
	new file:   lef/openGFX430.lef
	modified:   lef/user_project_wrapper.lef
	new file:   mag/openGFX430.mag
	new file:   mag/user_project_wrapper.mag.gz
	modified:   maglef/user_project_wrapper.mag
	new file:   openlane/openGFX430/config.tcl
	modified:   openlane/user_project_wrapper/config.tcl
	new file:   sdc/openGFX430.sdc
	new file:   sdc/user_project_wrapper.sdc
	new file:   sdf/openGFX430.sdf
	new file:   sdf/user_project_wrapper.sdf
	new file:   signoff/openGFX430/OPENLANE_VERSION
	new file:   signoff/openGFX430/PDK_SOURCES
	new file:   signoff/openGFX430/metrics.csv
	modified:   signoff/user_project_wrapper/OPENLANE_VERSION
	modified:   signoff/user_project_wrapper/PDK_SOURCES
	new file:   signoff/user_project_wrapper/metrics.csv
	new file:   spef/openGFX430.spef
	new file:   spef/user_project_wrapper.spef
	new file:   spi/lvs/openGFX430.spice
	modified:   spi/lvs/user_project_wrapper.spice
	new file:   verilog/dv/openGFX430/Makefile
	new file:   verilog/dv/openGFX430/openGFX430.c
	new file:   verilog/dv/openGFX430/openGFX430_tb.v
	new file:   verilog/gl/openGFX430.v
	modified:   verilog/gl/user_project_wrapper.v
	modified:   verilog/includes/includes.rtl.caravel_user_project
	new file:   verilog/rtl/src/ogfx_backend.v
	new file:   verilog/rtl/src/ogfx_backend_frame_fifo.v
	new file:   verilog/rtl/src/ogfx_backend_lut_fifo.v
	new file:   verilog/rtl/src/ogfx_gpu.v
	new file:   verilog/rtl/src/ogfx_gpu_dma.v
	new file:   verilog/rtl/src/ogfx_gpu_dma_addr.v
	new file:   verilog/rtl/src/ogfx_gpu_reg.v
	new file:   verilog/rtl/src/ogfx_if_lt24.v
	new file:   verilog/rtl/src/ogfx_ram_arbiter.v
	new file:   verilog/rtl/src/ogfx_reg.v
	new file:   verilog/rtl/src/ogfx_reg_fifo.v
	new file:   verilog/rtl/src/ogfx_reg_vram_addr.v
	new file:   verilog/rtl/src/ogfx_reg_vram_if.v
	new file:   verilog/rtl/src/openGFX430.v
	new file:   verilog/rtl/src/openGFX430_defines.v
	new file:   verilog/rtl/src/openGFX430_undefines.v
	modified:   verilog/rtl/user_project_wrapper.v
56 files changed
tree: b851bf49eaa9cf046478752eecaeb4fdbfde6fab
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. gfx430_architecture.png
  18. Makefile

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Graphics Controller


The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.

The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.

The core comes with some peripherals (16x16 Hardware Multiplier, Watchdog, GPIO, TimerA, generic templates), with a DMA interface, and most notably with a two-wire Serial Debug Interface supporting the MSPGCC GNU Debugger (GDB) for in-system software debugging.

While being fully FPGA friendly, this design is also particularly suited for ASIC implementations (typically mixed signal ICs with strong area and low-power requirements). In a nutshell, the openMSP430 brings with it:

  • Low area (8k-Gates), without hidden extra infrastructure overhead (memory backbone, IRQ controller and watchdog timer are already included).
  • Excellent code density.
  • Good performances.
  • Build-in power and clock managment options.
  • Multiple times Silicon Proven.



Support following graphic modes:

  • 16bpp
  • 8bpp
  • 4bpp
  • 2bpp
  • 1bpp
  • Smart address generation unit for fast indirect memory access.
  • GPU allowing hardware FILL, COPY and COPY_TRANSPARENT operations.
  • Supports the LT24 Terasic daughter card.