| design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY | |
| /home/vijayan/CARAVEL_FLOW/graphics_controller/openlane/openGFX430,openGFX430,22_08_31_13_48,flow completed,0h46m9s0ms,0h29m26s0ms,-3.3333333333333335,0.4890546994250001,-1,30.69,2701.39,-1,0,0,0,0,0,0,0,34,0,-1,-1,938758,140703,0.0,-0.56,0.0,-0.17,-1,0.0,-10.23,0.0,-0.21,-1,784858920.0,0.0,53.64,47.72,14.81,20.51,-1,10908,16340,760,6162,0,0,0,12155,449,178,196,621,2694,772,202,1066,1548,3034,43,502,6578,0,7080,466051.9808,0.0126,0.00667,9.65e-05,0.0158,0.0085,1.18e-07,0.018,0.01,1.84e-07,2.0199999999999996,11.0,90.9090909090909,10,DELAY 0,5,30,1,153.6,153.18,0.35,0.2,sky130_fd_sc_hd,2,4 |