mpw7 resubmit Signed-off-by: vijayank88 <paruthi143@gmail.com>
diff --git a/Makefile b/Makefile index 951292b..7d4e1c1 100644 --- a/Makefile +++ b/Makefile
@@ -17,23 +17,25 @@ export CARAVEL_ROOT?=$(PWD)/caravel PRECHECK_ROOT?=${HOME}/mpw_precheck -MCW_ROOT?=$(PWD)/mgmt_core_wrapper +export MCW_ROOT?=$(PWD)/mgmt_core_wrapper SIM?=RTL -export SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c -export OPEN_PDKS_COMMIT?=e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066 -export OPENLANE_TAG=2022.07.30 - # Install lite version of caravel, (1): caravel-lite, (0): caravel CARAVEL_LITE?=1 # PDK switch varient -export PDK?=sky130B +export PDK?=sky130A +#export PDK?=gf180mcuC export PDKPATH?=$(PDK_ROOT)/$(PDK) -MPW_TAG ?= mpw-7a +ifeq ($(PDK),sky130A) + SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c + export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f + export OPENLANE_TAG?=2022.11.19 + MPW_TAG ?= mpw-8b + ifeq ($(CARAVEL_LITE),1) CARAVEL_NAME := caravel-lite CARAVEL_REPO := https://github.com/efabless/caravel-lite @@ -44,6 +46,38 @@ CARAVEL_TAG := $(MPW_TAG) endif +endif + +ifeq ($(PDK),sky130B) + SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c + export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f + export OPENLANE_TAG?=2022.11.19 + MPW_TAG ?= mpw-8b + +ifeq ($(CARAVEL_LITE),1) + CARAVEL_NAME := caravel-lite + CARAVEL_REPO := https://github.com/efabless/caravel-lite + CARAVEL_TAG := $(MPW_TAG) +else + CARAVEL_NAME := caravel + CARAVEL_REPO := https://github.com/efabless/caravel + CARAVEL_TAG := $(MPW_TAG) +endif + +endif + +ifeq ($(PDK),gf180mcuC) + + MPW_TAG ?= gfmpw-0b + CARAVEL_NAME := caravel + CARAVEL_REPO := https://github.com/efabless/caravel-gf180mcu + CARAVEL_TAG := $(MPW_TAG) + #OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9 + export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f + export OPENLANE_TAG?=2022.11.19 + +endif + # Include Caravel Makefile Targets .PHONY: % : check-caravel %: @@ -64,7 +98,7 @@ docker pull efabless/dv:latest .PHONY: setup -setup: install check-env install_mcw openlane pdk-with-volare +setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts # Openlane blocks=$(shell cd openlane && find * -maxdepth 0 -type d) @@ -87,8 +121,10 @@ -e CARAVEL_ROOT=${CARAVEL_ROOT} \ -e TOOLS=/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937 \ -e DESIGNS=$(TARGET_PATH) \ + -e USER_PROJECT_VERILOG=$(TARGET_PATH)/verilog \ -e PDK=$(PDK) \ -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \ + -e CARAVEL_VERILOG_PATH=$(TARGET_PATH)/caravel/verilog \ -e MCW_ROOT=$(MCW_ROOT) \ -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv:latest \ sh -c $(verify_command) @@ -225,3 +261,64 @@ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$' +export CUP_ROOT=$(shell pwd) +export TIMING_ROOT?=$(shell pwd)/deps/timing-scripts +export PROJECT_ROOT=$(CUP_ROOT) +timing-scripts-repo=https://github.com/efabless/timing-scripts.git + +$(TIMING_ROOT): + @mkdir -p $(CUP_ROOT)/deps + @git clone $(timing-scripts-repo) $(TIMING_ROOT) + +.PHONY: setup-timing-scripts +setup-timing-scripts: $(TIMING_ROOT) + @( cd $(TIMING_ROOT) && git pull ) + @#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); ) + @python3 -m venv ./venv + . ./venv/bin/activate && \ + python3 -m pip install --upgrade pip && \ + python3 -m pip install -r $(TIMING_ROOT)/requirements.txt && \ + deactivate + +./verilog/gl/user_project_wrapper.v: + $(error you don't have $@) + +./env/spef-mapping.tcl: + @echo "run the following:" + @echo "make extract-parasitics" + @echo "make create-spef-mapping" + exit 1 + +.PHONY: create-spef-mapping +create-spef-mapping: ./verilog/gl/user_project_wrapper.v + @. ./venv/bin/activate && \ + python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \ + -i ./verilog/gl/user_project_wrapper.v \ + -o ./env/spef-mapping.tcl \ + --pdk-path $(PDK_ROOT)/$(PDK) \ + --macro-parent mprj \ + --project-root "$(CUP_ROOT)" && \ + deactivate + +.PHONY: extract-parasitics +extract-parasitics: ./verilog/gl/user_project_wrapper.v + @. ./venv/bin/activate && \ + python3 $(TIMING_ROOT)/scripts/get_macros.py \ + -i ./verilog/gl/user_project_wrapper.v \ + -o ./tmp-macros-list \ + --project-root "$(CUP_ROOT)" \ + --pdk-path $(PDK_ROOT)/$(PDK) && \ + deactivate + @cat ./tmp-macros-list | cut -d " " -f2 \ + | xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \ + -f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'" + @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk rcx-user_project_wrapper + @cat ./tmp-macros-list + @rm ./tmp-macros-list + +.PHONY: caravel-sta +caravel-sta: ./env/spef-mapping.tcl + @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ + @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast + @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow + @echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v new file mode 100644 index 0000000..ee44b08 --- /dev/null +++ b/verilog/rtl/user_defines.v
@@ -0,0 +1,92 @@ +// SPDX-FileCopyrightText: 2022 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`ifndef __USER_DEFINES_H +// User GPIO initial configuration parameters +`define __USER_DEFINES_H + +// deliberately erroneous placeholder value; user required to config GPIO's to other +`define GPIO_MODE_INVALID 13'hXXXX + +// Authoritive source of these MODE defs is: caravel/verilog/rtl/user_defines.v +// Useful GPIO mode values. These match the names used in defs.h. +// +`define GPIO_MODE_MGMT_STD_INPUT_NOPULL 13'h0403 +`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 13'h0c01 +`define GPIO_MODE_MGMT_STD_INPUT_PULLUP 13'h0801 +`define GPIO_MODE_MGMT_STD_OUTPUT 13'h1809 +`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 13'h1801 +`define GPIO_MODE_MGMT_STD_ANALOG 13'h000b + +`define GPIO_MODE_USER_STD_INPUT_NOPULL 13'h0402 +`define GPIO_MODE_USER_STD_INPUT_PULLDOWN 13'h0c00 +`define GPIO_MODE_USER_STD_INPUT_PULLUP 13'h0800 +`define GPIO_MODE_USER_STD_OUTPUT 13'h1808 +`define GPIO_MODE_USER_STD_BIDIRECTIONAL 13'h1800 +`define GPIO_MODE_USER_STD_OUT_MONITORED 13'h1802 +`define GPIO_MODE_USER_STD_ANALOG 13'h000a + +// The power-on configuration for GPIO 0 to 4 is fixed and cannot be +// modified (allowing the SPI and debug to always be accessible unless +// overridden by a flash program). + +// The values below can be any of the standard types defined above, +// or they can be any 13-bit value if the user wants a non-standard +// startup state for the GPIO. By default, every GPIO from 5 to 37 +// is set to power up as an input controlled by the management SoC. +// Users may want to redefine these so that the user project powers +// up in a state that can be used immediately without depending on +// the management SoC to run a startup program to configure the GPIOs. + +`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_INVALID + +// Configurations of GPIO 14 to 24 are used on caravel but not caravan. +`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_INVALID + +`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_INVALID + +`endif // __USER_DEFINES_H