commit | 8228c12434afc3b246a31a84b5fcc13e60beefa9 | [log] [tgz] |
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author | vijayank88 <paruthi143@gmail.com> | Thu Sep 01 10:07:21 2022 +0000 |
committer | vijayank88 <paruthi143@gmail.com> | Thu Sep 01 11:17:50 2022 +0000 |
tree | b851bf49eaa9cf046478752eecaeb4fdbfde6fab | |
parent | 4604ea49a72242512db4a86f95c6282d22d35aba [diff] |
initial commit Signed-off-by: vijayank88 <paruthi143@gmail.com> modified: Makefile modified: README.md renamed: gds/user_project_wrapper.gds -> gds/openGFX430.gds.gz new file: gds/user_proj_example.gds.gz new file: gds/user_project_wrapper.gds.gz new file: gfx430_architecture.png new file: lef/openGFX430.lef modified: lef/user_project_wrapper.lef new file: mag/openGFX430.mag new file: mag/user_project_wrapper.mag.gz modified: maglef/user_project_wrapper.mag new file: openlane/openGFX430/config.tcl modified: openlane/user_project_wrapper/config.tcl new file: sdc/openGFX430.sdc new file: sdc/user_project_wrapper.sdc new file: sdf/openGFX430.sdf new file: sdf/user_project_wrapper.sdf new file: signoff/openGFX430/OPENLANE_VERSION new file: signoff/openGFX430/PDK_SOURCES new file: signoff/openGFX430/metrics.csv modified: signoff/user_project_wrapper/OPENLANE_VERSION modified: signoff/user_project_wrapper/PDK_SOURCES new file: signoff/user_project_wrapper/metrics.csv new file: spef/openGFX430.spef new file: spef/user_project_wrapper.spef new file: spi/lvs/openGFX430.spice modified: spi/lvs/user_project_wrapper.spice new file: verilog/dv/openGFX430/Makefile new file: verilog/dv/openGFX430/openGFX430.c new file: verilog/dv/openGFX430/openGFX430_tb.v new file: verilog/gl/openGFX430.v modified: verilog/gl/user_project_wrapper.v modified: verilog/includes/includes.rtl.caravel_user_project new file: verilog/rtl/src/ogfx_backend.v new file: verilog/rtl/src/ogfx_backend_frame_fifo.v new file: verilog/rtl/src/ogfx_backend_lut_fifo.v new file: verilog/rtl/src/ogfx_gpu.v new file: verilog/rtl/src/ogfx_gpu_dma.v new file: verilog/rtl/src/ogfx_gpu_dma_addr.v new file: verilog/rtl/src/ogfx_gpu_reg.v new file: verilog/rtl/src/ogfx_if_lt24.v new file: verilog/rtl/src/ogfx_ram_arbiter.v new file: verilog/rtl/src/ogfx_reg.v new file: verilog/rtl/src/ogfx_reg_fifo.v new file: verilog/rtl/src/ogfx_reg_vram_addr.v new file: verilog/rtl/src/ogfx_reg_vram_if.v new file: verilog/rtl/src/openGFX430.v new file: verilog/rtl/src/openGFX430_defines.v new file: verilog/rtl/src/openGFX430_undefines.v modified: verilog/rtl/user_project_wrapper.v
:exclamation: Important Note |
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The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.
The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.
The core comes with some peripherals (16x16 Hardware Multiplier, Watchdog, GPIO, TimerA, generic templates), with a DMA interface, and most notably with a two-wire Serial Debug Interface supporting the MSPGCC GNU Debugger (GDB) for in-system software debugging.
While being fully FPGA friendly, this design is also particularly suited for ASIC implementations (typically mixed signal ICs with strong area and low-power requirements). In a nutshell, the openMSP430 brings with it:
Support following graphic modes: