| ############################################################################### |
| # Created by write_sdc |
| # Sun Sep 11 11:39:04 2022 |
| ############################################################################### |
| current_design warpv_core |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name clk -period 15.0000 [get_ports {clk}] |
| set_clock_transition 0.1500 [get_clocks {clk}] |
| set_clock_uncertainty 0.2500 clk |
| set_propagated_clock [get_clocks {clk}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[0]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[10]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[11]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[12]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[13]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[14]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[15]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[16]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[17]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[18]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[19]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[1]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[20]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[21]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[22]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[23]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[24]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[25]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[26]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[27]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[28]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[29]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[2]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[30]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[31]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[3]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[4]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[5]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[6]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[7]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[8]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_doutb[9]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[0]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[10]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[11]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[12]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[13]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[14]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[15]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[16]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[17]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[18]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[19]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[1]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[20]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[21]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[22]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[23]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[24]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[25]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[26]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[27]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[28]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[29]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[2]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[30]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[31]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[3]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[4]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[5]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[6]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[7]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[8]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_data[9]}] |
| set_input_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {reset}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[0]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[10]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[11]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[12]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[13]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[14]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[15]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[16]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[17]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[18]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[19]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[1]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[20]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[21]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[22]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[23]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[24]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[25]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[26]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[27]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[28]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[29]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[2]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[30]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[31]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[3]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[4]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[5]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[6]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[7]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[8]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addra[9]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[0]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[10]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[11]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[12]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[13]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[14]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[15]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[16]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[17]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[18]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[19]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[1]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[20]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[21]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[22]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[23]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[24]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[25]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[26]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[27]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[28]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[29]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[2]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[30]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[31]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[3]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[4]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[5]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[6]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[7]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[8]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_addrb[9]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[0]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[10]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[11]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[12]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[13]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[14]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[15]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[16]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[17]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[18]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[19]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[1]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[20]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[21]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[22]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[23]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[24]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[25]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[26]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[27]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[28]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[29]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[2]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[30]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[31]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[3]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[4]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[5]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[6]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[7]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[8]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dina[9]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[0]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[10]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[11]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[12]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[13]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[14]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[15]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[16]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[17]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[18]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[19]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[1]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[20]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[21]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[22]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[23]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[24]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[25]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[26]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[27]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[28]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[29]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[2]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[30]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[31]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[3]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[4]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[5]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[6]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[7]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[8]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_dinb[9]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_ena}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_enb}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_wea0}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_wea[0]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_wea[1]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_wea[2]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_wea[3]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_web[0]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_web[1]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_web[2]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {dmem_web[3]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[0]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[10]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[11]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[12]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[13]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[14]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[15]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[16]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[17]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[18]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[19]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[1]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[20]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[21]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[22]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[23]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[24]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[25]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[26]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[27]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[28]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[29]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[2]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[30]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[31]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[3]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[4]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[5]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[6]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[7]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[8]}] |
| set_output_delay 3.0000 -clock [get_clocks {clk}] -add_delay [get_ports {imem_addr[9]}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {dmem_ena}] |
| set_load -pin_load 0.0334 [get_ports {dmem_enb}] |
| set_load -pin_load 0.0334 [get_ports {dmem_wea0}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[31]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[30]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[29]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[28]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[27]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[26]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[25]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[24]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[23]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[22]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[21]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[20]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[19]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[18]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[17]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[16]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[15]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[14]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[13]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[12]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[11]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[10]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[9]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[8]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[7]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[6]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[5]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[4]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[3]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[2]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[1]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addra[0]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[31]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[30]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[29]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[28]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[27]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[26]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[25]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[24]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[23]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[22]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[21]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[20]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[19]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[18]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[17]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[16]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[15]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[14]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[13]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[12]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[11]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[10]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[9]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[8]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[7]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[6]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[5]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[4]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[3]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[2]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[1]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_addrb[0]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[31]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[30]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[29]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[28]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[27]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[26]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[25]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[24]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[23]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[22]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[21]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[20]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[19]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[18]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[17]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[16]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[15]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[14]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[13]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[12]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[11]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[10]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[9]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[8]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[7]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[6]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[5]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[4]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[3]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[2]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[1]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dina[0]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[31]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[30]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[29]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[28]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[27]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[26]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[25]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[24]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[23]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[22]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[21]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[20]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[19]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[18]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[17]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[16]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[15]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[14]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[13]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[12]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[11]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[10]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[9]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[8]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[7]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[6]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[5]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[4]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[3]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[2]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[1]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_dinb[0]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_wea[3]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_wea[2]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_wea[1]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_wea[0]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_web[3]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_web[2]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_web[1]}] |
| set_load -pin_load 0.0334 [get_ports {dmem_web[0]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {imem_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_doutb[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem_data[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 5.0000 [current_design] |