| commit | 78d60aed9b67196e8c5f104a7a8ab10b1c97f49f | [log] [tgz] |
|---|---|---|
| author | Ali Imran <59641896+ALI11-2000@users.noreply.github.com> | Mon Sep 12 10:27:27 2022 +0500 |
| committer | GitHub <noreply@github.com> | Mon Sep 12 10:27:27 2022 +0500 |
| tree | b4d91da9554894af9e9eac9f8dad903405492f71 | |
| parent | 2b2c6e7de1429a142cd6784b5ea4110436f4436f [diff] |
Update user_project_ci.yml
WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging “transaction-level design” methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable. WARP-V is an evolving library of CPU components as well as various compositions of them. It is driven by a community interested in transforming the silicon industry through open-source hardware and revolutionary design methodology.