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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-007
/
slot-018
/
d9a00d8f8ce90d3b63cee7abf2441dcd762f4975
/
.
/
verilog
/
rtl
/
adder_rtl.v
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module
Adder
#(parameter SIZE=64)
(
input wire clk
,
input wire
[
SIZE
-
1
:
0
]
a
,
input wire
[
SIZE
-
1
:
0
]
b
,
output reg
[
SIZE
-
1
:
0
]
out
);
always
@(
posedge clk
)
begin
out
<=
a
+
b
;
end
endmodule