blob: c9266ee072fe7b741663eee1e72e7e26daf0d072 [file] [log] [blame]
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +02001# SPDX-FileCopyrightText: 2020 Efabless Corporation
2#
3# Licensed under the Apache License, Version 2.0 (the "License");
4# you may not use this file except in compliance with the License.
5# You may obtain a copy of the License at
6#
7# http://www.apache.org/licenses/LICENSE-2.0
8#
9# Unless required by applicable law or agreed to in writing, software
10# distributed under the License is distributed on an "AS IS" BASIS,
11# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12# See the License for the specific language governing permissions and
13# limitations under the License.
14# SPDX-License-Identifier: Apache-2.0
15
nofal6eecddc2021-10-12 22:46:36 +020016set ::env(PDK) "sky130A"
17set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
18
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020019set script_dir [file dirname [file normalize [info script]]]
20
21set ::env(DESIGN_NAME) user_proj_example
22
23set ::env(VERILOG_FILES) "\
manarabdelatycf577da2021-09-17 18:20:33 +020024 $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020025 $script_dir/../../verilog/rtl/user_proj_example.v"
26
manarabdelatycf577da2021-09-17 18:20:33 +020027set ::env(DESIGN_IS_CORE) 0
28
29set ::env(CLOCK_PORT) "wb_clk_i"
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020030set ::env(CLOCK_NET) "counter.clk"
31set ::env(CLOCK_PERIOD) "10"
32
33set ::env(FP_SIZING) absolute
Ahmed Ghazy548e5a72021-04-06 00:07:33 +020034set ::env(DIE_AREA) "0 0 900 600"
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020035
36set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
37
38set ::env(PL_BASIC_PLACEMENT) 1
Ahmed Ghazy548e5a72021-04-06 00:07:33 +020039set ::env(PL_TARGET_DENSITY) 0.05
Ahmed Ghazyd4ec2f02021-04-05 18:32:10 +020040
manarabdelatycf577da2021-09-17 18:20:33 +020041# Maximum layer used for routing is metal 4.
42# This is because this macro will be inserted in a top level (user_project_wrapper)
43# where the PDN is planned on metal 5. So, to avoid having shorts between routes
44# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.
kareem76e8a0f2022-02-25 10:13:53 -080045#
46# set ::env(GLB_RT_MAXLAYER) 5
47
48set ::env(RT_MAX_LAYER) {met4}
manarabdelatycf577da2021-09-17 18:20:33 +020049
50# You can draw more power domains if you need to
51set ::env(VDD_NETS) [list {vccd1}]
52set ::env(GND_NETS) [list {vssd1}]
53
54set ::env(DIODE_INSERTION_STRATEGY) 4
55# If you're going to use multiple power domains, then disable cvc run.
56set ::env(RUN_CVC) 1