Ahmed Ghazy | d4ec2f0 | 2021-04-05 18:32:10 +0200 | [diff] [blame] | 1 | # SPDX-FileCopyrightText: 2020 Efabless Corporation |
| 2 | # |
| 3 | # Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | # you may not use this file except in compliance with the License. |
| 5 | # You may obtain a copy of the License at |
| 6 | # |
| 7 | # http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | # |
| 9 | # Unless required by applicable law or agreed to in writing, software |
| 10 | # distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | # See the License for the specific language governing permissions and |
| 13 | # limitations under the License. |
| 14 | # SPDX-License-Identifier: Apache-2.0 |
| 15 | |
nofal | 6eecddc | 2021-10-12 22:46:36 +0200 | [diff] [blame] | 16 | set ::env(PDK) "sky130A" |
| 17 | set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" |
| 18 | |
Ahmed Ghazy | d4ec2f0 | 2021-04-05 18:32:10 +0200 | [diff] [blame] | 19 | set script_dir [file dirname [file normalize [info script]]] |
| 20 | |
| 21 | set ::env(DESIGN_NAME) user_proj_example |
| 22 | |
| 23 | set ::env(VERILOG_FILES) "\ |
manarabdelaty | cf577da | 2021-09-17 18:20:33 +0200 | [diff] [blame] | 24 | $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ |
Ahmed Ghazy | d4ec2f0 | 2021-04-05 18:32:10 +0200 | [diff] [blame] | 25 | $script_dir/../../verilog/rtl/user_proj_example.v" |
| 26 | |
manarabdelaty | cf577da | 2021-09-17 18:20:33 +0200 | [diff] [blame] | 27 | set ::env(DESIGN_IS_CORE) 0 |
| 28 | |
| 29 | set ::env(CLOCK_PORT) "wb_clk_i" |
Ahmed Ghazy | d4ec2f0 | 2021-04-05 18:32:10 +0200 | [diff] [blame] | 30 | set ::env(CLOCK_NET) "counter.clk" |
| 31 | set ::env(CLOCK_PERIOD) "10" |
| 32 | |
| 33 | set ::env(FP_SIZING) absolute |
Ahmed Ghazy | 548e5a7 | 2021-04-06 00:07:33 +0200 | [diff] [blame] | 34 | set ::env(DIE_AREA) "0 0 900 600" |
Ahmed Ghazy | d4ec2f0 | 2021-04-05 18:32:10 +0200 | [diff] [blame] | 35 | |
| 36 | set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg |
| 37 | |
| 38 | set ::env(PL_BASIC_PLACEMENT) 1 |
Ahmed Ghazy | 548e5a7 | 2021-04-06 00:07:33 +0200 | [diff] [blame] | 39 | set ::env(PL_TARGET_DENSITY) 0.05 |
Ahmed Ghazy | d4ec2f0 | 2021-04-05 18:32:10 +0200 | [diff] [blame] | 40 | |
manarabdelaty | cf577da | 2021-09-17 18:20:33 +0200 | [diff] [blame] | 41 | # Maximum layer used for routing is metal 4. |
| 42 | # This is because this macro will be inserted in a top level (user_project_wrapper) |
| 43 | # where the PDN is planned on metal 5. So, to avoid having shorts between routes |
| 44 | # in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. |
kareem | 76e8a0f | 2022-02-25 10:13:53 -0800 | [diff] [blame] | 45 | # |
| 46 | # set ::env(GLB_RT_MAXLAYER) 5 |
| 47 | |
| 48 | set ::env(RT_MAX_LAYER) {met4} |
manarabdelaty | cf577da | 2021-09-17 18:20:33 +0200 | [diff] [blame] | 49 | |
| 50 | # You can draw more power domains if you need to |
| 51 | set ::env(VDD_NETS) [list {vccd1}] |
| 52 | set ::env(GND_NETS) [list {vssd1}] |
| 53 | |
| 54 | set ::env(DIODE_INSERTION_STRATEGY) 4 |
| 55 | # If you're going to use multiple power domains, then disable cvc run. |
| 56 | set ::env(RUN_CVC) 1 |