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getziadzfb87c6f2022-05-12 15:26:53 -04001# ORDER PRGA Tapeout
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3This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.
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6A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)
7 - An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
8 - 24-track routing channel with L1 tracks
9 - Capable of implementing 16 out of 30 ISCAS'89 circuits
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manarabdelatyf2b6ea22021-04-20 19:07:40 +020011
Manar90842af2021-04-20 11:19:16 +020012[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
Manarc7bcaf92021-04-16 18:21:23 +020013
getziadzfb87c6f2022-05-12 15:26:53 -040014## Design
Manarc7bcaf92021-04-16 18:21:23 +020015
getziadzfb87c6f2022-05-12 15:26:53 -040016We used a three level hierarchical design:
Manarc7bcaf92021-04-16 18:21:23 +020017
getziadzfb87c6f2022-05-12 15:26:53 -040018- 1x Caravel user project wrapper
19 - 1x PRGA top
20 - 64x CLB tile