getziadz | fb87c6f | 2022-05-12 15:26:53 -0400 | [diff] [blame] | 1 | # ORDER PRGA Tapeout |
| 2 | |
| 3 | This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA. |
| 4 | |
| 5 | |
| 6 | A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array) |
| 7 | - An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing |
| 8 | - 24-track routing channel with L1 tracks |
| 9 | - Capable of implementing 16 out of 30 ISCAS'89 circuits |
| 10 | |
manarabdelaty | f2b6ea2 | 2021-04-20 19:07:40 +0200 | [diff] [blame] | 11 | |
Manar | 90842af | 2021-04-20 11:19:16 +0200 | [diff] [blame] | 12 | [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml) |
Manar | c7bcaf9 | 2021-04-16 18:21:23 +0200 | [diff] [blame] | 13 | |
getziadz | fb87c6f | 2022-05-12 15:26:53 -0400 | [diff] [blame] | 14 | ## Design |
Manar | c7bcaf9 | 2021-04-16 18:21:23 +0200 | [diff] [blame] | 15 | |
getziadz | fb87c6f | 2022-05-12 15:26:53 -0400 | [diff] [blame] | 16 | We used a three level hierarchical design: |
Manar | c7bcaf9 | 2021-04-16 18:21:23 +0200 | [diff] [blame] | 17 | |
getziadz | fb87c6f | 2022-05-12 15:26:53 -0400 | [diff] [blame] | 18 | - 1x Caravel user project wrapper |
| 19 | - 1x PRGA top |
| 20 | - 64x CLB tile |