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foss-eda-tools/third_party/shuttle/sky130/mpw-006/slot-037/718805cefc1d01086ec2e1acae6f8489e9affac7^!/.
commit
718805cefc1d01086ec2e1acae6f8489e9affac7
[log]
author
Ang Li <angl@princeton.edu>
Wed May 18 18:45:08 2022 -0400
committer
Ang Li <angl@princeton.edu>
Wed May 18 18:45:08 2022 -0400
tree
befb3dff6831d408a00da25cc6ad5e9b87d4a519
parent
d49c4ed32edd86ac319ec59f55d0a6ffbd0fda4e [diff]
[GDS/GL/Script] PRGA top with on hold violation

diff --git a/gds/top.gds.gz b/gds/top.gds.gz
index a57205d..a4cf7e3 100644
--- a/gds/top.gds.gz
+++ b/gds/top.gds.gz
Binary files differ

diff --git a/lef/top.lef b/lef/top.lef
index 4e16cb8..a844a72 100644
--- a/lef/top.lef
+++ b/lef/top.lef

@@ -1363,7 +1363,7 @@
       LAYER li1 ;
         RECT 5.520 10.795 2594.400 3187.925 ;
       LAYER met1 ;
-        RECT 5.520 10.640 2597.090 3188.080 ;
+        RECT 5.520 10.640 2596.630 3188.080 ;
       LAYER met2 ;
         RECT 6.990 3195.720 26.490 3196.410 ;
         RECT 27.330 3195.720 80.310 3196.410 ;
@@ -1413,8 +1413,8 @@
         RECT 2410.590 3195.720 2463.570 3196.410 ;
         RECT 2464.410 3195.720 2517.850 3196.410 ;
         RECT 2518.690 3195.720 2572.130 3196.410 ;
-        RECT 2572.970 3195.720 2597.060 3196.410 ;
-        RECT 6.990 4.280 2597.060 3195.720 ;
+        RECT 2572.970 3195.720 2596.600 3196.410 ;
+        RECT 6.990 4.280 2596.600 3195.720 ;
         RECT 6.990 3.670 185.190 4.280 ;
         RECT 186.030 3.670 556.410 4.280 ;
         RECT 557.250 3.670 927.630 4.280 ;
@@ -1422,7 +1422,7 @@
         RECT 1300.150 3.670 1670.530 4.280 ;
         RECT 1671.370 3.670 2042.210 4.280 ;
         RECT 2043.050 3.670 2413.430 4.280 ;
-        RECT 2414.270 3.670 2597.060 4.280 ;
+        RECT 2414.270 3.670 2596.600 4.280 ;
       LAYER met3 ;
         RECT 4.000 3167.120 2596.000 3188.005 ;
         RECT 4.400 3165.720 2595.600 3167.120 ;
@@ -1522,39 +1522,39 @@
         RECT 4.400 32.960 2595.600 34.360 ;
         RECT 4.000 10.715 2596.000 32.960 ;
       LAYER met4 ;
-        RECT 40.775 102.175 97.440 3128.505 ;
-        RECT 99.840 102.175 174.240 3128.505 ;
-        RECT 176.640 102.175 251.040 3128.505 ;
-        RECT 253.440 102.175 327.840 3128.505 ;
-        RECT 330.240 102.175 404.640 3128.505 ;
-        RECT 407.040 102.175 481.440 3128.505 ;
-        RECT 483.840 102.175 558.240 3128.505 ;
-        RECT 560.640 102.175 635.040 3128.505 ;
-        RECT 637.440 102.175 711.840 3128.505 ;
-        RECT 714.240 102.175 788.640 3128.505 ;
-        RECT 791.040 102.175 865.440 3128.505 ;
-        RECT 867.840 102.175 942.240 3128.505 ;
-        RECT 944.640 102.175 1019.040 3128.505 ;
-        RECT 1021.440 102.175 1095.840 3128.505 ;
-        RECT 1098.240 102.175 1172.640 3128.505 ;
-        RECT 1175.040 102.175 1249.440 3128.505 ;
-        RECT 1251.840 102.175 1326.240 3128.505 ;
-        RECT 1328.640 102.175 1403.040 3128.505 ;
-        RECT 1405.440 102.175 1479.840 3128.505 ;
-        RECT 1482.240 102.175 1556.640 3128.505 ;
-        RECT 1559.040 102.175 1633.440 3128.505 ;
-        RECT 1635.840 102.175 1710.240 3128.505 ;
-        RECT 1712.640 102.175 1787.040 3128.505 ;
-        RECT 1789.440 102.175 1863.840 3128.505 ;
-        RECT 1866.240 102.175 1940.640 3128.505 ;
-        RECT 1943.040 102.175 2017.440 3128.505 ;
-        RECT 2019.840 102.175 2094.240 3128.505 ;
-        RECT 2096.640 102.175 2171.040 3128.505 ;
-        RECT 2173.440 102.175 2247.840 3128.505 ;
-        RECT 2250.240 102.175 2324.640 3128.505 ;
-        RECT 2327.040 102.175 2401.440 3128.505 ;
-        RECT 2403.840 102.175 2478.240 3128.505 ;
-        RECT 2480.640 102.175 2481.865 3128.505 ;
+        RECT 40.775 102.855 97.440 3128.505 ;
+        RECT 99.840 102.855 174.240 3128.505 ;
+        RECT 176.640 102.855 251.040 3128.505 ;
+        RECT 253.440 102.855 327.840 3128.505 ;
+        RECT 330.240 102.855 404.640 3128.505 ;
+        RECT 407.040 102.855 481.440 3128.505 ;
+        RECT 483.840 102.855 558.240 3128.505 ;
+        RECT 560.640 102.855 635.040 3128.505 ;
+        RECT 637.440 102.855 711.840 3128.505 ;
+        RECT 714.240 102.855 788.640 3128.505 ;
+        RECT 791.040 102.855 865.440 3128.505 ;
+        RECT 867.840 102.855 942.240 3128.505 ;
+        RECT 944.640 102.855 1019.040 3128.505 ;
+        RECT 1021.440 102.855 1095.840 3128.505 ;
+        RECT 1098.240 102.855 1172.640 3128.505 ;
+        RECT 1175.040 102.855 1249.440 3128.505 ;
+        RECT 1251.840 102.855 1326.240 3128.505 ;
+        RECT 1328.640 102.855 1403.040 3128.505 ;
+        RECT 1405.440 102.855 1479.840 3128.505 ;
+        RECT 1482.240 102.855 1556.640 3128.505 ;
+        RECT 1559.040 102.855 1633.440 3128.505 ;
+        RECT 1635.840 102.855 1710.240 3128.505 ;
+        RECT 1712.640 102.855 1787.040 3128.505 ;
+        RECT 1789.440 102.855 1863.840 3128.505 ;
+        RECT 1866.240 102.855 1940.640 3128.505 ;
+        RECT 1943.040 102.855 2017.440 3128.505 ;
+        RECT 2019.840 102.855 2094.240 3128.505 ;
+        RECT 2096.640 102.855 2171.040 3128.505 ;
+        RECT 2173.440 102.855 2247.840 3128.505 ;
+        RECT 2250.240 102.855 2324.640 3128.505 ;
+        RECT 2327.040 102.855 2401.440 3128.505 ;
+        RECT 2403.840 102.855 2478.240 3128.505 ;
+        RECT 2480.640 102.855 2482.785 3128.505 ;
   END
 END top
 END LIBRARY

diff --git a/openlane/prga/config.tcl b/openlane/prga/config.tcl
index bb0df5a..7a9c0f3 100644
--- a/openlane/prga/config.tcl
+++ b/openlane/prga/config.tcl

@@ -50,9 +50,16 @@
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
 
-set ::env(PL_TARGET_DENSITY)            0.125
-set ::env(PL_RESIZER_MAX_WIRE_LENGTH)   250
-set ::env(CTS_CLK_MAX_WIRE_LENGTH)      250
+set ::env(PL_TARGET_DENSITY)                0.125
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN)     0.25
+set ::env(PL_RESIZER_MAX_CAP_MARGIN)        50
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN)       50
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH)       250
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN)    0.15
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN)       20
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN)      20
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH)      250
+set ::env(CTS_CLK_MAX_WIRE_LENGTH)          250
 
 # Maximum layer used for routing is metal 4.
 # This is because this macro will be inserted in a top level (user_project_wrapper) 

diff --git a/verilog/gl/top.v b/verilog/gl/top.v
index cb702f7..d128b5d 100644
--- a/verilog/gl/top.v
+++ b/verilog/gl/top.v
Binary files differ