Updated user_project_wrapper gds and config.tcl

gds/user_project_wrapper.gds.gz

diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 6cbd92f..58d81e8 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index ae8c8aa..11e34c6 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -41,7 +41,7 @@
 set ::env(CLOCK_PORT) "user_clock2"
 set ::env(CLOCK_NET) "top.prog_clk top.ipin_x0y1_0"
 
-set ::env(CLOCK_PERIOD) "1100"
+set ::env(CLOCK_PERIOD) "1000"
 
 #set ::env(FP_SIZING) absolute
 #set ::env(DIE_AREA) "0 0 2920 3520"
@@ -76,6 +76,8 @@
 set ::env(SYNTH_TOP_LEVEL) 1
 set ::env(PL_RANDOM_GLB_PLACEMENT) 1
 
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN)      20
+
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0