| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/tb/sar_10b/tr_sar.sch |
| **.subckt tr_sar |
| Vssa avss GND 0 |
| Vcca avdd GND 1.5 |
| Vinn vinn GND vsign |
| Vinp vinp GND vsigp |
| Vclk clk GND PULSE(0 1 10e-6 1e-9 1e-9 2e-6 4e-6) |
| Vcal cal GND 0 |
| xsar avdd dvdd dvss result_9_ result_8_ result_7_ result_6_ result_5_ result_4_ result_3_ result_2_ |
| + result_1_ result_0_ vinn avss clk vinp dvdd valid cal rstn sar |
| Vrstn rstn GND PULSE(0 1.2 10e-6 1e-9 1e-9 99e-6 100e-6) |
| Vssd dvss GND 0 |
| Vccd dvdd GND 1.2 |
| **** begin user architecture code |
| |
| .lib /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/sky130.lib.spice tt |
| .include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.spice |
| .include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_8.spice |
| .include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_3.spice |
| .include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.spice |
| .include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.spice |
| .include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.spice |
| .include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap_2.spice |
| *------------------------- |
| * normal setup |
| *------------------------- |
| .options method = gear |
| .options gmin = 1e-15 |
| .options abstol = 1e-14 |
| .options chtol = 1e-18 |
| .options reltol = 100e-6 |
| *------------------------- |
| |
| *------------------------- |
| * extracted logic setup |
| *------------------------- |
| *.options method = gear |
| *.options gmin = 1e-12 |
| *.options abstol = 1e-10 |
| *.options chtol = 1e-12 |
| *.options reltol = 100e-3 |
| *------------------------- |
| |
| |
| .ic v(xsar.vp)=0 |
| .ic v(xsar.vn)=0 |
| .ic v(xsar.outp)=0 |
| .ic v(xsar.outn)=0 |
| .ic v(xsar.comp)=0 |
| |
| .ic v(xsar.ctlp_0_)=0 |
| .ic v(xsar.ctlp_1_)=0 |
| .ic v(xsar.ctlp_2_)=0 |
| .ic v(xsar.ctlp_3_)=0 |
| .ic v(xsar.ctlp_4_)=0 |
| .ic v(xsar.ctlp_5_)=0 |
| .ic v(xsar.ctlp_6_)=0 |
| .ic v(xsar.ctlp_7_)=0 |
| .ic v(xsar.ctlp_8_)=0 |
| .ic v(xsar.ctlp_9_)=0 |
| |
| .ic v(xsar.ctln_0_)=0 |
| .ic v(xsar.ctln_1_)=0 |
| .ic v(xsar.ctln_2_)=0 |
| .ic v(xsar.ctln_3_)=0 |
| .ic v(xsar.ctln_4_)=0 |
| .ic v(xsar.ctln_5_)=0 |
| .ic v(xsar.ctln_6_)=0 |
| .ic v(xsar.ctln_7_)=0 |
| .ic v(xsar.ctln_8_)=0 |
| .ic v(xsar.ctln_9_)=0 |
| |
| |
| *.include /home/oe23ranan/lsi/mpw6/xschem/switches/bootstrapped_sw.sp |
| *.include /home/oe23ranan/lsi/mpw6/xschem/sar_10b/dac/dac_mom.pex.sp |
| *.include /home/oe23ranan/lsi/mpw6/xschem/sar_10b/sar/sar.pex.spice |
| *.include /home/oe23ranan/lsi/mpw6/xschem/sar_10b/sar/sar_mom.pex.spice |
| *.include /home/oe23ranan/lsi/mpw6/xschem/sar_10b/sar/sar_mim.pex.spice |
| *.include /home/oe23ranan/lsi/mpw6/xschem/sar_10b/control/sarlogic.ext.spice |
| *.include /home/oe23ranan/lsi/mpw6/xschem/sar_10b/sar/sar.pex.spice |
| .include /home/oe23ranan/lsi/mpw6/xschem/sar_10b/sar/sar.ext.spice |
| |
| .param MC_SWITCH=0 |
| .param vin=0 |
| .param vcm=0.75 |
| .param vsigp="{vcm + vin/2}" |
| .param vsign="{vcm - vin/2}" |
| |
| .tran 100e-9 68e-6 uic |
| |
| .control |
| |
| run |
| |
| meas tran d0 find v(xsar.xlogic.res0) at=62.5e-6 |
| meas tran d1 find v(xsar.xlogic.res1) at=62.5e-6 |
| meas tran d2 find v(xsar.xlogic.res2) at=62.5e-6 |
| meas tran d3 find v(xsar.xlogic.res3) at=62.5e-6 |
| meas tran d4 find v(xsar.xlogic.res4) at=62.5e-6 |
| meas tran d5 find v(xsar.xlogic.res5) at=62.5e-6 |
| meas tran d6 find v(xsar.xlogic.res6) at=62.5e-6 |
| meas tran d7 find v(xsar.xlogic.res7) at=62.5e-6 |
| meas tran d8 find v(xsar.xlogic.res8) at=62.5e-6 |
| meas tran d9 find v(xsar.xlogic.res9) at=62.5e-6 |
| |
| meas tran vpmax max xsar.vp |
| meas tran vpmin min xsar.vp |
| meas tran vpend find v(xsar.vp) at=62.5e-6 |
| |
| meas tran vnmax max xsar.vn |
| meas tran vnmin min xsar.vn |
| meas tran vnend find v(xsar.vn) at=62.5e-6 |
| |
| meas tran i_inp_max max(i_inp_abs) |
| |
| * Current measurements |
| let i_inp_abs = abs(vinp#branch) |
| let i_inn_abs = abs(vinn#branch) |
| let i_vcca_abs = abs(vcca#branch) |
| let i_vccd_abs = abs(vccd#branch) |
| |
| meas tran i_inp_max max i_inp_abs from=1u |
| meas tran i_inn_max max i_inn_abs from=1u |
| meas tran i_vcca_max max i_vcca_abs from=1u |
| meas tran i_vccd_max max i_vccd_abs from=1u |
| |
| |
| print i_inp_max |
| print i_inn_max |
| print i_vcca_max |
| print i_vccd_max |
| |
| print d0 |
| print d1 |
| print d2 |
| print d3 |
| print d4 |
| print d5 |
| print d6 |
| print d7 |
| print d8 |
| print d9 |
| |
| print vpmax |
| print vpmin |
| |
| print vnmax |
| print vnmin |
| |
| print vpend |
| print vnend |
| |
| echo Simulation Finished |
| echo ------------------- |
| shell date |
| echo ------------------- |
| |
| .endc |
| |
| * FET CORNERS |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/tt_all.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ff_all.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ss_all.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/tt.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ff.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ss.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/sf.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/fs.spice |
| |
| * TT + R + C |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/tt_rmax_cmax.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/tt_rmin_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/tt_rmax_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/tt_rmin_cmax.spice |
| |
| * FF + R + C |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ff_rmax_cmax.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ff_rmin_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ff_rmax_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ff_rmin_cmax.spice |
| |
| |
| * SS + R + C |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ss_rmax_cmax.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ss_rmin_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ss_rmax_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/ss_rmin_cmax.spice |
| |
| * SF + R + C |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/sf_rmax_cmax.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/sf_rmin_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/sf_rmax_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/sf_rmin_cmax.spice |
| |
| * FS + R + C |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/fs_rmax_cmax.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/fs_rmin_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/fs_rmax_cmin.spice |
| *.include /tmp/caravel_tutorial/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/corners/fs_rmin_cmax.spice |
| |
| **** end user architecture code |
| **.ends |
| |
| * expanding symbol: sar_10b/sar/sar.sym # of pins=12 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/sar/sar.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/sar/sar.sch |
| .subckt sar avdd dvdd dvss result_9_ result_8_ result_7_ result_6_ result_5_ result_4_ result_3_ |
| + result_2_ result_1_ result_0_ vinn avss clk vinp en valid cal rstn |
| *.iopin avss |
| *.iopin avdd |
| *.iopin dvss |
| *.iopin dvdd |
| *.ipin vinp |
| *.ipin vinn |
| *.opin |
| *+ result_9_,result_8_,result_7_,result_6_,result_5_,result_4_,result_3_,result_2_,result_1_,result_0_ |
| *.ipin clk |
| *.ipin en |
| *.opin valid |
| *.ipin cal |
| *.ipin rstn |
| xlat dvdd comp net1 dvss outn outp latch |
| xdn vn sample avdd avss vinn ctln_9_ ctln_8_ ctln_7_ ctln_6_ ctln_5_ ctln_4_ ctln_3_ ctln_2_ ctln_1_ |
| + ctln_0_ avss dac |
| xdp vp sample avdd avss vinp ctlp_9_ ctlp_8_ ctlp_7_ ctlp_6_ ctlp_5_ ctlp_4_ ctlp_3_ ctlp_2_ ctlp_1_ |
| + ctlp_0_ avdd dac |
| xcom avss avdd clkca outp vp outn vn trim_4_ trim_3_ trim_2_ trim_1_ trim_0_ trimb_4_ trimb_3_ |
| + trimb_2_ trimb_1_ trimb_0_ comparator |
| XC1_57_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_56_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_55_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_54_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_53_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_52_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_51_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_50_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_49_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_48_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_47_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_46_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_45_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_44_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_43_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_42_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_41_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_40_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_39_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_38_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_37_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_36_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_35_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_34_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_33_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_32_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_31_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_30_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_29_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_28_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_27_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_26_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_25_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_24_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_23_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_22_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_21_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_20_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_19_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_18_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_17_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_16_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_15_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_14_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_13_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_12_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_11_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_10_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_9_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_8_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_7_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_6_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_5_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_4_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_3_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_2_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_1_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC1_0_ avdd avss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_13_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_12_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_11_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_10_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_9_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_8_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_7_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_6_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_5_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_4_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_3_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_2_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_1_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| XC2_0_ dvdd dvss sky130_fd_pr__cap_mim_m3_2 W=12 L=12 MF=1 m=1 |
| xlogic trim_4_ trim_3_ trim_2_ trim_1_ trim_0_ trimb_4_ trimb_3_ trimb_2_ trimb_1_ trimb_0_ clkc |
| + comp cal en ctlp_9_ ctlp_8_ ctlp_7_ ctlp_6_ ctlp_5_ ctlp_4_ ctlp_3_ ctlp_2_ ctlp_1_ ctlp_0_ clk |
| + result_9_ result_8_ result_7_ result_6_ result_5_ result_4_ result_3_ result_2_ result_1_ result_0_ ctln_9_ |
| + ctln_8_ ctln_7_ ctln_6_ ctln_5_ ctln_4_ ctln_3_ ctln_2_ ctln_1_ ctln_0_ valid rstn sample dvdd dvss |
| + sarlogic |
| xbuf avdd clkc clkca avss buffer_lvt |
| .ends |
| |
| |
| * expanding symbol: sar_10b/latch/latch.sym # of pins=6 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/latch/latch.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/latch/latch.sch |
| .subckt latch vdd Q Qn vss R S |
| *.ipin S |
| *.ipin R |
| *.iopin vss |
| *.iopin vdd |
| *.opin Q |
| *.opin Qn |
| x1 vdd Qn Q vss inv_lvt |
| x2 vdd Q Qn vss inv_lvt |
| x3 vdd R net2 vss inv_lvt |
| x4 vdd S net1 vss inv_lvt |
| XM3 Qn net1 vss vss sky130_fd_pr__nfet_01v8_lvt L=0.4 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM1 Q net2 vss vss sky130_fd_pr__nfet_01v8_lvt L=0.4 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| .ends |
| |
| |
| * expanding symbol: sar_10b/dac/dac.sym # of pins=7 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/dac/dac.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/dac/dac.sch |
| .subckt dac out sample vdd vss vin ctl_9_ ctl_8_ ctl_7_ ctl_6_ ctl_5_ ctl_4_ ctl_3_ ctl_2_ ctl_1_ |
| + ctl_0_ dum |
| *.ipin vin |
| *.ipin sample |
| *.opin out |
| *.ipin ctl_9_,ctl_8_,ctl_7_,ctl_6_,ctl_5_,ctl_4_,ctl_3_,ctl_2_,ctl_1_,ctl_0_ |
| *.ipin dum |
| *.iopin vdd |
| *.iopin vss |
| xca out n6 n0 n5 n4 n2 ndum n3 n1 n7 n8 n9 carray |
| xswt out sample vdd vin vss bootstrapped_sw_hv |
| xidum dum vss vss vdd vdd ndum sky130_fd_sc_hd__inv_2 |
| xi0 ctl_0_ vss vss vdd vdd n0 sky130_fd_sc_hd__inv_2 |
| xi1 ctl_1_ vss vss vdd vdd n1 sky130_fd_sc_hd__inv_2 |
| xi2 ctl_2_ vss vss vdd vdd n2 sky130_fd_sc_hd__inv_2 |
| xi3 ctl_3_ vss vss vdd vdd n3 sky130_fd_sc_hd__inv_2 |
| xi4 ctl_4_ vss vss vdd vdd n4 sky130_fd_sc_hd__inv_2 |
| xi5 ctl_5_ vss vss vdd vdd n5 sky130_fd_sc_hd__inv_2 |
| xi6 ctl_6_ vss vss vdd vdd n6 sky130_fd_sc_hd__inv_2 |
| xi7 ctl_7_ vss vss vdd vdd n7 sky130_fd_sc_hd__inv_2 |
| xi8 ctl_8_ vss vss vdd vdd n8 sky130_fd_sc_hd__inv_2 |
| xi9 ctl_9_ vss vss vdd vdd n9 sky130_fd_sc_hd__inv_2 |
| .ends |
| |
| |
| * expanding symbol: sar_10b/comparator/comparator.sym # of pins=9 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/comparator/comparator.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/comparator/comparator.sch |
| .subckt comparator vss vdd clk outp vp outn vn trim_4_ trim_3_ trim_2_ trim_1_ trim_0_ trimb_4_ |
| + trimb_3_ trimb_2_ trimb_1_ trimb_0_ |
| *.ipin vn |
| *.ipin vp |
| *.ipin clk |
| *.iopin vdd |
| *.iopin vss |
| *.opin outp |
| *.opin outn |
| *.ipin trim_4_,trim_3_,trim_2_,trim_1_,trim_0_ |
| *.ipin trimb_4_,trimb_3_,trimb_2_,trimb_1_,trimb_0_ |
| XMdiff diff clk vss vss sky130_fd_pr__nfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=2 m=2 |
| XMinn in vn diff vss sky130_fd_pr__nfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XMinp ip vp diff vss sky130_fd_pr__nfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XMl4 outp outn vdd vdd sky130_fd_pr__pfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XMl3 outn outp vdd vdd sky130_fd_pr__pfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM3 outp clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM2 outn clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XMl1 outn outp in vss sky130_fd_pr__nfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XMl2 outp outn ip vss sky130_fd_pr__nfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4 ip clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM1 in clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| x2 in trim_4_ trim_3_ trim_2_ trim_1_ trim_0_ vss trim |
| x3 ip trimb_4_ trimb_3_ trimb_2_ trimb_1_ trimb_0_ vss trim |
| .ends |
| |
| |
| * expanding symbol: sar_10b/control/sarlogic.sym # of pins=15 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/control/sarlogic.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/control/sarlogic.sch |
| .subckt sarlogic trim_4_ trim_3_ trim_2_ trim_1_ trim_0_ trimb_4_ trimb_3_ trimb_2_ trimb_1_ |
| + trimb_0_ clkc comp cal en ctlp_9_ ctlp_8_ ctlp_7_ ctlp_6_ ctlp_5_ ctlp_4_ ctlp_3_ ctlp_2_ ctlp_1_ ctlp_0_ |
| + clk result_9_ result_8_ result_7_ result_6_ result_5_ result_4_ result_3_ result_2_ result_1_ result_0_ |
| + ctln_9_ ctln_8_ ctln_7_ ctln_6_ ctln_5_ ctln_4_ ctln_3_ ctln_2_ ctln_1_ ctln_0_ valid rstn sample dvdd dvss |
| *.opin clkc |
| *.opin ctlp_9_,ctlp_8_,ctlp_7_,ctlp_6_,ctlp_5_,ctlp_4_,ctlp_3_,ctlp_2_,ctlp_1_,ctlp_0_ |
| *.opin ctln_9_,ctln_8_,ctln_7_,ctln_6_,ctln_5_,ctln_4_,ctln_3_,ctln_2_,ctln_1_,ctln_0_ |
| *.opin sample |
| *.opin trim_4_,trim_3_,trim_2_,trim_1_,trim_0_ |
| *.opin trimb_4_,trimb_3_,trimb_2_,trimb_1_,trimb_0_ |
| *.ipin comp |
| *.ipin cal |
| *.ipin en |
| *.ipin clk |
| *.ipin |
| *+ result_9_,result_8_,result_7_,result_6_,result_5_,result_4_,result_3_,result_2_,result_1_,result_0_ |
| *.ipin valid |
| *.ipin rstn |
| *.iopin dvdd |
| *.iopin dvss |
| **** begin user architecture code |
| .include /home/oe23ranan/lsi/mpw6/xschem/sar_10b/control/cmos_cells_digital.sp |
| .include /home/oe23ranan/lsi/mpw6/xschem/sar_10b/control/sarlogic.sp |
| |
| **** end user architecture code |
| **** begin user architecture code |
| * Keep the sar_logic underscore name. Otherwise xschem gets confused. |
| Xuut dclk drstn den dcomp dcal dvalid dres0 dres1 dres2 dres3 dres4 dres5 dres6 dres7 dres8 dres9 |
| + dsamp dctlp0 dctlp1 dctlp2 dctlp3 dctlp4 dctlp5 dctlp6 dctlp7 dctlp8 dctlp9 dctln0 dctln1 dctln2 dctln3 |
| + dctln4 dctln5 dctln6 dctln7 dctln8 dctln9 dtrim0 dtrim1 dtrim2 dtrim3 dtrim4 dtrimb0 dtrimb1 dtrimb2 |
| + dtrimb3 dtrimb4 dclkc sar_logic |
| |
| .model adc_buff adc_bridge(in_low = 0.2 in_high=0.8) |
| .model dac_buff dac_bridge(out_high = 1.2) |
| |
| Aad [clk rstn en comp cal] [dclk drstn den dcomp dcal] adc_buff |
| Ada1 [dctlp0 dctlp1 dctlp2 dctlp3 dctlp4 dctlp5 dctlp6 dctlp7 dctlp8 dctlp9] [ctlp_0_ ctlp_1_ |
| + ctlp_2_ ctlp_3_ ctlp_4_ ctlp_5_ ctlp_6_ ctlp_7_ ctlp_8_ ctlp_9_] dac_buff |
| Ada2 [dctln0 dctln1 dctln2 dctln3 dctln4 dctln5 dctln6 dctln7 dctln8 dctln9] [ctln_0_ ctln_1_ |
| + ctln_2_ ctln_3_ ctln_4_ ctln_5_ ctln_6_ ctln_7_ ctln_8_ ctln_9_] dac_buff |
| Ada3 [dres0 dres1 dres2 dres3 dres4 dres5 dres6 dres7 dres8 dres9 dsamp dclkc] [res0 res1 res2 res3 |
| + res4 res5 res6 res7 res8 res9 sample clkc] dac_buff |
| Ada4 [dtrim4 dtrim3 dtrim2 dtrim1 dtrim0 dtrimb4 dtrimb3 dtrimb2 dtrimb1 dtrimb0] [trim_4_ trim_3_ |
| + trim_2_ trim_1_ trim_0_ trimb_4_ trimb_3_ trimb_2_ trimb_1_ trimb_0_ ] dac_buff |
| |
| **** end user architecture code |
| .ends |
| |
| |
| * expanding symbol: logic/buffer_lvt.sym # of pins=4 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/logic/buffer_lvt.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/logic/buffer_lvt.sch |
| .subckt buffer_lvt vdd in out vss |
| *.iopin vdd |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| XM1 net1 in vss vss sky130_fd_pr__nfet_01v8_lvt L=0.4 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM2 net1 in vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.4 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM3 out net1 vss vss sky130_fd_pr__nfet_01v8_lvt L=0.4 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4 out net1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.4 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| .ends |
| |
| |
| * expanding symbol: logic/inv_lvt.sym # of pins=4 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/logic/inv_lvt.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/logic/inv_lvt.sch |
| .subckt inv_lvt vdd in out vss |
| *.iopin vdd |
| *.iopin vss |
| *.ipin in |
| *.opin out |
| XM1 out in vss vss sky130_fd_pr__nfet_01v8_lvt L=0.4 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM2 out in vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.4 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| .ends |
| |
| |
| * expanding symbol: sar_10b/dac/carray.sym # of pins=12 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/dac/carray.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/dac/carray.sch |
| .subckt carray top n6 n0 n5 n4 n2 ndum n3 n1 n7 n8 n9 |
| *.iopin top |
| *.iopin n7 |
| *.iopin n6 |
| *.iopin n5 |
| *.iopin n4 |
| *.iopin n2 |
| *.iopin n0 |
| *.iopin ndum |
| *.iopin n3 |
| *.iopin n1 |
| *.iopin n8 |
| *.iopin n9 |
| xcdum top ndum unitcap |
| xc0 top n0 unitcap |
| xc1_1_ top n1 unitcap |
| xc1_0_ top n1 unitcap |
| xc2_3_ top n2 unitcap |
| xc2_2_ top n2 unitcap |
| xc2_1_ top n2 unitcap |
| xc2_0_ top n2 unitcap |
| xc3_7_ top n3 unitcap |
| xc3_6_ top n3 unitcap |
| xc3_5_ top n3 unitcap |
| xc3_4_ top n3 unitcap |
| xc3_3_ top n3 unitcap |
| xc3_2_ top n3 unitcap |
| xc3_1_ top n3 unitcap |
| xc3_0_ top n3 unitcap |
| xc4_15_ top n4 unitcap |
| xc4_14_ top n4 unitcap |
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| xc4_10_ top n4 unitcap |
| xc4_9_ top n4 unitcap |
| xc4_8_ top n4 unitcap |
| xc4_7_ top n4 unitcap |
| xc4_6_ top n4 unitcap |
| xc4_5_ top n4 unitcap |
| xc4_4_ top n4 unitcap |
| xc4_3_ top n4 unitcap |
| xc4_2_ top n4 unitcap |
| xc4_1_ top n4 unitcap |
| xc4_0_ top n4 unitcap |
| xc5_31_ top n5 unitcap |
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| xc5_29_ top n5 unitcap |
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| xc5_3_ top n5 unitcap |
| xc5_2_ top n5 unitcap |
| xc5_1_ top n5 unitcap |
| xc5_0_ top n5 unitcap |
| xc6_63_ top n6 unitcap |
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| .ends |
| |
| |
| * expanding symbol: switches/bootstrapped_sw_hv.sym # of pins=5 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/switches/bootstrapped_sw_hv.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/switches/bootstrapped_sw_hv.sch |
| .subckt bootstrapped_sw_hv out en vdd in vss |
| *.iopin out |
| *.ipin en |
| *.iopin vss |
| *.iopin vdd |
| *.iopin in |
| xinv1 vdd en enb vss inv_lvt |
| XCbs_4_ vbsh vbsl sky130_fd_pr__cap_mim_m3_1 W=5 L=5 MF=1 m=1 |
| XCbs_3_ vbsh vbsl sky130_fd_pr__cap_mim_m3_1 W=5 L=5 MF=1 m=1 |
| XCbs_2_ vbsh vbsl sky130_fd_pr__cap_mim_m3_1 W=5 L=5 MF=1 m=1 |
| XCbs_1_ vbsh vbsl sky130_fd_pr__cap_mim_m3_1 W=5 L=5 MF=1 m=1 |
| XCbs_0_ vbsh vbsl sky130_fd_pr__cap_mim_m3_1 W=5 L=5 MF=1 m=1 |
| XM3 vdd vg vbsh vbsh sky130_fd_pr__pfet_g5v0d10v5 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4 vg enb vbsh vbsh sky130_fd_pr__pfet_g5v0d10v5 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XMs out vg in vss sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM1 vbsl vg in vss sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM2 vbsl enb vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XMs2 vss enb vs vss sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XMs1 vs vdd vg vss sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| .ends |
| |
| |
| * expanding symbol: sar_10b/comparator/trim.sym # of pins=3 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/comparator/trim.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/comparator/trim.sch |
| .subckt trim drain d_4_ d_3_ d_2_ d_1_ d_0_ vss |
| *.iopin vss |
| *.ipin d_4_,d_3_,d_2_,d_1_,d_0_ |
| *.opin drain |
| XM4_7_ n4 d_4_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4_6_ n4 d_4_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4_5_ n4 d_4_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4_4_ n4 d_4_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4_3_ n4 d_4_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4_2_ n4 d_4_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4_1_ n4 d_4_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM4_0_ n4 d_4_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM3_3_ n3 d_3_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM3_2_ n3 d_3_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM3_1_ n3 d_3_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM3_0_ n3 d_3_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM2_1_ n2 d_2_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM2_0_ n2 d_2_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM1 n1 d_1_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| XM0 n0 d_0_ vss vss sky130_fd_pr__nfet_01v8_lvt L=0.3 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' |
| + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' |
| + sa=0 sb=0 sd=0 mult=1 m=1 |
| x4_7_ drain n4 trimcap |
| x4_6_ drain n4 trimcap |
| x4_5_ drain n4 trimcap |
| x4_4_ drain n4 trimcap |
| x4_3_ drain n4 trimcap |
| x4_2_ drain n4 trimcap |
| x4_1_ drain n4 trimcap |
| x4_0_ drain n4 trimcap |
| x3_3_ drain n3 trimcap |
| x3_2_ drain n3 trimcap |
| x3_1_ drain n3 trimcap |
| x3_0_ drain n3 trimcap |
| x2_1_ drain n2 trimcap |
| x2_0_ drain n2 trimcap |
| x1 drain n1 trimcap |
| x0 drain n0 trimcap |
| .ends |
| |
| |
| * expanding symbol: sar_10b/unitcap/unitcap.sym # of pins=2 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/unitcap/unitcap.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/unitcap/unitcap.sch |
| .subckt unitcap cp cn |
| *.iopin cp |
| *.iopin cn |
| C1 cp cn 2.6f m=1 |
| .ends |
| |
| |
| * expanding symbol: sar_10b/comparator/trimcap.sym # of pins=2 |
| ** sym_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/comparator/trimcap.sym |
| ** sch_path: /home/oe23ranan/lsi/mpw6/xschem/sar_10b/comparator/trimcap.sch |
| .subckt trimcap cp cn |
| *.iopin cp |
| *.iopin cn |
| c0 net1 cn 2f m=1 |
| c1 cp net1 1f m=1 |
| .ends |
| |
| .GLOBAL GND |
| .end |
