Bit mismatch solved
diff --git a/verilog/dv/FPU_Single/FPU_Single_tb.v b/verilog/dv/FPU_Single/FPU_Single_tb.v index e7176c3..d538969 100644 --- a/verilog/dv/FPU_Single/FPU_Single_tb.v +++ b/verilog/dv/FPU_Single/FPU_Single_tb.v
@@ -124,7 +124,7 @@ wait(mprj_io_0 == 32'h00000002); */ // Observe Output pins for Fmul - + /* wait(mprj_io_0 == 32'h4342C190); wait(mprj_io_0 == 32'hC128167B); wait(mprj_io_0 == 32'hCD883D35); @@ -133,6 +133,24 @@ wait(mprj_io_0 == 32'h8292A6E7); wait(mprj_io_0 == 32'hBA56B228); wait(mprj_io_0 == 32'hB53C1C1E); + */ + // Observe Output pins for Fadd/fsub + + wait(mprj_io_0 == 32'h421FAF69); + wait(mprj_io_0 == 32'hC05FDF3C); + wait(mprj_io_0 == 32'hC636EF85); + wait(mprj_io_0 == 32'hC3F0D1EC); + wait(mprj_io_0 == 32'hC204B540); + wait(mprj_io_0 == 32'h444BBD70); + wait(mprj_io_0 == 32'h3EB2007E); + wait(mprj_io_0 == 32'hBCA715C9); + wait(mprj_io_0 == 32'hC1E45772); + wait(mprj_io_0 == 32'hC0EBB646); + wait(mprj_io_0 == 32'h470BC01F); + wait(mprj_io_0 == 32'hC3FE6148); + wait(mprj_io_0 == 32'h4268AB02); + wait(mprj_io_0 == 32'hC45CE8F6); + wait(mprj_io_0 == 32'hBEB465E8); $display("MPRJ-IO state = %h", mprj_io_0[31:0]);
diff --git a/verilog/dv/asm/fadd_fsub.s b/verilog/dv/asm/fadd_fsub.s index 1305af3..ccbea28 100644 --- a/verilog/dv/asm/fadd_fsub.s +++ b/verilog/dv/asm/fadd_fsub.s
@@ -20,37 +20,37 @@ _start: - li x5, 0x40B60EBF + li x5, 0x40B60EBF // 1 fmv.w.x f0, x5 - li x5, 0x4208ED91 + li x5, 0x4208ED91 // 2 fmv.w.x f1, x5 - li x5, 0x3FF78D50 + li x5, 0x3FF78D50 // 3 fmv.w.x f2, x5 - li x5, 0xC0ADD2F2 + li x5, 0xC0ADD2F2 // 4 fmv.w.x f3, x5 - li x5, 0xC6B97C00 + li x5, 0xC6B97C00 // 5 fmv.w.x f4, x5 - li x5, 0x463C087B + li x5, 0x463C087B // 6 fmv.w.x f5, x5 - li x5, 0x4158F5C3 + li x5, 0x4158F5C3 // 7 fmv.w.x f6, x5 - li x5, 0xC3F7999A + li x5, 0xC3F7999A //8 fmv.w.x f7, x5 - li x5, 0xC236B021 + li x5, 0xC236B021 // 9 fmv.w.x f8, x5 - li x5, 0x4147EB85 + li x5, 0x4147EB85 // 10 fmv.w.x f9, x5 - li x5, 0x44545333 + li x5, 0x44545333 // 11 fmv.w.x f10, x5 - li x5, 0xC2095C29 + li x5, 0xC2095C29 // 12 fmv.w.x f11, x5 - li x5, 0x3EB33333 + li x5, 0x3EB33333 // 13 fmv.w.x f12, x5 - li x5, 0xBB195AAF + li x5, 0xBB195AAF //14 fmv.w.x f13, x5 - li x5, 0x380FDD58 + li x5, 0x380FDD58 //15 fmv.w.x f14, x5 - li x5, 0xBCA75DB8 + li x5, 0xBCA75DB8 //16 fmv.w.x f15, x5 fadd.s f16, f1, f0 fadd.s f17, f3, f2
diff --git a/verilog/rtl/FPU/Dec_gpr_ctl.v b/verilog/rtl/FPU/Dec_gpr_ctl.v index ad2c597..babaa54 100644 --- a/verilog/rtl/FPU/Dec_gpr_ctl.v +++ b/verilog/rtl/FPU/Dec_gpr_ctl.v
@@ -46,7 +46,7 @@ integer p; always @(*) begin if(rst_l == 1'b0) begin - w0v = 32'h00000000; + w0v = 31'h00000000; for(p=1; p<32; p=p+1) begin gpr_in[p] = {XLEN{1'b0}}; end
diff --git a/verilog/rtl/FPU/FPU_decode.v b/verilog/rtl/FPU/FPU_decode.v index b340c96..989d8c0 100644 --- a/verilog/rtl/FPU/FPU_decode.v +++ b/verilog/rtl/FPU/FPU_decode.v
@@ -101,7 +101,7 @@ always @(posedge clk) begin if(rst_l == 1'b0 | illegal_config) begin - control_signals_r <= 114'h0; + control_signals_r <= 115'h0; end else @@ -113,7 +113,7 @@ end else if((~valid_execution) | ((~fpu_active) & (fpu_complete))) begin - control_signals_r <= 114'h0; + control_signals_r <= 115'h0; end else begin
diff --git a/verilog/rtl/FPU/beh_lib.v b/verilog/rtl/FPU/beh_lib.v index 32a2894..67b166f 100644 --- a/verilog/rtl/FPU/beh_lib.v +++ b/verilog/rtl/FPU/beh_lib.v
@@ -18,7 +18,7 @@ end else always @(posedge clk or negedge rst_l) if (rst_l == 0) - dout[WIDTH - 1:0] <= 0; + dout[WIDTH - 1:0] <= {{WIDTH{0}}; else dout[WIDTH - 1:0] <= din[WIDTH - 1:0]; endgenerate @@ -707,4 +707,4 @@ wire SE; assign SE = 0; assign l1clk = clk; -endmodule \ No newline at end of file +endmodule
diff --git a/verilog/rtl/FPU/iccm_controller.v b/verilog/rtl/FPU/iccm_controller.v index 611396f..21544ac 100644 --- a/verilog/rtl/FPU/iccm_controller.v +++ b/verilog/rtl/FPU/iccm_controller.v
@@ -71,7 +71,7 @@ ctrl_fsm_ns = LOAD; else ctrl_fsm_ns = DONE; - default: ctrl_fsm_ns = RESET; + //default: ctrl_fsm_ns = RESET; endcase end assign rx_byte_d = rx_byte_i; @@ -82,7 +82,7 @@ always @(posedge clk_i or negedge rst_ni) if (!rst_ni) begin we_q <= 1'b0; - addr_q <= 13'b0000000000000; + addr_q <= 14'b00000000000000; rx_byte_q0 <= 8'b00000000; rx_byte_q1 <= 8'b00000000; rx_byte_q2 <= 8'b00000000;
diff --git a/verilog/rtl/FPU/uart_rx_prog.v b/verilog/rtl/FPU/uart_rx_prog.v index 7af5031..7a046df 100644 --- a/verilog/rtl/FPU/uart_rx_prog.v +++ b/verilog/rtl/FPU/uart_rx_prog.v
@@ -53,8 +53,8 @@ s_IDLE : begin r_Rx_DV <= 1'b0; - r_Clock_Count <= 0; - r_Bit_Index <= 0; + r_Clock_Count <= 16'h0000; + r_Bit_Index <= 3'b000; if (r_Rx_Data == 1'b0) // Start bit detected r_SM_Main <= s_RX_START_BIT; @@ -69,7 +69,7 @@ begin if (r_Rx_Data == 1'b0) begin - r_Clock_Count <= 0; // reset counter, found the middle + r_Clock_Count <= 16'h0000; // reset counter, found the middle r_SM_Main <= s_RX_DATA_BITS; end else @@ -77,7 +77,7 @@ end else begin - r_Clock_Count <= r_Clock_Count + 1; + r_Clock_Count <= r_Clock_Count + 16'd1; r_SM_Main <= s_RX_START_BIT; end end // case: s_RX_START_BIT @@ -88,23 +88,23 @@ begin if (r_Clock_Count < CLKS_PER_BIT-1) begin - r_Clock_Count <= r_Clock_Count + 1; + r_Clock_Count <= r_Clock_Count + 16'd1; r_SM_Main <= s_RX_DATA_BITS; end else begin - r_Clock_Count <= 0; + r_Clock_Count <= 16'h0000; r_Rx_Byte[r_Bit_Index] <= r_Rx_Data; // Check if we have received all bits if (r_Bit_Index < 7) begin - r_Bit_Index <= r_Bit_Index + 1; + r_Bit_Index <= r_Bit_Index + 3'b001; r_SM_Main <= s_RX_DATA_BITS; end else begin - r_Bit_Index <= 0; + r_Bit_Index <= 3'b000; r_SM_Main <= s_RX_STOP_BIT; end end @@ -117,13 +117,13 @@ // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish if (r_Clock_Count < CLKS_PER_BIT-1) begin - r_Clock_Count <= r_Clock_Count + 1; + r_Clock_Count <= r_Clock_Count + 16'd1; r_SM_Main <= s_RX_STOP_BIT; end else begin r_Rx_DV <= 1'b1; - r_Clock_Count <= 0; + r_Clock_Count <= 16'h0000; r_SM_Main <= s_CLEANUP; end end // case: s_RX_STOP_BIT
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 4e5125e..6392c92 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -97,7 +97,7 @@ // Ouptut at LA bits [63:32] assign la_data_out[31:0] = 32'h00000000; assign la_data_out[63:32] = (&la_oenb[63:32]) ? FPU_sp_result : 32'h00000000; - assign la_data_out[127:64] = {(127-64){1'b0}}; + assign la_data_out[127:64] = {64{1'b0}}; // Assuming LA probes [65:64] are for controlling the count clk & reset assign clk = (~la_oenb[64]) ? la_data_in[64] : wb_clk_i;