First RTL files are added
diff --git a/verilog/rtl/FPU/Dec_gpr_ctl.v b/verilog/rtl/FPU/Dec_gpr_ctl.v
new file mode 100644
index 0000000..8f7b702
--- /dev/null
+++ b/verilog/rtl/FPU/Dec_gpr_ctl.v
@@ -0,0 +1,64 @@
+`include "beh_lib.v"
+
+module dec_gpr_ctl
+#(
+ parameter XLEN = 32
+ ) (
+
+ input rden0,
+ input rden1,
+
+ input [4:0] raddr0, // logical read addresses
+ input [4:0] raddr1,
+
+ input wen0, // write enable
+ input [4:0] waddr0, // write address
+ input [XLEN-1:0] wd0, // write data
+
+ input clk,
+ input rst_l,
+
+ output [XLEN-1:0] rd0, // read data
+ output [XLEN-1:0] rd1,
+
+ input scan_mode
+);
+
+ wire [XLEN-1:0] gpr_out [31:1]; // 31 x 32 bit GPRs
+ reg [XLEN-1:0] gpr_in [31:1];
+ reg [31:1] w0v;
+ wire [31:1] gpr_wr_en;
+
+
+ // GPR Write Enables
+ assign gpr_wr_en[31:1] = (rst_l == 1'b0) ? {31{1'b1}} : (w0v[31:1]);
+
+generate
+ for (genvar j=1; j<32; j=j+1)
+ rvdffe #(32) gprff (.*, .en(gpr_wr_en[j]), .din(gpr_in[j][XLEN-1:0]), .dout(gpr_out[j][XLEN-1:0]));
+endgenerate
+
+
+ // GPR Read logic
+ assign rd0 = (rst_l == 1'b0) ? {XLEN{1'b0}} : ((rden0 == 1'b1) & (raddr0 != 5'b00000)) ? gpr_out[raddr0][XLEN-1:0] : {XLEN{1'b0}};
+ assign rd1 = (rst_l == 1'b0) ? {XLEN{1'b0}} : ((rden1 == 1'b1) & (raddr1 != 5'b00000)) ? gpr_out[raddr1][XLEN-1:0] : {XLEN{1'b0}};
+
+ // GPR write logic
+integer j;
+ always @(*) begin
+ if(rst_l == 1'b0) begin
+ w0v = 32'h00000000;
+ for(j=1; j<32; j=j+1) begin
+ gpr_in[j] = {XLEN{1'b0}};
+ end
+ end
+ else begin
+ for (int j=1; j<32; j=j+1) begin
+ w0v[j] = wen0 & (waddr0[4:0] == j );
+ gpr_in[j] = ({XLEN{w0v[j]}} & wd0[XLEN-1:0]);
+ end
+ end
+ end
+
+endmodule
+
diff --git a/verilog/rtl/FPU/Execution.v b/verilog/rtl/FPU/Execution.v
new file mode 100644
index 0000000..e6d01fc
--- /dev/null
+++ b/verilog/rtl/FPU/Execution.v
@@ -0,0 +1,65 @@
+`include "FPU_exu.v"
+
+module Execution(clk,rst_l,RS1_d,RS2_d,result,Flag_ADDI,Flag_LI,Activation_Signal,Flag_Reset,fpu_active,illegal_config,valid_execution,fs1_data,fs2_data,fs3_data,sfpu_op,fpu_pre,fpu_rounding,float_control,fpu_result_1,S_flag,dec_i0_rs1_en_d,dec_i0_rs2_en_d,IV_exception,fpu_complete,fpu_sel);
+ input clk,rst_l,Flag_ADDI,Flag_LI,Flag_Reset,fpu_active,illegal_config,valid_execution,dec_i0_rs1_en_d,dec_i0_rs2_en_d;
+ input [31:0]RS1_d,RS2_d;
+ input [15:0]fs1_data,fs2_data,fs3_data;
+ input [23:0]sfpu_op;
+ input [2:0]fpu_pre,fpu_rounding;
+ input [3:0]float_control;
+ input [2:0]fpu_sel;
+ output reg[31:0]result;
+ output reg Activation_Signal;
+ output [15:0]fpu_result_1;
+ output [4:0]S_flag;
+ output IV_exception;
+ output fpu_complete;
+
+ wire [31:0]result_w;
+ wire complete;
+ wire [31:0]fpu_result_rd_w;
+
+ FPU_exu FPU_Execution(
+ .clk(clk),
+ .rst_l(rst_l),
+ .scan_mode(1'b0),
+ .valid_execution(valid_execution),
+ .float_control(float_control),
+ .sfpu_op(sfpu_op),
+ .fpu_rnd(fpu_rounding),
+ .fpu_pre(fpu_pre),
+ .dec_i0_rs1_en_d(dec_i0_rs1_en_d), // Qualify GPR RS1 data
+ .dec_i0_rs2_en_d(dec_i0_rs2_en_d), // Qualify GPR RS2 data
+ .gpr_i0_rs1_d(RS1_d), // DEC data gpr
+ .gpr_i0_rs2_d(RS2_d), // DEC data gpr
+ .fs1_data(fs1_data),
+ .fs2_data(fs2_data),
+ .fs3_data(fs3_data),
+ .fpu_sel(fpu_sel),
+ .fpu_result_1(fpu_result_1), // single cycle result
+ .fpu_result_rd(fpu_result_rd_w), // integer result
+ .fpu_complete(fpu_complete),
+ .sflags(S_flag),
+ .IV_exception(IV_exception)
+ );
+
+ assign result_w = (~rst_l) ? 32'h00000000 : (Flag_ADDI | Flag_LI) ? (RS1_d + RS2_d) : 32'h00000000;
+ assign complete = (~rst_l) ? 1'b0 : (Flag_ADDI | Flag_LI | Flag_Reset) ? 1'b1 : 1'b0;
+
+ always @(posedge clk)
+ begin
+ if(~rst_l)
+ begin
+ result = 32'h00000000;
+ Activation_Signal = 1'b0;
+ end
+
+ else
+ begin
+ result = result_w;
+ Activation_Signal = complete;
+ end
+ end
+
+
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v b/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v
new file mode 100644
index 0000000..e83f122
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v
@@ -0,0 +1,70 @@
+ //this module is responsible fo rperdfiming the post normalization of the generted result from addition of mantissas
+//`include "F_LZD_Main.v"
+
+module FMADD_Post_Normalization_Add_Sub(Post_Normalization_input_Mantissa,Post_Normalization_input_exponent,Post_Normalization_input_Carry,Post_Normalization_input_Eff_sub,Post_Normalization_input_Eff_add,Post_Normalization_input_Guard,Post_Normalization_input_Round,Post_Normalization_input_Sticky,Post_Normalization_output_Guard,Post_Normalization_output_Round,Post_Normalization_output_Sticky,Post_Normalization_output_Mantissa,Post_Normalization_output_exponent );
+
+//defination of parameters
+parameter std = 31;
+parameter man = 22;
+parameter exp = 7;
+
+//declaration of putptu ports
+input [man+man+3:0] Post_Normalization_input_Mantissa;
+input [exp:0] Post_Normalization_input_exponent;
+input Post_Normalization_input_Carry,Post_Normalization_input_Eff_sub,Post_Normalization_input_Eff_add,Post_Normalization_input_Guard,Post_Normalization_input_Round,Post_Normalization_input_Sticky;
+
+//declaration of putptu ports
+output [man + 1 :0] Post_Normalization_output_Mantissa;
+output [exp+1:0] Post_Normalization_output_exponent;
+output Post_Normalization_output_Guard,Post_Normalization_output_Round,Post_Normalization_output_Sticky;
+
+//declaration of interim wires
+wire [exp:0] Post_Normaliaation_Bit_Shamt_interim;
+wire [exp:0] Post_Normaliaation_Bit_Shamt_1;
+wire [23:0] Post_Normaliaation_Bit_input_LZD;
+wire [4:0] Post_Normaliaation_Bit_output_LZD;
+wire Post_Normaliaation_Bit_exp_LZD_Comp;
+wire [exp:0] Post_Normaliaation_Bit_Shift_Amount;
+wire [man+man+3:0] Post_Normalization_Shifter_Output_Sub,Post_Normalization_Shifter_Output_add,Post_Normalization_Shifter_input_add;
+wire [man+man+3:0] Post_Normalization_Mantissa_interim_48;
+wire [exp:0] Post_Normaliaation_EFF_Sub_interim_Exponent;
+wire [exp+1:0] Post_Normaliaation_EFF_add_interim_Exponent;
+
+
+
+//instantition of LZD
+ FMADD_PN_LZD m2 (
+ .FMADD_PN_LZD_input_man_48 ( Post_Normaliaation_Bit_input_LZD ),
+ .FMADD_PN_LZD_output_pos ( Post_Normaliaation_Bit_output_LZD)
+ ) ;
+
+
+//main functionality
+
+//subtraction lane
+assign Post_Normaliaation_Bit_Shamt_interim = Post_Normalization_input_exponent - 1'b1;
+assign Post_Normaliaation_Bit_Shamt_1 = (Post_Normalization_input_Eff_sub) ? Post_Normaliaation_Bit_Shamt_interim : 8'h00;
+assign Post_Normaliaation_Bit_input_LZD = (Post_Normalization_input_Eff_sub) ? Post_Normalization_input_Mantissa[man+man+3:man+2] : {(man+2){1'b0}};
+assign Post_Normaliaation_Bit_exp_LZD_Comp = Post_Normalization_input_exponent > Post_Normaliaation_Bit_output_LZD;
+assign Post_Normaliaation_Bit_Shift_Amount = (Post_Normaliaation_Bit_exp_LZD_Comp) ? { {exp-4 {1'b0}},Post_Normaliaation_Bit_output_LZD} : Post_Normaliaation_Bit_Shamt_1 ;
+assign Post_Normalization_Shifter_Output_Sub = Post_Normalization_input_Mantissa << Post_Normaliaation_Bit_Shift_Amount;
+assign Post_Normaliaation_EFF_Sub_interim_Exponent = Post_Normalization_input_exponent - Post_Normaliaation_Bit_Shift_Amount ;
+
+
+//additio lanse
+assign Post_Normaliaation_EFF_add_interim_Exponent = {1'b0,Post_Normalization_input_exponent} + Post_Normalization_input_Carry ;
+assign Post_Normalization_Shifter_input_add = (Post_Normalization_input_Eff_add) ? Post_Normalization_input_Mantissa : {(man+man+4){1'b0}};
+assign Post_Normalization_Shifter_Output_add = (Post_Normalization_input_Carry) ? { Post_Normalization_input_Carry,Post_Normalization_Shifter_input_add[man+man+3:1] } : Post_Normalization_Shifter_input_add[man+man+3:0] ;
+
+//Output Selestion and Round bits extarcion
+assign Post_Normalization_Mantissa_interim_48 = (Post_Normalization_input_Eff_sub) ? Post_Normalization_Shifter_Output_Sub : Post_Normalization_Shifter_Output_add ;
+
+assign Post_Normalization_output_Mantissa = Post_Normalization_Mantissa_interim_48[man+man+3:man+2];
+assign Post_Normalization_output_Round = Post_Normalization_Mantissa_interim_48[man] ;
+assign Post_Normalization_output_Guard = Post_Normalization_Mantissa_interim_48[man+1];
+assign Post_Normalization_output_Sticky = ( (|Post_Normalization_Mantissa_interim_48[man-1:0]) | Post_Normalization_input_Guard | Post_Normalization_input_Round | Post_Normalization_input_Sticky);
+assign Post_Normalization_output_exponent = (Post_Normalization_input_Eff_sub) ? {1'b0,Post_Normaliaation_EFF_Sub_interim_Exponent} : Post_Normaliaation_EFF_add_interim_Exponent;
+
+
+endmodule
+
diff --git a/verilog/rtl/FPU/FMADD_Exponent_Matching.v b/verilog/rtl/FPU/FMADD_Exponent_Matching.v
new file mode 100644
index 0000000..3ef15c4
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_Exponent_Matching.v
@@ -0,0 +1,74 @@
+//module is responsible for matching the exponents for addition
+
+module FMADD_Exponent_Matching (Exponent_Matching_input_Sign_A,Exponent_Matching_input_Sign_B,Exponent_Matching_input_Exp_A,Exponent_Matching_input_Exp_B,Exponent_Matching_input_Mantissa_A,Exponent_Matching_input_Mantissa_B,Exponent_Matching_input_opcode,Exponent_Matching_output_Mantissa_A,Exponent_Matching_output_Mantissa_B,Exponent_Matching_output_Exp,Exponent_Matching_output_Guard,Exponent_Matching_output_Round,Exponent_Matching_output_Sticky,Exponent_Matching_output_Sign,Exponent_Matching_output_Eff_Sub,Exponent_Matching_output_Eff_add);
+
+//defination of prameters
+parameter std =31;
+parameter man =22;
+parameter exp =7;
+
+//declaration of inptu port
+input Exponent_Matching_input_Sign_A,Exponent_Matching_input_Sign_B;
+input [exp:0] Exponent_Matching_input_Exp_A,Exponent_Matching_input_Exp_B;
+input [man+man+3:0] Exponent_Matching_input_Mantissa_A,Exponent_Matching_input_Mantissa_B;
+
+// opcode[0] = Fadd
+// opcode[1] = Fsub
+input [1:0] Exponent_Matching_input_opcode;
+
+//declaration of putptu ports
+output Exponent_Matching_output_Sign;
+output [man+man+3:0] Exponent_Matching_output_Mantissa_A,Exponent_Matching_output_Mantissa_B;
+output [exp:0] Exponent_Matching_output_Exp;
+output Exponent_Matching_output_Guard,Exponent_Matching_output_Round,Exponent_Matching_output_Sticky,Exponent_Matching_output_Eff_Sub,Exponent_Matching_output_Eff_add;
+
+//main funtionality
+
+//declaration for wires
+
+wire Exponent_Matching_Bit_Exp_A_ge_B,Exponent_Matching_Bit_Exp_A_gt_B,Exponent_Matching_Bit_Exp_A_eq_B,Exponent_Matching_Bit_Man_a_ge_Man_B,Exponent_Matching_Bit_Eff_sub,Exponent_Matching_Bit_Eff_add;
+wire [4*man+7:0] Exponent_Matching_Shifter_input,Exponent_Matching_Shifter_output;
+wire [exp:0] Exponent_Matching_Exp_Sub_input_1 , Exponent_Matching_Exp_Sub_input_2;
+wire [exp:0] Exponent_Matching_Shif_Amount;
+
+//check for exp_A >= exp_B
+assign Exponent_Matching_Bit_Exp_A_gt_B = Exponent_Matching_input_Exp_A > Exponent_Matching_input_Exp_B;
+assign Exponent_Matching_Bit_Exp_A_eq_B = Exponent_Matching_input_Exp_A == Exponent_Matching_input_Exp_B;
+assign Exponent_Matching_Bit_Exp_A_ge_B = Exponent_Matching_Bit_Exp_A_gt_B | Exponent_Matching_Bit_Exp_A_eq_B;
+
+//check for Manstissa _A >= Mantisa_B
+assign Exponent_Matching_Bit_Man_a_ge_Man_B = Exponent_Matching_input_Mantissa_A >= Exponent_Matching_input_Mantissa_B;
+
+//check for true subtraction or ture additions
+assign Exponent_Matching_Bit_Eff_sub = ( ( Exponent_Matching_input_Sign_A ^ Exponent_Matching_input_Sign_B) & ( Exponent_Matching_input_opcode[0] ) ) | ( (~(Exponent_Matching_input_Sign_A ^ Exponent_Matching_input_Sign_B)) & ( Exponent_Matching_input_opcode[1] ) );
+assign Exponent_Matching_output_Eff_Sub = Exponent_Matching_Bit_Eff_sub;
+assign Exponent_Matching_Bit_Eff_add = ( ( Exponent_Matching_input_Sign_A ^ Exponent_Matching_input_Sign_B) & ( Exponent_Matching_input_opcode[1] ) ) | ( (~(Exponent_Matching_input_Sign_A ^ Exponent_Matching_input_Sign_B)) & ( Exponent_Matching_input_opcode[0] ) );
+assign Exponent_Matching_output_Eff_add = Exponent_Matching_Bit_Eff_add;
+//shifter circutrary input
+assign Exponent_Matching_Shifter_input = ( Exponent_Matching_Bit_Exp_A_ge_B ) ? { Exponent_Matching_input_Mantissa_B , {(2*man)+4{1'b0}}} : { Exponent_Matching_input_Mantissa_A , {(2*man)+4{1'b0}}} ;
+
+//logic for determination of shift amount and slection of finalized exponent
+assign Exponent_Matching_Exp_Sub_input_1 = ( Exponent_Matching_Bit_Exp_A_ge_B ) ? Exponent_Matching_input_Exp_A : Exponent_Matching_input_Exp_B;
+assign Exponent_Matching_Exp_Sub_input_2 = ( ~Exponent_Matching_Bit_Exp_A_ge_B ) ? Exponent_Matching_input_Exp_A : Exponent_Matching_input_Exp_B;
+assign Exponent_Matching_Shif_Amount = Exponent_Matching_Exp_Sub_input_1 -Exponent_Matching_Exp_Sub_input_2;
+
+//shifting circutary
+assign Exponent_Matching_Shifter_output = Exponent_Matching_Shifter_input >> Exponent_Matching_Shif_Amount ;
+
+//decision for sign of the Addition Lane's output
+assign Exponent_Matching_output_Sign = ( Exponent_Matching_Bit_Eff_add | ( Exponent_Matching_Bit_Exp_A_gt_B & Exponent_Matching_Bit_Eff_sub ) | ( ( Exponent_Matching_Bit_Exp_A_eq_B & Exponent_Matching_Bit_Eff_sub ) & ( Exponent_Matching_Bit_Man_a_ge_Man_B ) ) ) ? Exponent_Matching_input_Sign_A : (( Exponent_Matching_input_opcode[1]) ? Exponent_Matching_input_Sign_B ^ Exponent_Matching_input_opcode[1] : Exponent_Matching_input_Sign_B ^ 1'b0 ) ;
+
+//decision fo MAntissa A for output
+assign Exponent_Matching_output_Mantissa_A = (Exponent_Matching_Bit_Exp_A_ge_B) ? Exponent_Matching_input_Mantissa_A : Exponent_Matching_Shifter_output[4*man+7 : 2*man+4];
+assign Exponent_Matching_output_Mantissa_B = (Exponent_Matching_Bit_Exp_A_ge_B) ? Exponent_Matching_Shifter_output[4*man+7 : 2*man+4] : Exponent_Matching_input_Mantissa_B;
+
+//decision of xponent
+assign Exponent_Matching_output_Exp = Exponent_Matching_Exp_Sub_input_1;
+
+//decision fo rrounding bits
+assign Exponent_Matching_output_Guard = Exponent_Matching_Shifter_output[man+man+3] ;
+assign Exponent_Matching_output_Round = Exponent_Matching_Shifter_output[man+man+2] ;
+assign Exponent_Matching_output_Sticky = (|Exponent_Matching_Shifter_output [man+man:0]) ;
+
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_LZD_L0.v b/verilog/rtl/FPU/FMADD_LZD_L0.v
new file mode 100644
index 0000000..026c41d
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_LZD_L0.v
@@ -0,0 +1,52 @@
+//`include "LZD_comb.v"
+
+module FMADD_LZD_layer_0 (L0_input_man_48, L0_output_pos_val);
+
+input [23:0] L0_input_man_48;
+output [23:0] L0_output_pos_val;
+
+wire L0_wire_pos_0 , L0_wire_val_0 ;
+wire L0_wire_pos_1 , L0_wire_val_1 ;
+wire L0_wire_pos_2 , L0_wire_val_2 ;
+wire L0_wire_pos_3 , L0_wire_val_3 ;
+wire L0_wire_pos_4 , L0_wire_val_4 ;
+wire L0_wire_pos_5 , L0_wire_val_5 ;
+wire L0_wire_pos_6 , L0_wire_val_6 ;
+wire L0_wire_pos_7 , L0_wire_val_7 ;
+wire L0_wire_pos_8 , L0_wire_val_8;
+wire L0_wire_pos_9 , L0_wire_val_9 ;
+wire L0_wire_pos_10 , L0_wire_val_10 ;
+wire L0_wire_pos_11 , L0_wire_val_11 ;
+
+
+//Layer 0
+FPU_LZD_comb L0_0 (.in_bits(L0_input_man_48[1:0]), .out_pos(L0_wire_pos_0), .out_val(L0_wire_val_0));
+FPU_LZD_comb L0_1 (.in_bits(L0_input_man_48[3:2]), .out_pos(L0_wire_pos_1), .out_val(L0_wire_val_1));
+FPU_LZD_comb L0_2 (.in_bits(L0_input_man_48[5:4]), .out_pos(L0_wire_pos_2), .out_val(L0_wire_val_2));
+FPU_LZD_comb L0_3 (.in_bits(L0_input_man_48[7:6]), .out_pos(L0_wire_pos_3), .out_val(L0_wire_val_3));
+FPU_LZD_comb L0_4 (.in_bits(L0_input_man_48[9:8]), .out_pos(L0_wire_pos_4), .out_val(L0_wire_val_4));
+FPU_LZD_comb L0_5 (.in_bits(L0_input_man_48[11:10]), .out_pos(L0_wire_pos_5), .out_val(L0_wire_val_5));
+FPU_LZD_comb L0_6 (.in_bits(L0_input_man_48[13:12]), .out_pos(L0_wire_pos_6), .out_val(L0_wire_val_6));
+FPU_LZD_comb L0_7 (.in_bits(L0_input_man_48[15:14]), .out_pos(L0_wire_pos_7), .out_val(L0_wire_val_7));
+FPU_LZD_comb L0_8 (.in_bits(L0_input_man_48[17:16]), .out_pos(L0_wire_pos_8), .out_val(L0_wire_val_8));
+FPU_LZD_comb L0_9 (.in_bits(L0_input_man_48[19:18]), .out_pos(L0_wire_pos_9), .out_val(L0_wire_val_9));
+FPU_LZD_comb L0_10 (.in_bits(L0_input_man_48[21:20]), .out_pos(L0_wire_pos_10), .out_val(L0_wire_val_10));
+FPU_LZD_comb L0_11 (.in_bits(L0_input_man_48[23:22]), .out_pos(L0_wire_pos_11), .out_val(L0_wire_val_11));
+
+assign L0_output_pos_val =
+{L0_wire_val_11, L0_wire_pos_11,
+ L0_wire_val_10, L0_wire_pos_10,
+ L0_wire_val_9, L0_wire_pos_9,
+ L0_wire_val_8, L0_wire_pos_8,
+ L0_wire_val_7, L0_wire_pos_7,
+ L0_wire_val_6, L0_wire_pos_6,
+ L0_wire_val_5, L0_wire_pos_5,
+ L0_wire_val_4, L0_wire_pos_4,
+ L0_wire_val_3, L0_wire_pos_3,
+ L0_wire_val_2, L0_wire_pos_2,
+ L0_wire_val_1, L0_wire_pos_1,
+ L0_wire_val_0, L0_wire_pos_0};
+
+
+endmodule
+
diff --git a/verilog/rtl/FPU/FMADD_LZD_L1.v b/verilog/rtl/FPU/FMADD_LZD_L1.v
new file mode 100644
index 0000000..edd026c
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_LZD_L1.v
@@ -0,0 +1,32 @@
+//`include "LZD_mux.v"
+
+module FMADD_LZD_layer_1 (L1_input_pos_val, L1_output_pos_val);
+
+parameter layer = 1;
+
+//Input of layer 1, Output from layer 0
+input [23 :0]L1_input_pos_val;
+
+//Output of layer 1, this will be Input to layer 2
+output [17 : 0] L1_output_pos_val;
+
+//Wires
+wire L1_wire_output_val_0, L1_wire_output_val_1, L1_wire_output_val_2, L1_wire_output_val_3, L1_wire_output_val_4, L1_wire_output_val_5;
+wire [layer : 0] L1_wire_output_pos_0, L1_wire_output_pos_1, L1_wire_output_pos_2, L1_wire_output_pos_3, L1_wire_output_pos_4, L1_wire_output_pos_5;
+
+
+FPU_LZD_mux L1_0 (.in_val_2(L1_input_pos_val[3]), .in_pos_2(L1_input_pos_val[2]), .in_val_1(L1_input_pos_val[1]), .in_pos_1(L1_input_pos_val[0]), .out_pos(L1_wire_output_pos_0), .out_val(L1_wire_output_val_0)); defparam L1_0.layer = 1;
+FPU_LZD_mux L1_1 (.in_val_2(L1_input_pos_val[7]), .in_pos_2(L1_input_pos_val[6]), .in_val_1(L1_input_pos_val[5]), .in_pos_1(L1_input_pos_val[4]), .out_pos(L1_wire_output_pos_1), .out_val(L1_wire_output_val_1)); defparam L1_1.layer = 1;
+FPU_LZD_mux L1_2 (.in_val_2(L1_input_pos_val[11]), .in_pos_2(L1_input_pos_val[10]), .in_val_1(L1_input_pos_val[9]), .in_pos_1(L1_input_pos_val[8]), .out_pos(L1_wire_output_pos_2), .out_val(L1_wire_output_val_2)); defparam L1_2.layer = 1;
+FPU_LZD_mux L1_3 (.in_val_2(L1_input_pos_val[15]), .in_pos_2(L1_input_pos_val[14]), .in_val_1(L1_input_pos_val[13]), .in_pos_1(L1_input_pos_val[12]), .out_pos(L1_wire_output_pos_3), .out_val(L1_wire_output_val_3)); defparam L1_3.layer = 1;
+FPU_LZD_mux L1_4 (.in_val_2(L1_input_pos_val[19]), .in_pos_2(L1_input_pos_val[18]), .in_val_1(L1_input_pos_val[17]), .in_pos_1(L1_input_pos_val[16]), .out_pos(L1_wire_output_pos_4), .out_val(L1_wire_output_val_4)); defparam L1_4.layer = 1;
+FPU_LZD_mux L1_5 (.in_val_2(L1_input_pos_val[23]), .in_pos_2(L1_input_pos_val[22]), .in_val_1(L1_input_pos_val[21]), .in_pos_1(L1_input_pos_val[20]), .out_pos(L1_wire_output_pos_5), .out_val(L1_wire_output_val_5)); defparam L1_5.layer = 1;
+
+assign L1_output_pos_val =
+{L1_wire_output_val_5, L1_wire_output_pos_5,
+ L1_wire_output_val_4, L1_wire_output_pos_4,
+ L1_wire_output_val_3, L1_wire_output_pos_3,
+ L1_wire_output_val_2, L1_wire_output_pos_2,
+ L1_wire_output_val_1, L1_wire_output_pos_1,
+ L1_wire_output_val_0, L1_wire_output_pos_0};
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_LZD_L2.v b/verilog/rtl/FPU/FMADD_LZD_L2.v
new file mode 100644
index 0000000..218dace
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_LZD_L2.v
@@ -0,0 +1,26 @@
+//`include "LZD_mux.v"
+
+module FMADD_LZD_layer_2 (L2_input_pos_val, L2_output_pos_val);
+
+parameter layer = 2;
+
+//Input of layer 2, Output from layer 1
+input [17 :0]L2_input_pos_val;
+
+//Output of layer 2, this will be Input to layer 3
+output [11 : 0] L2_output_pos_val;
+
+//Wires
+wire L2_wire_output_val_0, L2_wire_output_val_1, L2_wire_output_val_2;
+wire [layer : 0] L2_wire_output_pos_0, L2_wire_output_pos_1, L2_wire_output_pos_2;
+
+
+FPU_LZD_mux L2_0 (.in_val_2(L2_input_pos_val[5]), .in_pos_2(L2_input_pos_val[4:3]), .in_val_1(L2_input_pos_val[2]), .in_pos_1(L2_input_pos_val[1:0]), .out_pos(L2_wire_output_pos_0), .out_val(L2_wire_output_val_0)); defparam L2_0.layer = 2;
+FPU_LZD_mux L2_1 (.in_val_2(L2_input_pos_val[11]), .in_pos_2(L2_input_pos_val[10:9]), .in_val_1(L2_input_pos_val[8]), .in_pos_1(L2_input_pos_val[7:6]), .out_pos(L2_wire_output_pos_1), .out_val(L2_wire_output_val_1)); defparam L2_1.layer = 2;
+FPU_LZD_mux L2_2 (.in_val_2(L2_input_pos_val[17]), .in_pos_2(L2_input_pos_val[16:15]), .in_val_1(L2_input_pos_val[14]), .in_pos_1(L2_input_pos_val[13:12]), .out_pos(L2_wire_output_pos_2), .out_val(L2_wire_output_val_2)); defparam L2_2.layer = 2;
+
+assign L2_output_pos_val =
+{L2_wire_output_val_2, L2_wire_output_pos_2,
+ L2_wire_output_val_1, L2_wire_output_pos_1,
+ L2_wire_output_val_0, L2_wire_output_pos_0};
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_LZD_L3.v b/verilog/rtl/FPU/FMADD_LZD_L3.v
new file mode 100644
index 0000000..b6a6489
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_LZD_L3.v
@@ -0,0 +1,26 @@
+//`include "LZD_mux.v"
+
+module FMADD_LZD_layer_3 (L3_input_pos_val, L3_output_pos_val);
+
+parameter layer = 3;
+
+//Input of layer 3, Output from layer 2
+input [11 :0]L3_input_pos_val;
+
+//Output of layer 3, this will be Input to layer 4
+output [9 : 0] L3_output_pos_val;
+
+//Wires
+wire L3_wire_output_val_0, L3_wire_output_val_1;
+wire [layer : 0] L3_wire_output_pos_0, L3_wire_output_pos_1;
+
+
+FPU_LZD_mux L3_0 (.in_val_2(L3_input_pos_val[7]), .in_pos_2(L3_input_pos_val[6:4]), .in_val_1(L3_input_pos_val[3]), .in_pos_1(L3_input_pos_val[2:0]), .out_pos(L3_wire_output_pos_0), .out_val(L3_wire_output_val_0)); defparam L3_0.layer = 3;
+
+assign L3_wire_output_val_1 = L3_input_pos_val[11];
+assign L3_wire_output_pos_1 = {1'b1,L3_input_pos_val[10:8]};
+
+assign L3_output_pos_val =
+{L3_wire_output_val_1, L3_wire_output_pos_1,
+ L3_wire_output_val_0, L3_wire_output_pos_0};
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_LZD_L4.v b/verilog/rtl/FPU/FMADD_LZD_L4.v
new file mode 100644
index 0000000..816bd8e
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_LZD_L4.v
@@ -0,0 +1,31 @@
+//`include "LZD_mux.v"
+
+module FMADD_LZD_layer_4 (L4_input_pos_val, L4_output_pos);
+
+parameter layer = 4;
+
+//Input of layer 4, Output from layer 3
+input [9 :0]L4_input_pos_val;
+
+//Output of layer 4, this will be position of Leading 1
+output [4 : 0] L4_output_pos;
+
+//Wires
+wire L4_wire_output_val;
+wire [layer : 0] L4_wire_output_pos;
+wire [layer : 0]L4_wire_output_pos_32;
+
+
+FPU_LZD_mux L4_0 (.in_val_2(L4_input_pos_val[9]), .in_pos_2(L4_input_pos_val[8:5]), .in_val_1(L4_input_pos_val[4]), .in_pos_1(L4_input_pos_val[3:0]), .out_pos(L4_wire_output_pos), .out_val(L4_wire_output_val)); defparam L4_0.layer = 4;
+
+assign L4_wire_output_pos_32 =
+{L4_wire_output_val & L4_wire_output_pos[4],
+L4_wire_output_val & L4_wire_output_pos[3],
+L4_wire_output_val & L4_wire_output_pos[2],
+L4_wire_output_val & L4_wire_output_pos[1],
+L4_wire_output_val & L4_wire_output_pos[0]};
+
+//5'b1100 == 2;s compliment of 8, 8 is subtracted from the final result since the LZD is of 32 bit and actual data is of 24 bit.
+assign L4_output_pos = L4_wire_output_pos_32 + 5'b11000;
+
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_LZD_main.v b/verilog/rtl/FPU/FMADD_LZD_main.v
new file mode 100644
index 0000000..8a52ce0
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_LZD_main.v
@@ -0,0 +1,36 @@
+/*`include "fma_LZD_L0.v"
+`include "fma_LZD_L1.v"
+`include "fma_LZD_L2.v"
+`include "fma_LZD_L3.v"
+`include "fma_LZD_L4.v"*/
+
+module FMADD_PN_LZD (FMADD_PN_LZD_input_man_48, FMADD_PN_LZD_output_pos);
+
+
+parameter layer = 1;
+
+input [23 : 0]FMADD_PN_LZD_input_man_48;
+
+output [4: 0]FMADD_PN_LZD_output_pos;
+
+wire [23 : 0] LZD_wire_output_L0;
+wire [17 : 0] LZD_wire_output_L1;
+wire [11 : 0] LZD_wire_output_L2;
+wire [9 : 0] LZD_wire_output_L3;
+
+//Layer 0
+FMADD_LZD_layer_0 L0 (.L0_input_man_48(FMADD_PN_LZD_input_man_48), .L0_output_pos_val(LZD_wire_output_L0));
+
+//Layer 1
+FMADD_LZD_layer_1 L1 (.L1_input_pos_val(LZD_wire_output_L0), .L1_output_pos_val(LZD_wire_output_L1));
+
+//Layer 2
+FMADD_LZD_layer_2 L2 (.L2_input_pos_val(LZD_wire_output_L1), .L2_output_pos_val(LZD_wire_output_L2));
+
+//Layer 3
+FMADD_LZD_layer_3 L3 (.L3_input_pos_val(LZD_wire_output_L2), .L3_output_pos_val(LZD_wire_output_L3));
+
+//Layer 4
+FMADD_LZD_layer_4 L4 (.L4_input_pos_val(LZD_wire_output_L3), .L4_output_pos(FMADD_PN_LZD_output_pos));
+
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v b/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v
new file mode 100644
index 0000000..3a94261
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v
@@ -0,0 +1,159 @@
+`include "fma_LZD.v"
+
+module FMADD_PN_MUL( FMADD_PN_MUL_input_sign, FMADD_PN_MUL_input_exp_DB, FMADD_PN_MUL_input_multiplied_man, FMADD_PN_MUL_input_lzd, FMADD_PN_MUL_input_rm, FMADD_PN_MUL_input_A_neg, FMADD_PN_MUL_input_A_pos, FMADD_PN_MUL_input_A_sub, FMADD_PN_MUL_input_B_neg, FMADD_PN_MUL_input_B_pos, FMADD_PN_MUL_input_B_sub, FMADD_PN_MUL_output_no, FMADD_PN_MUL_output_overflow, FMADD_PN_MUL_output_sticky_PN);
+
+initial
+begin
+ $dumpfile("dump.vcd");
+ $dumpvars(0);
+end
+
+//Defining Parameters
+parameter std = 31;//Standard - 1
+parameter man = 22;//mantissa bits -1
+parameter exp = 7;//Exp bits -1
+parameter bias = 127;//Bias for selected standard
+parameter lzd = 4;
+
+input FMADD_PN_MUL_input_A_neg, FMADD_PN_MUL_input_A_pos, FMADD_PN_MUL_input_A_sub, FMADD_PN_MUL_input_B_neg, FMADD_PN_MUL_input_B_pos, FMADD_PN_MUL_input_B_sub;
+input FMADD_PN_MUL_input_sign;
+input [exp+1 : 0]FMADD_PN_MUL_input_exp_DB;
+input [man+man+3 : 0]FMADD_PN_MUL_input_multiplied_man;
+input [lzd : 0]FMADD_PN_MUL_input_lzd;
+input [2 : 0]FMADD_PN_MUL_input_rm;
+
+
+output [man+man+exp+5 : 0]FMADD_PN_MUL_output_no;//57 bit output having sign, 8bit exp and 48bit mantissa
+output FMADD_PN_MUL_output_overflow;
+output FMADD_PN_MUL_output_sticky_PN;
+
+wire [lzd : 0]FMADD_PN_MUL_input_lzd_shifts = FMADD_PN_MUL_input_lzd + 1'b1;
+
+wire FMADD_PN_MUL_wire_op_1, FMADD_PN_MUL_wire_op_2, FMADD_PN_MUL_wire_op_3, FMADD_PN_MUL_wire_op_4, FMADD_PN_MUL_wire_op_5;
+wire [exp+1 : 0]FMADD_PN_MUL_wire_127_sub_expDB_extra_bit, FMADD_PN_MUL_wire_expDB_sub_127_extra_bit;
+wire [exp : 0] FMADD_PN_MUL_wire_exp_shifts_interim;
+wire [lzd+1 : 0]FMADD_PN_MUL_wire_exp_shifts;
+wire FMADD_PN_MUL_wire_condition_2;
+wire [lzd+1 : 0]FMADD_PN_MUL_wire_shifts_lzd_msb;
+wire [4 : 0] FMADD_PN_MUL_wire_output_LZD;
+wire FMADD_PN_MUL_wire_condition_3;
+wire [exp : 0]FMADD_PN_MUL_wire_shifts_interim;
+wire [31 : 0]FMADD_PN_MUL_wire_useless;
+wire FMADD_PN_MUL_wire_shifts_overflow;
+wire [lzd+1 : 0]FMADD_PN_MUL_wire_shifts_final;
+wire FMADD_PN_MUL_wire_exp_eq_127, FMADD_PN_MUL_wire_exp_gt_127, FMADD_PN_MUL_wire_exp_lt_127, PM_MUL_wire_sub_or_norm_op5;
+wire FMADD_PN_LZD_wire_direction_shifts;
+wire [man+man+3 : 0]FMADD_PN_MUL_wire_DTRS, FMADD_PN_MUL_wire_DTLS;
+wire [man+man+4 : 0]FMADD_PN_MUL_wire_RS_data, FMADD_PN_MUL_wire_LS_data;
+wire [man+man+4 : 0]FMADD_PN_MUL_wire_man_interim;
+wire [man+man+3 : 0]FMADD_PN_MUL_wire_man_final;
+
+
+wire FMADD_PN_MUL_wire_condition_5;
+wire [31 : 0]FMADD_PN_MUL_wire_zero_useless;
+wire [exp+1 : 0]FMADD_PN_MUL_wire_exp_interim_1;
+wire FMADD_PN_MUL_wire_condition_6;
+wire [exp+1 : 0]FMADD_PN_MUL_wire_exp_interim_2;
+wire [exp+1 : 0]FMADD_PN_MUL_wire_exp_interim_3;
+wire FMADD_PN_MUL_wire_condition_7;
+wire [4 : 0]FMADD_PN_MUL_wire_lzd_true;
+wire [4 : 0]FMADD_PN_MUL_wire_lzd_true_sub_49;
+wire [exp+1 : 0]FMADD_PN_MUL_wire_exp_interim_4;
+wire [exp+1 : 0]FMADD_PN_MUL_wire_exp_interim_5;
+
+wire FMADD_PN_MUL_wire_exception_cond1;
+wire [man+man+exp+5 : 0]FMADD_PN_MUL_wire_output_interim_1;
+wire FMADD_PN_MUL_wire_exception_cond2;
+
+
+assign FMADD_PN_MUL_wire_op_1 = (FMADD_PN_MUL_input_A_pos) & (FMADD_PN_MUL_input_B_pos) ;
+assign FMADD_PN_MUL_wire_op_2 = (FMADD_PN_MUL_input_A_neg) & (FMADD_PN_MUL_input_B_pos) | (FMADD_PN_MUL_input_A_pos) & (FMADD_PN_MUL_input_B_neg) ;
+assign FMADD_PN_MUL_wire_op_3 = (FMADD_PN_MUL_input_A_pos) & (FMADD_PN_MUL_input_B_sub) | (FMADD_PN_MUL_input_A_sub) & (FMADD_PN_MUL_input_B_pos) ;
+assign FMADD_PN_MUL_wire_op_4 = (FMADD_PN_MUL_input_A_neg) & (FMADD_PN_MUL_input_B_sub) | (FMADD_PN_MUL_input_A_sub) & (FMADD_PN_MUL_input_B_neg) ;
+assign FMADD_PN_MUL_wire_op_5 = (FMADD_PN_MUL_input_A_neg) & (FMADD_PN_MUL_input_B_neg);
+
+//both wires are 9 bit(extra bit) since the DB exponent is of 9 bits
+assign FMADD_PN_MUL_wire_127_sub_expDB_extra_bit = bias[exp+1:0] - FMADD_PN_MUL_input_exp_DB;
+assign FMADD_PN_MUL_wire_expDB_sub_127_extra_bit = FMADD_PN_MUL_input_exp_DB - bias[exp+1:0];
+
+
+
+assign FMADD_PN_MUL_wire_exp_shifts_interim = FMADD_PN_MUL_wire_op_3 ? (FMADD_PN_MUL_wire_expDB_sub_127_extra_bit[exp : 0]) : (FMADD_PN_MUL_wire_127_sub_expDB_extra_bit[exp : 0]);
+
+//man+man+4 is first stored here since man is a parameter and parameters are 32 bit wide so using parameter directly will raise a mismatch error.
+assign FMADD_PN_MUL_wire_useless = man+man+4;
+assign FMADD_PN_MUL_wire_shifts_overflow = (FMADD_PN_MUL_wire_exp_shifts_interim > man+man+4) | (FMADD_PN_MUL_input_A_sub & FMADD_PN_MUL_input_B_sub);
+//If shifts are greater than 48 then set then to 48.
+assign FMADD_PN_MUL_wire_exp_shifts = (FMADD_PN_MUL_wire_shifts_overflow) ? (FMADD_PN_MUL_wire_useless[(lzd+1) : 0]) : (FMADD_PN_MUL_wire_exp_shifts_interim[(lzd+1) : 0]) ;
+
+assign FMADD_PN_MUL_wire_condition_2 = FMADD_PN_MUL_wire_op_3 & (!(FMADD_PN_MUL_input_lzd_shifts > FMADD_PN_MUL_wire_expDB_sub_127_extra_bit));
+assign FMADD_PN_MUL_wire_shifts_lzd_msb = FMADD_PN_MUL_wire_condition_2 ? ({1'b0,FMADD_PN_MUL_input_lzd_shifts}) : { ({(lzd+1){1'b0}}) , (!FMADD_PN_MUL_input_multiplied_man[man+man+3])} ;
+
+//Condition using which value of shift will be decided
+assign FMADD_PN_MUL_wire_condition_3 = FMADD_PN_MUL_wire_condition_2 | FMADD_PN_MUL_wire_op_1 | FMADD_PN_MUL_wire_op_2 | (FMADD_PN_MUL_wire_op_5 & (!PM_MUL_wire_sub_or_norm_op5));
+//Deciding which value of shift to select
+assign FMADD_PN_MUL_wire_shifts_final = FMADD_PN_MUL_wire_condition_3 ? FMADD_PN_MUL_wire_shifts_lzd_msb : FMADD_PN_MUL_wire_exp_shifts ;
+
+assign FMADD_PN_MUL_wire_exp_eq_127 = FMADD_PN_MUL_input_exp_DB == bias;
+assign FMADD_PN_MUL_wire_exp_gt_127 = FMADD_PN_MUL_input_exp_DB > bias;
+assign FMADD_PN_MUL_wire_exp_lt_127 = FMADD_PN_MUL_input_exp_DB < bias;
+
+//PM_MUL_wire_sub_or_norm_op5 == 1 when subnormal results from multiplication of -ve exp with subnormal
+assign PM_MUL_wire_sub_or_norm_op5 =
+(!FMADD_PN_MUL_input_multiplied_man[man+man+3]) & (!FMADD_PN_MUL_wire_exp_eq_127) & (!FMADD_PN_MUL_wire_exp_gt_127) & ( FMADD_PN_MUL_wire_exp_lt_127) |
+(!FMADD_PN_MUL_input_multiplied_man[man+man+3]) & ( FMADD_PN_MUL_wire_exp_eq_127) & (!FMADD_PN_MUL_wire_exp_gt_127) & (!FMADD_PN_MUL_wire_exp_lt_127) |
+( FMADD_PN_MUL_input_multiplied_man[man+man+3]) & (!FMADD_PN_MUL_wire_exp_eq_127) & (!FMADD_PN_MUL_wire_exp_gt_127) & ( FMADD_PN_MUL_wire_exp_lt_127) ;
+
+//Direction == 1 when right shifts are to be done and 0 when left shifts are to be done
+//Direction of shifts is also to the right in case both the numbers are subnormal
+assign FMADD_PN_LZD_wire_direction_shifts = (FMADD_PN_MUL_wire_op_5 & PM_MUL_wire_sub_or_norm_op5) | FMADD_PN_MUL_wire_op_4 | (FMADD_PN_MUL_input_A_sub & FMADD_PN_MUL_input_B_sub);
+
+//DTRS = Data To Right Shift
+assign FMADD_PN_MUL_wire_DTRS = FMADD_PN_LZD_wire_direction_shifts ? FMADD_PN_MUL_input_multiplied_man : 48'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ;
+//DTLS = Data To Left Shift
+assign FMADD_PN_MUL_wire_DTLS = FMADD_PN_LZD_wire_direction_shifts ? 48'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 : FMADD_PN_MUL_input_multiplied_man ;
+
+//RS == Right Shifted
+assign FMADD_PN_MUL_wire_RS_data = ({1'b0, FMADD_PN_MUL_wire_DTRS}) >> FMADD_PN_MUL_wire_shifts_final;
+//LS == Left Shifted
+assign FMADD_PN_MUL_wire_LS_data = ({1'b0, FMADD_PN_MUL_wire_DTLS}) << FMADD_PN_MUL_wire_shifts_final;
+
+assign FMADD_PN_MUL_wire_man_interim = FMADD_PN_LZD_wire_direction_shifts ? FMADD_PN_MUL_wire_RS_data : FMADD_PN_MUL_wire_LS_data ;
+
+assign FMADD_PN_MUL_wire_man_final = (FMADD_PN_MUL_wire_man_interim[man+man+4]) ? FMADD_PN_MUL_wire_man_interim[man+man+4 : 1] : FMADD_PN_MUL_wire_man_interim[man+man+3 : 0];
+
+//Exponent Logic
+
+
+assign FMADD_PN_MUL_wire_condition_5 = FMADD_PN_MUL_wire_op_4 | (FMADD_PN_MUL_wire_op_5 & PM_MUL_wire_sub_or_norm_op5) | (FMADD_PN_MUL_wire_op_3 & (FMADD_PN_MUL_input_lzd_shifts > FMADD_PN_MUL_wire_expDB_sub_127_extra_bit)) | (FMADD_PN_MUL_input_A_sub & FMADD_PN_MUL_input_B_sub) ;
+
+// Zero is first stored here since exponent size of different standards is different and using one specific size for FMADD_PN_MUL_wire_exp_interim_1 will raise a mismatch error.
+assign FMADD_PN_MUL_wire_zero_useless = 0;
+assign FMADD_PN_MUL_wire_exp_interim_1 = FMADD_PN_MUL_wire_condition_5 ? ({(exp+2){1'b0}}) : (FMADD_PN_MUL_wire_expDB_sub_127_extra_bit) ;
+
+assign FMADD_PN_MUL_wire_condition_6 = FMADD_PN_MUL_wire_op_1 | FMADD_PN_MUL_wire_op_2 | (FMADD_PN_MUL_wire_op_5 & (!PM_MUL_wire_sub_or_norm_op5));
+assign FMADD_PN_MUL_wire_exp_interim_2 = FMADD_PN_MUL_wire_exp_interim_1 + FMADD_PN_MUL_input_multiplied_man[man+man+3];
+assign FMADD_PN_MUL_wire_exp_interim_3 = FMADD_PN_MUL_wire_condition_6 ? FMADD_PN_MUL_wire_exp_interim_2 : FMADD_PN_MUL_wire_exp_interim_1 ;
+
+assign FMADD_PN_MUL_wire_condition_7 = FMADD_PN_MUL_wire_condition_2;
+assign FMADD_PN_MUL_wire_lzd_true = FMADD_PN_MUL_input_lzd_shifts - 5'b0_0001;
+assign FMADD_PN_MUL_wire_lzd_true_sub_49 = (FMADD_PN_MUL_wire_lzd_true - FMADD_PN_MUL_wire_man_interim[man+man+4]);
+assign FMADD_PN_MUL_wire_exp_interim_4 = FMADD_PN_MUL_wire_exp_interim_3 - FMADD_PN_MUL_wire_lzd_true_sub_49;
+
+assign FMADD_PN_MUL_wire_exp_interim_5 = FMADD_PN_MUL_wire_condition_7 ? FMADD_PN_MUL_wire_exp_interim_4 : FMADD_PN_MUL_wire_exp_interim_3 ;
+
+//Selection of what exception to output in case of overflow, max normal number or infinity
+
+assign FMADD_PN_MUL_wire_exception_cond1 = (FMADD_PN_MUL_input_rm == 3'b000 | FMADD_PN_MUL_input_rm == 3'b100) | ((!FMADD_PN_MUL_input_sign) & (FMADD_PN_MUL_input_rm == 3'b011)) | ((FMADD_PN_MUL_input_sign) & (FMADD_PN_MUL_input_rm == 3'b010));
+assign FMADD_PN_MUL_wire_output_interim_1 = (FMADD_PN_MUL_wire_exception_cond1) ? ({ FMADD_PN_MUL_input_sign, ({exp+1{1'b1}}), ({man+man+4{1'b0}}) }) : ({ FMADD_PN_MUL_input_sign, ({{exp{1'b1}}, 1'b0}), ({man+man+4{1'b1}}) });
+//condition to select output, either exception or result from main, in case 9th bit (singke precision) of exp is high or bits from 8:0 are high then it is overflow
+assign FMADD_PN_MUL_wire_exception_cond2 = FMADD_PN_MUL_wire_exp_interim_5[exp+1] | (&FMADD_PN_MUL_wire_exp_interim_5[exp : 0]);
+//Selecting what to output exception or result coming form main
+assign FMADD_PN_MUL_output_no = (FMADD_PN_MUL_wire_exception_cond2) ? (FMADD_PN_MUL_wire_output_interim_1) : ({FMADD_PN_MUL_input_sign, (FMADD_PN_MUL_wire_exp_interim_5[exp : 0]), FMADD_PN_MUL_wire_man_final}) ;
+//In case cond2 is high overflow flag is set to one
+assign FMADD_PN_MUL_output_overflow = FMADD_PN_MUL_wire_exception_cond2;
+
+//in case shifts are greater than M+N or subnormal numbers are getting multiplied with each other then sticky_PN will get high.
+assign FMADD_PN_MUL_output_sticky_PN = FMADD_PN_MUL_wire_shifts_overflow;
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
new file mode 100644
index 0000000..b8bf8e2
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
@@ -0,0 +1,316 @@
+
+// Designed by : ALi Raza Zaidi
+//mains modue of FMADD
+/*
+//including coommon blocks
+`include "FMADD_M_G.v"
+`include "FMADD_Ext.v"
+`include "F_LZD_Main.v"
+
+//including Multiplication LANE
+`include "FMADD_E_A.v"
+`include "FMADD_mult.v"
+`include "FMADD_PN_MUL.v"
+`include "FMADD_RB_MUL.v"
+
+//Includign Addition/Subtraction LANE
+`include "FMADD_E_M.v"
+`include "FMADD_M_A.v"
+`include "FMADD_PN_Ad.v"
+`include "FMADD_RB_Ad.v"*/
+
+
+module FPU_FMADD_SUBB_Top (FMADD_SUBB_input_IEEE_A, FMADD_SUBB_input_IEEE_B, FMADD_SUBB_input_IEEE_C, FMADD_SUBB_input_opcode,rst_l,FMADD_SUBB_input_Frm,FMADD_SUBB_output_IEEE_FMADD, FMADD_SUBB_output_S_Flags_FMADD, FMADD_SUBB_output_IEEE_FMUL, FMADD_SUBB_output_S_Flags_FMUL );
+
+parameter std =31;
+parameter man =22;
+parameter exp = 7;
+parameter bias = 8'b01111111;
+parameter lzd = 3;
+
+//declaration of inputs
+input [std:0] FMADD_SUBB_input_IEEE_A, FMADD_SUBB_input_IEEE_B,FMADD_SUBB_input_IEEE_C;
+input [6:0] FMADD_SUBB_input_opcode;
+input [2:0] FMADD_SUBB_input_Frm;
+input rst_l;
+
+//Opcodes description
+/*
+Opcodes[0] = Fadd
+Opcodes[1] = Fsubb
+Opcodes[2] = Fmul
+Opcodes[3] = Fmadd
+Opcodes[4] = Fmsubb
+Opcodes[5] = Fnmadd
+Opcodes[6] = Fnmsubb
+*/
+
+//declaration of putputs
+output [std:0] FMADD_SUBB_output_IEEE_FMADD, FMADD_SUBB_output_IEEE_FMUL;
+output [2:0] FMADD_SUBB_output_S_Flags_FMADD , FMADD_SUBB_output_S_Flags_FMUL;
+//output FMADD_SUBB_output_FMADD_Ready_Flag;
+
+//instantiation of sub modules
+//mantissa generation modules: This module concatenates the hidden bit, and sets the exponent in accordance with the type of number (Normal Sub_Normal)
+
+//activation isgnal for multiplication lane
+wire Activation_signal_MUL,Activation_signal;
+wire [std:0] input_interim_Mantissa_gnerator_A,input_interim_Mantissa_gnerator_B,input_interim_Mantissa_gnerator_C;
+wire [std+1:0] output_interim_M_G_A,output_interim_M_G_B,output_interim_M_G_C;
+wire output_interim_A_sub_norm,output_interim_B_sub_norm,output_interim_A_pos_exp,output_interim_B_pos_exp,output_interim_A_neg_exp,output_interim_B_neg_exp;
+
+
+//Reset condition
+assign input_interim_Mantissa_gnerator_A = (rst_l) ? FMADD_SUBB_input_IEEE_A : { std+1 {1'b0} };
+assign input_interim_Mantissa_gnerator_B = (rst_l) ? FMADD_SUBB_input_IEEE_B : { std+1 {1'b0} };
+assign input_interim_Mantissa_gnerator_C = (rst_l) ? FMADD_SUBB_input_IEEE_C : { std+1 {1'b0} };
+assign Activation_signal_MUL = (rst_l) ? ( |(FMADD_SUBB_input_opcode[6:2]) ) : 1'b0;
+assign Activation_signal = (rst_l) ? ( | (FMADD_SUBB_input_opcode[6:0])) : 1'b0;
+
+FMADD_Mantissa_Generator Mantissa_Generator (
+ .Mantissa_Generator_input_IEEE_A (input_interim_Mantissa_gnerator_A),
+ .Mantissa_Generator_input_IEEE_B (input_interim_Mantissa_gnerator_B),
+ .Mantissa_Generator_input_IEEE_C (input_interim_Mantissa_gnerator_C),
+ .Mantissa_Generator_input_Activation_signal (Activation_signal),
+ .Mantissa_Generator_output_A_Sub_norm(output_interim_A_sub_norm),
+ .Mantissa_Generator_output_B_Sub_norm(output_interim_B_sub_norm),
+ .Mantissa_Generator_output_A_pos_exp(output_interim_A_pos_exp),
+ .Mantissa_Generator_output_B_pos_exp(output_interim_B_pos_exp),
+ .Mantissa_Generator_output_A_neg_exp(output_interim_A_neg_exp),
+ .Mantissa_Generator_output_B_neg_exp(output_interim_B_neg_exp),
+ .Mantissa_Generator_output_IEEE_A (output_interim_M_G_A),
+ .Mantissa_Generator_output_IEEE_B (output_interim_M_G_B),
+ .Mantissa_Generator_output_IEEE_C (output_interim_M_G_C)
+ );
+defparam Mantissa_Generator.std = std;
+defparam Mantissa_Generator.man = man;
+defparam Mantissa_Generator.exp = exp;
+
+//extend module : This module is responsible for making the input representable in IEEE exteded format
+wire [std+1 : 0] input_Extender_B;
+wire [1+exp+2*(man+2):0] output_interim_Extender_A,output_interim_Extender_B;
+
+//selection of the second operand of the extender : If addition is the inputted instruction B goes to extender otherwise C goes to the Extender
+assign input_Extender_B = (| FMADD_SUBB_input_opcode[1:0]) ? output_interim_M_G_B : output_interim_M_G_C;
+FMADD_Extender Extender (
+ .Extender_input_A(output_interim_M_G_A),
+ .Extender_input_B(input_Extender_B),
+ .Extender_output_A(output_interim_Extender_A),
+ .Extender_output_B(output_interim_Extender_B)
+);
+defparam Extender.std = std;
+defparam Extender.man = man;
+defparam Extender.exp = exp;
+
+//exponent addition module: This module is repsonsible for carrying out tje first operation of Multiplication i.e.e exponent addition
+wire [4:0] input_interim_exponent_addition_opcodes;
+wire input_Exponent_Addition_input_Sign_A;
+wire [exp+1 : 0] output_interim_exponent_addition;
+wire output_interim_exponent_addition_sign;
+wire underflow_FMUL;
+
+assign input_Exponent_Addition_input_Sign_A = ( |FMADD_SUBB_input_opcode[6:5] ) ? (~output_interim_M_G_A[std+1]) : (output_interim_M_G_A[std+1]) ;
+
+FMADD_Exponent_addition Exponent_Addition (
+ .Exponent_addition_input_A({ input_Exponent_Addition_input_Sign_A, output_interim_M_G_A[std:man+2] } ),
+ .Exponent_addition_input_B(output_interim_M_G_B[std+1:man+2]),
+ .Exponent_addition_input_Activation_Signal (Activation_signal_MUL),
+ .Exponent_addition_output_exp(output_interim_exponent_addition),
+ .output_underflow_check (underflow_FMUL),
+ .Exponent_addition_output_sign(output_interim_exponent_addition_sign)
+);
+defparam Exponent_Addition.std = std;
+defparam Exponent_Addition.man = man;
+defparam Exponent_Addition.exp = exp;
+
+
+//mantissa multiplication Module
+wire [man+man+3 :0] output_interim_mantissa_multiplication;
+
+FMADD_Mantissa_Multiplication Mantissa_Multiplication (
+ .Mantissa_Multiplication_input_A(output_interim_M_G_A[man+1:0]),
+ .Mantissa_Multiplication_input_B(output_interim_M_G_B[man+1:0]),
+ .Mantissa_Multiplication_input_Activation_Signal (Activation_signal_MUL),
+ .Mantissa_Multiplication_output_Mantissa( output_interim_mantissa_multiplication)
+);
+defparam Mantissa_Multiplication.man = man;
+defparam Mantissa_Multiplication.exp = exp;
+
+//instantiation of LZD module
+wire [23:0] input_LZD;
+wire [4:0] output_interim_LZD;
+
+assign input_LZD = (output_interim_A_sub_norm) ? output_interim_M_G_A[man+1:0] : output_interim_M_G_B[man+1:0] ;
+
+
+FMADD_PN_LZD Leading_Zero_detection (
+ .FMADD_PN_LZD_input_man_48(input_LZD),
+ .FMADD_PN_LZD_output_pos(output_interim_LZD)
+ );
+
+
+//post normalaization Module
+wire [1+exp+2*(man+2):0] output_interim_post_normalization_IEEE;
+wire output_interim_post_normalization_mul_overflow_flag, output_interim_post_normalization_mul_sticky;
+
+FMADD_PN_MUL Post_Normalization_Mul (
+ . FMADD_PN_MUL_input_sign (output_interim_exponent_addition_sign),
+ . FMADD_PN_MUL_input_multiplied_man (output_interim_mantissa_multiplication),
+ . FMADD_PN_MUL_input_exp_DB (output_interim_exponent_addition),
+ . FMADD_PN_MUL_input_lzd (output_interim_LZD),
+ . FMADD_PN_MUL_input_A_sub (output_interim_A_sub_norm),
+ . FMADD_PN_MUL_input_B_sub (output_interim_B_sub_norm),
+ . FMADD_PN_MUL_input_A_pos (output_interim_A_pos_exp),
+ . FMADD_PN_MUL_input_B_pos (output_interim_B_pos_exp),
+ . FMADD_PN_MUL_input_A_neg (output_interim_A_neg_exp),
+ . FMADD_PN_MUL_input_B_neg (output_interim_B_neg_exp),
+ . FMADD_PN_MUL_output_no (output_interim_post_normalization_IEEE),
+ . FMADD_PN_MUL_output_overflow (output_interim_post_normalization_mul_overflow_flag),
+ . FMADD_PN_MUL_output_sticky_PN(output_interim_post_normalization_mul_sticky),
+ . FMADD_PN_MUL_input_rm(FMADD_SUBB_input_Frm)
+);
+
+defparam Post_Normalization_Mul.std = std;
+defparam Post_Normalization_Mul.exp = exp;
+defparam Post_Normalization_Mul.man = man;
+defparam Post_Normalization_Mul.bias = bias;
+defparam Post_Normalization_Mul.lzd = lzd;
+
+//module instantiatyion of Rounding Block of Multipliction Lane
+wire [std:0] output_rounding_Block;
+wire [2:0] output_interim_rounding_Block_S_Flag;
+
+FMADD_ROUND_MUL Rounding_Block_Mul (
+ .FMADD_ROUND_MUL_input_overflow(output_interim_post_normalization_mul_overflow_flag),
+ .FMADD_ROUND_MUL_input_sticky_PN(output_interim_post_normalization_mul_sticky),
+ .FMADD_ROUND_MUL_input_no(output_interim_post_normalization_IEEE),
+ .FMADD_ROUND_MUL_input_rm(FMADD_SUBB_input_Frm),
+ .FMADD_ROUND_MUL_output_no(output_rounding_Block),
+ .FMADD_ROUND_MUL_output_S_Flags(output_interim_rounding_Block_S_Flag)
+);
+defparam Rounding_Block_Mul.std = std;
+defparam Rounding_Block_Mul.exp = exp;
+defparam Rounding_Block_Mul.man = man;
+
+//module instantiation of FMADD Lane
+///=interim wires and register for FMADD Lane
+
+//ppelining registers
+wire [1+exp+2*(man+2):0] input_interim_ADD_LANE_A;
+wire [1+exp+2*(man+2):0] input_interim_ADD_LANE_B;
+
+//inputs to the FMADD LANE
+assign input_interim_ADD_LANE_A = ( |(FMADD_SUBB_input_opcode[1:0] ) ) ? output_interim_Extender_A : (| FMADD_SUBB_input_opcode[6:3]) ? output_interim_post_normalization_IEEE : 57'h000000000000000 ;
+assign input_interim_ADD_LANE_B = (|(FMADD_SUBB_input_opcode[1:0] ) ) ? output_interim_Extender_B : (| FMADD_SUBB_input_opcode[6:3]) ? output_interim_Extender_B : 57'h000000000000000;
+
+//exponent_Matching
+wire output_interim_Exponent_Mathcing_Sign;
+wire [man+man+3:0] output_interim_Exponent_Mathcing_Mantissa_A;
+wire [man+man+3:0] output_interim_Exponent_Mathcing_Mantissa_B;
+wire [exp:0] output_interim_Exponent_Mathcing_Exponent;
+wire output_interim_Exponent_Mathcing_Eff_add;
+wire output_interim_Exponent_Mathcing_Eff_sub;
+wire output_interim_Exponent_Mathcing_Guard;
+wire output_interim_Exponent_Mathcing_Round;
+wire output_interim_Exponent_Mathcing_Sticky;
+
+
+
+FMADD_Exponent_Matching Exponent_Matching (
+ .Exponent_Matching_input_Sign_A ( input_interim_ADD_LANE_A[1+exp+2*(man+2)] ),
+ .Exponent_Matching_input_Sign_B( input_interim_ADD_LANE_B[1+exp+2*(man+2)] ),
+ .Exponent_Matching_input_Exp_A( input_interim_ADD_LANE_A[exp+2*(man+2): man+man+4] ),
+ .Exponent_Matching_input_Exp_B( input_interim_ADD_LANE_B[exp+2*(man+2): man+man+4] ),
+ .Exponent_Matching_input_Mantissa_A( input_interim_ADD_LANE_A[man+man+3 : 0] ),
+ .Exponent_Matching_input_Mantissa_B( input_interim_ADD_LANE_B[man+man+3 : 0] ),
+ .Exponent_Matching_input_opcode( { FMADD_SUBB_input_opcode[1] | FMADD_SUBB_input_opcode[4] | FMADD_SUBB_input_opcode[6] , FMADD_SUBB_input_opcode[0] | FMADD_SUBB_input_opcode[5] | FMADD_SUBB_input_opcode[3]} ),
+ .Exponent_Matching_output_Mantissa_A( output_interim_Exponent_Mathcing_Mantissa_A),
+ .Exponent_Matching_output_Mantissa_B( output_interim_Exponent_Mathcing_Mantissa_B),
+ .Exponent_Matching_output_Exp (output_interim_Exponent_Mathcing_Exponent),
+ .Exponent_Matching_output_Sign( output_interim_Exponent_Mathcing_Sign),
+ .Exponent_Matching_output_Guard (output_interim_Exponent_Mathcing_Guard),
+ .Exponent_Matching_output_Round( output_interim_Exponent_Mathcing_Round),
+ .Exponent_Matching_output_Sticky( output_interim_Exponent_Mathcing_Sticky),
+ .Exponent_Matching_output_Eff_Sub( output_interim_Exponent_Mathcing_Eff_sub),
+ .Exponent_Matching_output_Eff_add( output_interim_Exponent_Mathcing_Eff_add)
+ );
+defparam Exponent_Matching.std = std;
+defparam Exponent_Matching.exp = exp;
+defparam Exponent_Matching.man = man;
+
+
+//Mantissa Addition
+wire [man+man+3:0] output_interim_Mantissa_Addition_Mantissa;
+wire output_interim_Mantissa_Addition_Carry;
+FMADD_Mantissa_Addition Mantissa_Addition (
+ .Mantissa_Addition_input_Mantissa_A( output_interim_Exponent_Mathcing_Mantissa_A),
+ .Mantissa_Addition_input_Mantissa_B( output_interim_Exponent_Mathcing_Mantissa_B),
+ .Mantissa_Addition_input_Eff_Sub( output_interim_Exponent_Mathcing_Eff_sub),
+ .Mantissa_Addition_output_Mantissa(output_interim_Mantissa_Addition_Mantissa ),
+ .Mantissa_Addition_output_Carry(output_interim_Mantissa_Addition_Carry)
+);
+defparam Mantissa_Addition.std = std;
+defparam Mantissa_Addition.exp = exp;
+defparam Mantissa_Addition.man = man;
+
+//Post Normalization Module
+wire output_interim_Post_Norm_Add_Guard;
+wire output_interim_Post_Norm_Add_Round;
+wire output_interim_Post_Norm_Add_Sticky;
+wire [exp+1:0] output_interim_Post_Norm_Add_Exponent;
+wire [man+1:0] output_interim_Post_Norm_Add_Mantissa;
+FMADD_Post_Normalization_Add_Sub Post_Normalization_Add (
+ .Post_Normalization_input_Mantissa ( output_interim_Mantissa_Addition_Mantissa ),
+ .Post_Normalization_input_exponent ( output_interim_Exponent_Mathcing_Exponent),
+ .Post_Normalization_input_Carry ( output_interim_Mantissa_Addition_Carry),
+ .Post_Normalization_input_Eff_sub ( output_interim_Exponent_Mathcing_Eff_sub ),
+ .Post_Normalization_input_Eff_add ( output_interim_Exponent_Mathcing_Eff_add),
+ .Post_Normalization_input_Guard ( output_interim_Exponent_Mathcing_Guard),
+ .Post_Normalization_input_Round ( output_interim_Exponent_Mathcing_Round),
+ .Post_Normalization_input_Sticky ( output_interim_Exponent_Mathcing_Sticky ),
+ .Post_Normalization_output_Guard ( output_interim_Post_Norm_Add_Guard),
+ .Post_Normalization_output_Round (output_interim_Post_Norm_Add_Round),
+ .Post_Normalization_output_Sticky ( output_interim_Post_Norm_Add_Sticky),
+ .Post_Normalization_output_Mantissa ( output_interim_Post_Norm_Add_Mantissa ),
+ .Post_Normalization_output_exponent ( output_interim_Post_Norm_Add_Exponent)
+);
+defparam Post_Normalization_Add.std = std;
+defparam Post_Normalization_Add.exp = exp;
+defparam Post_Normalization_Add.man = man;
+
+//Rounding Mode Module
+wire [exp:0] output_interim_Rounding_Block_Exp;
+wire [man:0] output_interim_Rounding_Block_Mantissa;
+wire output_interim_Rounding_Block_Sign;
+wire [1:0] output_interim_Rounding_Block_S_flags;
+wire [2:0] input_rounding_block_Add_frm;
+
+assign input_rounding_block_Add_frm = (|FMADD_SUBB_input_opcode[6:3] | (|FMADD_SUBB_input_opcode[1:0]) ) ? FMADD_SUBB_input_Frm : 3'b000;
+
+FMADD_Roudning_Block_Addition Rounding_Block_Add (
+ .Rounding_Block_input_Mantissa (output_interim_Post_Norm_Add_Mantissa) ,
+ .Rounding_Block_input_Exponent (output_interim_Post_Norm_Add_Exponent),
+ .Rounding_Block_input_Sign (output_interim_Exponent_Mathcing_Sign),
+ .Rounding_Block_input_Guard (output_interim_Post_Norm_Add_Guard),
+ .Rounding_Block_input_Round (output_interim_Post_Norm_Add_Round),
+ .Rounding_Block_input_Sticky (output_interim_Post_Norm_Add_Sticky),
+ .Rounding_Block_input_Frm (input_rounding_block_Add_frm),
+ .Rounding_Block_output_Exponent (output_interim_Rounding_Block_Exp),
+ .Rounding_Block_output_Sign ( output_interim_Rounding_Block_Sign),
+ .Rounding_Block_output_Mantissa( output_interim_Rounding_Block_Mantissa ),
+ .Rounding_Block_output_S_Flags (output_interim_Rounding_Block_S_flags)
+);
+defparam Rounding_Block_Add.std = std;
+defparam Rounding_Block_Add.exp = exp;
+defparam Rounding_Block_Add.man = man;
+
+//Multiplication lane output ports
+assign FMADD_SUBB_output_IEEE_FMUL = ( (~FMADD_SUBB_input_opcode[2]) | underflow_FMUL | (~rst_l) ) ? { std+1 {1'b0} } : output_rounding_Block ;
+assign FMADD_SUBB_output_S_Flags_FMUL = ( ( FMADD_SUBB_input_opcode[2] ) & (rst_l) ) ? output_interim_rounding_Block_S_Flag : 3'b000;
+
+//addition Lane output POrts
+assign FMADD_SUBB_output_IEEE_FMADD = ( ((|FMADD_SUBB_input_opcode[1:0]) | (|FMADD_SUBB_input_opcode[6:3]) ) & (rst_l) ) ? { output_interim_Rounding_Block_Sign, output_interim_Rounding_Block_Exp ,output_interim_Rounding_Block_Mantissa } :{ std+1 {1'b0} } ;
+assign FMADD_SUBB_output_S_Flags_FMADD = ( ( (|FMADD_SUBB_input_opcode[1:0]) | (|FMADD_SUBB_input_opcode[6:3]) ) & (rst_l) ) ? {output_interim_Rounding_Block_S_flags[1],1'b0,output_interim_Rounding_Block_S_flags[0]} : 3'b00;
+
+
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_exponent_addition.v b/verilog/rtl/FPU/FMADD_exponent_addition.v
new file mode 100644
index 0000000..4990447
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_exponent_addition.v
@@ -0,0 +1,25 @@
+//This module is responsisble for addition of exponents
+
+module FMADD_Exponent_addition (Exponent_addition_input_A,Exponent_addition_input_B,Exponent_addition_input_Activation_Signal,Exponent_addition_output_exp,Exponent_addition_output_sign,output_underflow_check);
+parameter std=31;
+parameter man =22;
+parameter exp = 7;
+
+//declaration of inputs
+input [exp+1:0] Exponent_addition_input_A,Exponent_addition_input_B;
+input Exponent_addition_input_Activation_Signal;
+
+//declaration of putputs
+output [exp+1:0] Exponent_addition_output_exp;
+output Exponent_addition_output_sign;
+output output_underflow_check;
+wire [exp+1:0] Exponent_addition_wire_exp;
+
+//functionality
+assign Exponent_addition_wire_exp = (Exponent_addition_input_Activation_Signal) ? (Exponent_addition_input_A[exp:0] + Exponent_addition_input_B[exp:0]): 9'b000000000;
+assign output_underflow_check = Exponent_addition_wire_exp < 103;
+assign Exponent_addition_output_exp = Exponent_addition_wire_exp;
+assign Exponent_addition_output_sign = (Exponent_addition_input_Activation_Signal) ? (Exponent_addition_input_A [exp+1] ^ Exponent_addition_input_B[exp+1]) : 1'b0;
+
+
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_extender.v b/verilog/rtl/FPU/FMADD_extender.v
new file mode 100644
index 0000000..3cd243a
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_extender.v
@@ -0,0 +1,20 @@
+//module for extension
+
+module FMADD_Extender (Extender_input_A,Extender_input_B,Extender_output_A,Extender_output_B);
+parameter std =31;
+parameter man = 22;
+parameter exp = 7;
+
+//input declaration
+input [std+1:0] Extender_input_A,Extender_input_B;
+
+
+//output declaration
+output [1+exp+2*(man+2):0] Extender_output_A,Extender_output_B;
+
+//main functionlity
+assign Extender_output_A = {Extender_input_A,{man+2{1'b0}}} ;
+assign Extender_output_B = {Extender_input_B,{man+2{1'b0}}} ;
+
+
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_mantissa_addition.v b/verilog/rtl/FPU/FMADD_mantissa_addition.v
new file mode 100644
index 0000000..6df4a66
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_mantissa_addition.v
@@ -0,0 +1,41 @@
+//mantissa addition module
+
+
+module FMADD_Mantissa_Addition( Mantissa_Addition_input_Mantissa_A,Mantissa_Addition_input_Mantissa_B,Mantissa_Addition_input_Eff_Sub,Mantissa_Addition_output_Mantissa, Mantissa_Addition_output_Carry );
+
+//declaration of paramters
+parameter std =31;
+parameter man = 22;
+parameter exp = 7;
+
+//declaration of input ports
+input [man+man+3:0] Mantissa_Addition_input_Mantissa_A,Mantissa_Addition_input_Mantissa_B;
+input Mantissa_Addition_input_Eff_Sub;
+
+/*
+opcode[0]= fadd;
+opcode[1] = Fsuub
+*/
+
+
+wire [man+man+3:0] interim_mantissa_B,interim_mantissa_B_adder;
+wire Mantissa_Addition_interim_Carry;
+wire [man+man+3:0] Mantissa_Addition_Compliment_B;
+wire Mantissa_Addition_interim_Compliment_Carry;
+//declartion of output piorts
+output Mantissa_Addition_output_Carry;
+output [man+man+3:0] Mantissa_Addition_output_Mantissa;
+
+
+//Main functionality
+assign {Mantissa_Addition_interim_Compliment_Carry,Mantissa_Addition_Compliment_B} = ( {1'b0,(~(Mantissa_Addition_input_Mantissa_B))} + 1'b1);
+
+assign interim_mantissa_B = (Mantissa_Addition_input_Eff_Sub) ? Mantissa_Addition_Compliment_B : Mantissa_Addition_input_Mantissa_B ;
+assign {Mantissa_Addition_interim_Carry,interim_mantissa_B_adder} = {1'b0, interim_mantissa_B} + {1'b0,Mantissa_Addition_input_Mantissa_A};
+
+assign Mantissa_Addition_output_Mantissa = ( (~Mantissa_Addition_interim_Carry) & Mantissa_Addition_input_Eff_Sub & (~Mantissa_Addition_interim_Compliment_Carry) ) ? ( ~(interim_mantissa_B_adder) + 1'b1 ) : interim_mantissa_B_adder;
+assign Mantissa_Addition_output_Carry = Mantissa_Addition_interim_Carry;
+
+
+
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_mantissa_generator.v b/verilog/rtl/FPU/FMADD_mantissa_generator.v
new file mode 100644
index 0000000..39e745c
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_mantissa_generator.v
@@ -0,0 +1,46 @@
+//submodule of FMADD/subb
+//the module is responsible for selection and concatination of hidden bits as per requirments (Subnormal, Normal)
+
+module FMADD_Mantissa_Generator (Mantissa_Generator_input_IEEE_A,Mantissa_Generator_input_IEEE_B,Mantissa_Generator_input_IEEE_C,Mantissa_Generator_input_Activation_signal,Mantissa_Generator_output_IEEE_A,Mantissa_Generator_output_IEEE_B,Mantissa_Generator_output_IEEE_C,Mantissa_Generator_output_A_Sub_norm,Mantissa_Generator_output_B_Sub_norm,Mantissa_Generator_output_A_pos_exp,Mantissa_Generator_output_B_pos_exp,Mantissa_Generator_output_A_neg_exp,Mantissa_Generator_output_B_neg_exp);
+
+//declaration of parameters
+parameter std = 31;
+parameter man = 22;
+parameter exp = 7;
+
+
+//declaration of input ports
+input [std:0] Mantissa_Generator_input_IEEE_A,Mantissa_Generator_input_IEEE_B,Mantissa_Generator_input_IEEE_C;
+input Mantissa_Generator_input_Activation_signal;
+
+//declaration of ouptu ports
+output [std+1:0] Mantissa_Generator_output_IEEE_A,Mantissa_Generator_output_IEEE_B,Mantissa_Generator_output_IEEE_C;
+output Mantissa_Generator_output_A_Sub_norm,Mantissa_Generator_output_B_Sub_norm,Mantissa_Generator_output_A_pos_exp,Mantissa_Generator_output_B_pos_exp,Mantissa_Generator_output_A_neg_exp,Mantissa_Generator_output_B_neg_exp;
+
+//interim wires
+wire A_subnormal,B_subnormal,C_subnormal;
+
+//check for subnormal numbers
+assign A_subnormal= (&(~(Mantissa_Generator_input_IEEE_A[std-1:man+1]))) ;
+assign Mantissa_Generator_output_A_Sub_norm = A_subnormal & Mantissa_Generator_input_Activation_signal;
+
+assign B_subnormal= (&(~(Mantissa_Generator_input_IEEE_B[std-1:man+1]))) ;
+assign Mantissa_Generator_output_B_Sub_norm = B_subnormal & Mantissa_Generator_input_Activation_signal;
+
+assign C_subnormal= (&(~(Mantissa_Generator_input_IEEE_C[std-1:man+1]))) ;
+
+//check for positive and negative exponents;
+assign Mantissa_Generator_output_A_neg_exp = ( (~(A_subnormal)) & ( ~(Mantissa_Generator_input_IEEE_A[std-1]) ) & (~ ( & (Mantissa_Generator_input_IEEE_A[std-2:man+1]) ) ));
+assign Mantissa_Generator_output_A_pos_exp = ( (~(A_subnormal)) & (~(Mantissa_Generator_output_A_neg_exp))) ;
+assign Mantissa_Generator_output_B_neg_exp = ( (~(B_subnormal)) & ( ~(Mantissa_Generator_input_IEEE_B[std-1]) ) & (~ ( & (Mantissa_Generator_input_IEEE_B[std-2:man+1]) ) ));
+assign Mantissa_Generator_output_B_pos_exp = ( (~(B_subnormal)) & (~(Mantissa_Generator_output_B_neg_exp)) );
+
+//main functionality
+/*assign Mantissa_Generator_output_IEEE_A = ( Mantissa_Generator_input_Activation_signal ) ? ( (A_subnormal) ? { Mantissa_Generator_input_IEEE_A[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_A[man:0] } : {Mantissa_Generator_input_IEEE_A[std], Mantissa_Generator_input_IEEE_A[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_A[man:0] }) : {64'h0000000000000000 , 1'b0 } ;
+assign Mantissa_Generator_output_IEEE_B = ( Mantissa_Generator_input_Activation_signal ) ? ( (B_subnormal) ? { Mantissa_Generator_input_IEEE_B[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_B[man:0] } : {Mantissa_Generator_input_IEEE_B[std], Mantissa_Generator_input_IEEE_B[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_B[man:0] }) : {64'h0000000000000000 , 1'b0 } ;
+assign Mantissa_Generator_output_IEEE_C = ( Mantissa_Generator_input_Activation_signal ) ? ( (C_subnormal) ? { Mantissa_Generator_input_IEEE_C[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_C[man:0] } : {Mantissa_Generator_input_IEEE_C[std], Mantissa_Generator_input_IEEE_C[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_C[man:0] }) : {64'h0000000000000000 , 1'b0 } ;
+*/
+assign Mantissa_Generator_output_IEEE_A = ( Mantissa_Generator_input_Activation_signal ) ? ( (A_subnormal) ? { Mantissa_Generator_input_IEEE_A[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_A[man:0] } : {Mantissa_Generator_input_IEEE_A[std], Mantissa_Generator_input_IEEE_A[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_A[man:0] }) : {{std{1'b0}},1'b0, 1'b0 } ;
+assign Mantissa_Generator_output_IEEE_B = ( Mantissa_Generator_input_Activation_signal ) ? ( (B_subnormal) ? { Mantissa_Generator_input_IEEE_B[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_B[man:0] } : {Mantissa_Generator_input_IEEE_B[std], Mantissa_Generator_input_IEEE_B[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_B[man:0] }) : {{std{1'b0}},1'b0, 1'b0 } ;
+assign Mantissa_Generator_output_IEEE_C = ( Mantissa_Generator_input_Activation_signal ) ? ( (C_subnormal) ? { Mantissa_Generator_input_IEEE_C[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_C[man:0] } : {Mantissa_Generator_input_IEEE_C[std], Mantissa_Generator_input_IEEE_C[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_C[man:0] }) : {{std{1'b0}},1'b0, 1'b0 } ;
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_mantissa_multiplication.v b/verilog/rtl/FPU/FMADD_mantissa_multiplication.v
new file mode 100644
index 0000000..4c0c0e3
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_mantissa_multiplication.v
@@ -0,0 +1,16 @@
+// mantissa_mutliplication_nodule is resposible
+
+module FMADD_Mantissa_Multiplication (Mantissa_Multiplication_input_A,Mantissa_Multiplication_input_B,Mantissa_Multiplication_input_Activation_Signal,Mantissa_Multiplication_output_Mantissa);
+parameter man = 22;
+parameter exp = 7;
+
+//declaration of inputs
+input [man+1:0] Mantissa_Multiplication_input_A,Mantissa_Multiplication_input_B;
+input Mantissa_Multiplication_input_Activation_Signal;
+//declaration
+output [man+man+3:0] Mantissa_Multiplication_output_Mantissa;
+
+//main functionality
+assign Mantissa_Multiplication_output_Mantissa = (Mantissa_Multiplication_input_Activation_Signal) ? Mantissa_Multiplication_input_A * Mantissa_Multiplication_input_B: {2{{2'b00, {man{1'b0}}}}};
+
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_rounding_block_Addition.v b/verilog/rtl/FPU/FMADD_rounding_block_Addition.v
new file mode 100644
index 0000000..509e51c
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_rounding_block_Addition.v
@@ -0,0 +1,60 @@
+//moduel resposible for exponent matching
+
+module FMADD_Roudning_Block_Addition( Rounding_Block_input_Mantissa,Rounding_Block_input_Exponent,Rounding_Block_input_Sign,Rounding_Block_input_Guard,Rounding_Block_input_Round,Rounding_Block_input_Sticky,Rounding_Block_input_Frm,Rounding_Block_output_Exponent,Rounding_Block_output_Sign,Rounding_Block_output_Mantissa,Rounding_Block_output_S_Flags);
+
+//declaration of paramters
+parameter std = 31;
+parameter man = 22;
+parameter exp = 7;
+
+//declaration of inputs
+input [man+1:0] Rounding_Block_input_Mantissa;
+input [exp+1:0] Rounding_Block_input_Exponent;
+input Rounding_Block_input_Sign,Rounding_Block_input_Guard,Rounding_Block_input_Round,Rounding_Block_input_Sticky;
+input [2:0] Rounding_Block_input_Frm;
+
+//declaration of outputs
+output [man:0] Rounding_Block_output_Mantissa;
+output [exp:0] Rounding_Block_output_Exponent;
+output Rounding_Block_output_Sign;
+output [1:0] Rounding_Block_output_S_Flags;
+
+//interim wires
+wire Rounding_Block_Bit_pos_inf;
+wire Rounding_Block_Bit_neg_inf;
+wire Rounding_Block_Bit_RNE;
+wire Rounding_Block_Bit_RN_MM;
+wire Rounding_Block_Bit_Round_up;
+wire [man+1:0] Rounding_Block_interim_Mantissa;
+wire Rounding_Block_Bit_Carry;
+wire [man+1:0] Rounding_Block_Shifter_output;
+wire [exp+1:0] Rounding_Block_interim_exponent;
+wire [exp:0] Rounding_Block_final_exponent;
+wire Roinding_Block_Overflow_check;
+
+
+//main functionality
+assign Rounding_Block_Bit_pos_inf = ( (Rounding_Block_input_Guard) | (Rounding_Block_input_Round) | (Rounding_Block_input_Sticky) ) & ( ~(Rounding_Block_input_Sign) );
+assign Rounding_Block_Bit_neg_inf = ( (Rounding_Block_input_Guard) | (Rounding_Block_input_Round) | (Rounding_Block_input_Sticky) ) & (Rounding_Block_input_Sign);
+assign Rounding_Block_Bit_RNE = ( Rounding_Block_input_Guard & ( Rounding_Block_input_Round | Rounding_Block_input_Sticky )) | ( ( Rounding_Block_input_Guard & ( (~Rounding_Block_input_Round) & (~Rounding_Block_input_Sticky) )) & Rounding_Block_input_Mantissa[0] );
+assign Rounding_Block_Bit_RN_MM = ( Rounding_Block_input_Guard & ( Rounding_Block_input_Round | Rounding_Block_input_Sticky )) | ( Rounding_Block_input_Guard & ( (~Rounding_Block_input_Round) & (~Rounding_Block_input_Sticky) ));
+
+assign Rounding_Block_Bit_Round_up = (Rounding_Block_input_Frm == 3'b011) ? Rounding_Block_Bit_pos_inf : (Rounding_Block_input_Frm == 3'b010) ? Rounding_Block_Bit_neg_inf : (Rounding_Block_input_Frm == 3'b000) ? Rounding_Block_Bit_RNE : (Rounding_Block_input_Frm == 3'b100) ? Rounding_Block_Bit_RN_MM : 1'b0;
+
+assign { Rounding_Block_Bit_Carry, Rounding_Block_interim_Mantissa} = {1'b0,Rounding_Block_input_Mantissa} + Rounding_Block_Bit_Round_up ;
+assign Rounding_Block_Shifter_output = (Rounding_Block_Bit_Carry) ? { Rounding_Block_Bit_Carry , Rounding_Block_interim_Mantissa[man+1:1]} : Rounding_Block_interim_Mantissa[man+1:0] ;
+assign Rounding_Block_interim_exponent = Rounding_Block_input_Exponent + Rounding_Block_Bit_Carry;
+assign Roinding_Block_Overflow_check = (Rounding_Block_interim_exponent == 9'h0ff );
+
+
+assign Rounding_Block_final_exponent = (Roinding_Block_Overflow_check) ? {exp+1{1'b1}} : Rounding_Block_interim_exponent[exp:0] ;
+assign Rounding_Block_output_Exponent = (Rounding_Block_Shifter_output[man+1] ) ? Rounding_Block_final_exponent : {exp+1{1'b0}} ;
+assign Rounding_Block_output_Mantissa = (Roinding_Block_Overflow_check) ? {man+1 {1'b0}} : Rounding_Block_Shifter_output[man:0];
+assign Rounding_Block_output_Sign = Rounding_Block_input_Sign;
+//delcaration of inexact flag
+assign Rounding_Block_output_S_Flags[0] = Rounding_Block_input_Round | Rounding_Block_input_Guard | Rounding_Block_input_Sticky;
+//declaration of overflow flag
+assign Rounding_Block_output_S_Flags[1] = Roinding_Block_Overflow_check ;
+
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
new file mode 100644
index 0000000..26dfafa
--- /dev/null
+++ b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
@@ -0,0 +1,59 @@
+module FMADD_ROUND_MUL(FMADD_ROUND_MUL_input_overflow, FMADD_ROUND_MUL_input_sticky_PN, FMADD_ROUND_MUL_input_no, FMADD_ROUND_MUL_input_rm, FMADD_ROUND_MUL_output_no, FMADD_ROUND_MUL_output_S_Flags);
+
+parameter std=31;
+parameter man =22;
+parameter exp = 7;
+parameter biad = 127;
+
+
+input [man+man+exp+5 : 0]FMADD_ROUND_MUL_input_no;
+input [2 : 0] FMADD_ROUND_MUL_input_rm;
+input FMADD_ROUND_MUL_input_overflow;
+input FMADD_ROUND_MUL_input_sticky_PN;
+
+output [std : 0] FMADD_ROUND_MUL_output_no;
+output [2 : 0]FMADD_ROUND_MUL_output_S_Flags;
+assign FMADD_ROUND_MUL_output_S_Flags = {FMADD_ROUND_MUL_output_overflow,FMADD_ROUND_MUL_output_underflow,FMADD_ROUND_MUL_output_inexact};
+
+
+wire FMADD_ROUND_MUL_output_inexact, FMADD_ROUND_MUL_output_underflow, FMADD_ROUND_MUL_output_overflow;
+wire FMADD_ROUND_MUL_wire_guard, FMADD_ROUND_MUL_wire_round, FMADD_ROUND_MUL_wire_sticky;
+wire FMADD_ROUND_MUL_wire_condition_inf, FMADD_ROUND_MUL_wire_condition_rnte, FMADD_ROUND_MUL_wire_condition_rntmm;
+wire FMADD_ROUND_MUL_wire_condition_sticky;
+wire FMADD_ROUND_MUL_wire_inc;
+wire [man+1 : 0] FMADD_ROUND_MUL_wire_rounded_man;
+wire [exp : 0] FMADD_ROUND_MUL_wire_rounded_exp;
+wire [man : 0] FMADD_ROUND_MUL_wire_final_man;
+
+assign FMADD_ROUND_MUL_wire_guard = FMADD_ROUND_MUL_input_no[man+1];
+assign FMADD_ROUND_MUL_wire_round = FMADD_ROUND_MUL_input_no[man];
+assign FMADD_ROUND_MUL_wire_sticky = |FMADD_ROUND_MUL_input_no[man-1 : 0];
+
+assign FMADD_ROUND_MUL_wire_condition_inf = ((FMADD_ROUND_MUL_wire_round | FMADD_ROUND_MUL_wire_guard | (FMADD_ROUND_MUL_wire_sticky)) & ((FMADD_ROUND_MUL_input_rm == 3'b011 & ~FMADD_ROUND_MUL_input_no[man+2+man+2+exp+1])|(FMADD_ROUND_MUL_input_rm == 3'b010 & FMADD_ROUND_MUL_input_no[man+2+man+2+exp+1])));
+assign FMADD_ROUND_MUL_wire_condition_rnte = (FMADD_ROUND_MUL_input_rm == 3'b000 & ((FMADD_ROUND_MUL_wire_guard & (FMADD_ROUND_MUL_wire_round | (FMADD_ROUND_MUL_wire_sticky))) | (FMADD_ROUND_MUL_wire_guard & ((~FMADD_ROUND_MUL_wire_round) & ~(FMADD_ROUND_MUL_wire_sticky)) & FMADD_ROUND_MUL_input_no[man+2])));
+assign FMADD_ROUND_MUL_wire_condition_rntmm = (FMADD_ROUND_MUL_input_rm == 3'b100 & ((FMADD_ROUND_MUL_wire_guard & (FMADD_ROUND_MUL_wire_round | (FMADD_ROUND_MUL_wire_sticky))) | (FMADD_ROUND_MUL_wire_guard & ((~FMADD_ROUND_MUL_wire_round) & ~(FMADD_ROUND_MUL_wire_sticky)))));
+assign FMADD_ROUND_MUL_wire_condition_sticky = FMADD_ROUND_MUL_input_sticky_PN & (((!FMADD_ROUND_MUL_input_no[man+man+exp+5]) & (FMADD_ROUND_MUL_input_rm == 3'b011)) | (FMADD_ROUND_MUL_input_no[man+man+exp+5] & (FMADD_ROUND_MUL_input_rm == 3'b010)));
+//FMADD_ROUND_MUL_wire_condition_sticky logic for rounding on the basis os STICKY bit coming from previous module, inc is done incase sticky_pn == 1 and sign == 0 and rm == 3 OR sticky_pn == 1 and sign ==1 and rm == 10
+
+// Add 1 in case rounding says so. Input_overflow is added so that inc becomes ineffective in case overflow is high
+assign FMADD_ROUND_MUL_wire_inc = (FMADD_ROUND_MUL_wire_condition_inf | FMADD_ROUND_MUL_wire_condition_rnte | FMADD_ROUND_MUL_wire_condition_rntmm | FMADD_ROUND_MUL_wire_condition_sticky) & (!FMADD_ROUND_MUL_input_overflow);
+assign FMADD_ROUND_MUL_wire_rounded_man = FMADD_ROUND_MUL_input_no[man+2+man+1 : man+2] + FMADD_ROUND_MUL_wire_inc;
+
+//If hidden bit before rounding is zero and after rounding is one then add one in exponent other wise don't
+assign FMADD_ROUND_MUL_wire_rounded_exp = ((!FMADD_ROUND_MUL_input_no[man+2+man+1]) & (FMADD_ROUND_MUL_wire_rounded_man[man+1])) ?
+FMADD_ROUND_MUL_input_no[man+2+man+2+exp : man+2+man+2] + 1'b1 : FMADD_ROUND_MUL_input_no[man+2+man+2+exp : man+2+man+2];
+
+//overflow occurs in case the exp and man before rounding is complete zero.
+assign FMADD_ROUND_MUL_output_underflow = &(!FMADD_ROUND_MUL_input_no[man+man+exp+4]);
+//Inexact is high in case any of the GRS are high or if overflow has occured
+assign FMADD_ROUND_MUL_output_inexact = FMADD_ROUND_MUL_wire_guard | FMADD_ROUND_MUL_wire_round | FMADD_ROUND_MUL_wire_sticky | FMADD_ROUND_MUL_input_sticky_PN | FMADD_ROUND_MUL_input_overflow;
+//overflow is detected in previous module of PN
+assign FMADD_ROUND_MUL_output_overflow = FMADD_ROUND_MUL_input_overflow;
+
+assign FMADD_ROUND_MUL_wire_final_man = FMADD_ROUND_MUL_output_overflow ?
+( {(man+1){1'b0}} ) : FMADD_ROUND_MUL_wire_rounded_man[man : 0];
+
+assign FMADD_ROUND_MUL_output_no = {FMADD_ROUND_MUL_input_no[man+man+exp+5], FMADD_ROUND_MUL_wire_rounded_exp, FMADD_ROUND_MUL_wire_final_man[man:0]};
+
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FPU_CSR.v b/verilog/rtl/FPU/FPU_CSR.v
new file mode 100644
index 0000000..fd3fa85
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_CSR.v
@@ -0,0 +1,40 @@
+module FPU_CSR(clk,rst_l,CSR_Read,CSR_Write,CSR_Addr,CSR_Write_Data,CSR_Read_Data,S_flag,fpu_active,fpu_complete,illegal_instr,Fpu_Frm);
+ input clk,rst_l,CSR_Write,CSR_Read,fpu_active,fpu_complete,illegal_instr;
+ input [11:0]CSR_Addr;
+ input [31:0]CSR_Write_Data;
+ input [4:0]S_flag;
+ output [31:0]CSR_Read_Data;
+ output [2:0] Fpu_Frm;
+
+ reg [4:0] fflag;
+ reg [2:0] frm;
+ reg [31:0]fcsr;
+ wire fflag_w,frm_w,fcsr_w;
+
+ assign fflag_w = (~rst_l) ? 1'b0 : (CSR_Addr == 12'h001) ? 1'b1 : 1'b0;
+ assign frm_w = (~rst_l) ? 1'b0 : (CSR_Addr == 12'h002) ? 1'b1 : 1'b0;
+ assign fcsr_w = (~rst_l) ? 1'b0 : (CSR_Addr == 12'h003) ? 1'b1 : 1'b0;
+ assign CSR_Read_Data = (~rst_l) ? 32'h00000000 : (({32{(CSR_Read & fflag_w)}} & {27'h000000,fflag}) |
+ ({32{(CSR_Read & frm_w)}} & {29'h0000000,frm}) |
+ ({32{(CSR_Read & fcsr_w)}} & fcsr));
+ assign Fpu_Frm = (~rst_l) ? 3'b000 : (fpu_active & (~illegal_instr)) ? frm : 3'b000;
+
+
+ always @ (posedge clk)
+ begin
+ if (~rst_l)
+ begin
+ fflag <= 5'b00000;
+ frm <= 3'b000;
+ fcsr <= 32'h00000000;
+ end
+
+ else
+ begin
+ fflag <= (fflag_w & CSR_Write) ? CSR_Write_Data[4:0] : (fcsr_w & CSR_Write) ? CSR_Write_Data[4:0] : (fpu_complete) ? (fflag[4:0] | S_flag[4:0]) : fflag;
+ frm <= (frm_w & CSR_Write) ? CSR_Write_Data[2:0] : (fcsr_w & CSR_Write) ? CSR_Write_Data[7:5] : frm;
+ fcsr <= (fcsr_w & CSR_Write) ? {24'h00000,CSR_Write_Data[7:0]} : (fpu_complete) ? ({24'h000000,frm,(fflag[4:0] | S_flag[4:0])}) : fcsr;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FPU_F2I.v b/verilog/rtl/FPU/FPU_F2I.v
new file mode 100644
index 0000000..d25afda
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_F2I.v
@@ -0,0 +1,188 @@
+module FPU_Float_to_Int(FLOAT_TO_INT_input_float, FLOAT_TO_INT_input_rm, FLOAT_TO_INT_input_opcode_FI, FLOAT_TO_INT_input_opcode_signed, FLOAT_TO_INT_input_opcode_unsigned, rst_l, FLOAT_TO_INT_output_int, FLOAT_TO_INT_output_invalid_flag, FLOAT_TO_INT_output_inexact_flag);
+
+parameter std = 15;//Bfloat16 and IEEE16
+//parameter std = 31;//IEEE32
+//parameter std = 63;//IEEE64
+
+parameter man = 9;//IEEE16
+//parameter man = 6;//Bfloat16
+//parameter man = 22;//IEEE32
+//parameter man = 51;//IEEE64
+
+parameter exp = 4;//IEEE16
+//parameter exp = 7;//IEEE32 and Bfloat16
+//parameter exp = 10;//IEEE64
+
+//parameter bias = 127;//Bfloat16
+parameter bias = 15;//16
+//parameter bias = 127;//32
+//parameter bias = 1023;//64
+
+input [std : 0]FLOAT_TO_INT_input_float;
+input [2:0]FLOAT_TO_INT_input_rm;
+input FLOAT_TO_INT_input_opcode_FI;
+input FLOAT_TO_INT_input_opcode_signed;
+input FLOAT_TO_INT_input_opcode_unsigned;
+input rst_l;
+
+
+output [31 : 0]FLOAT_TO_INT_output_int;
+output FLOAT_TO_INT_output_invalid_flag;
+output FLOAT_TO_INT_output_inexact_flag;
+
+initial
+begin
+$dumpfile("Dump.vcd");
+$dumpvars(0);
+end
+
+
+wire [std : 0] FLOAT_TO_INT_input_wire_float;
+wire [63 : 0]FLOAT_TO_INT_wire_float_mapped;
+wire [10 : 0]FLOAT_TO_INT_wire_shifts_interim;
+wire [10 : 0]FLOAT_TO_INT_wire_shifts_final;
+wire [83 : 0]FLOAT_TO_INT_wire_shifted_data;
+wire FLOAT_TO_INT_wire_condition_inf, FLOAT_TO_INT_wire_condition_rnte, FLOAT_TO_INT_wire_condition_rntmm;
+wire FLOAT_TO_INT_wire_rounding;
+wire [31 : 0]FLOAT_TO_INT_wire_rounded_int;
+wire [31 : 0]FLOAT_TO_INT_wire_main_output;
+wire FLOAT_TO_INT_bit_exception_for_max_caught, FLOAT_TO_INT_bit_exception_for_min_caught, FLOAT_TO_INT_bit_pos_infinity_caught, FLOAT_TO_INT_bit_neg_infinity_caught, FLOAT_TO_INT_bit_NaN_caught, FLOAT_TO_INT_bit_subnormal_caught;
+wire FLOAT_TO_INT_wire_max, FLOAT_TO_INT_wire_min;
+wire FLOAT_TO_INT_bit_fraction_caught;
+wire [31 : 0]FLOAT_TO_INT_wire_output_interim_1_1, FLOAT_TO_INT_wire_output_exceptions, FLOAT_TO_INT_wire_output_interim_1_2;
+wire FLOAT_TO_INT_bit_exception_for_max_1_caught, FLOAT_TO_INT_bit_exception_for_max_2_caught, FLOAT_TO_INT_bit_exception_for_min_1_caught;
+wire FLOAT_TO_INT_wire_hidden_bit_decision;
+
+//Setting the input to zero if rst_l or opcode_FI is low
+assign FLOAT_TO_INT_input_wire_float = (FLOAT_TO_INT_input_opcode_FI && rst_l) ? FLOAT_TO_INT_input_float
+
+//Mapping the data to 64bit precision std
+assign FLOAT_TO_INT_wire_float_mapped = {FLOAT_TO_INT_input_wire_float[std], (FLOAT_TO_INT_input_wire_float[std-1 : man+1] - bias[exp : 0] + 11'b011_1111_1111), ( {FLOAT_TO_INT_input_wire_float[man:0], {(51-man){1'b0}}} ) };
+
+//Calculating shift amount
+assign FLOAT_TO_INT_wire_shifts_interim = (11'b10000011110 - FLOAT_TO_INT_wire_float_mapped[62:52]);
+
+//Setting the shifts to 83 incase they are greater than 83, 83 not 84 cause hidden 1 is letter required for rounding in case of fraction and subnormal numbers
+assign FLOAT_TO_INT_wire_shifts_final = (FLOAT_TO_INT_wire_shifts_interim > 84) ? (11'b000_0101_0011) : FLOAT_TO_INT_wire_shifts_interim ;
+
+// Exponent and mantissa are all zero only in case of zeros, Hidden bit is set to zero only for the case of ) for subnormals it is not set to zero since setting it one will make the STICKY bit 1 (due to how the RTL is done which), sticky being one sets the inexact flag to 1.
+assign FLOAT_TO_INT_wire_hidden_bit_decision = (|FLOAT_TO_INT_input_wire_float[std-1 : 0]);
+assign FLOAT_TO_INT_wire_shifted_data = {FLOAT_TO_INT_wire_hidden_bit_decision, FLOAT_TO_INT_wire_float_mapped[51:0],31'b0000000000000000000000000000000} >> (FLOAT_TO_INT_wire_shifts_final);
+
+//Calculating incrementing conditions, if any of the three is high increment is to be done
+assign FLOAT_TO_INT_wire_condition_inf = ((FLOAT_TO_INT_wire_shifted_data[50] | FLOAT_TO_INT_wire_shifted_data[51] | (|FLOAT_TO_INT_wire_shifted_data[49:0])) & ((FLOAT_TO_INT_input_rm == 3'b011 & ~FLOAT_TO_INT_wire_float_mapped[63])|(FLOAT_TO_INT_input_rm == 3'b010 & FLOAT_TO_INT_wire_float_mapped[63])));
+assign FLOAT_TO_INT_wire_condition_rnte = (FLOAT_TO_INT_input_rm == 3'b000 & ((FLOAT_TO_INT_wire_shifted_data[51] & (FLOAT_TO_INT_wire_shifted_data[50] | (|FLOAT_TO_INT_wire_shifted_data[49:0]))) | (FLOAT_TO_INT_wire_shifted_data[51] & ((~FLOAT_TO_INT_wire_shifted_data[50]) & ~(|FLOAT_TO_INT_wire_shifted_data[49:0])) & FLOAT_TO_INT_wire_shifted_data[52])));
+assign FLOAT_TO_INT_wire_condition_rntmm = (FLOAT_TO_INT_input_rm == 3'b100 & ((FLOAT_TO_INT_wire_shifted_data[51] & (FLOAT_TO_INT_wire_shifted_data[50] | (|FLOAT_TO_INT_wire_shifted_data[49:0]))) | (FLOAT_TO_INT_wire_shifted_data[51] & ((~FLOAT_TO_INT_wire_shifted_data[50]) & ~(|FLOAT_TO_INT_wire_shifted_data[49:0])))));
+
+assign FLOAT_TO_INT_wire_rounding = FLOAT_TO_INT_wire_condition_inf | FLOAT_TO_INT_wire_condition_rnte | FLOAT_TO_INT_wire_condition_rntmm;
+
+//Roudning the Data
+assign FLOAT_TO_INT_wire_rounded_int = FLOAT_TO_INT_wire_shifted_data[83:52] + FLOAT_TO_INT_wire_rounding ;
+
+//Converting it to 2's compliment depending on opcode and sign of the number
+assign FLOAT_TO_INT_wire_main_output = (FLOAT_TO_INT_input_wire_float[std]) ? ((~FLOAT_TO_INT_wire_rounded_int)+1'b1) : (FLOAT_TO_INT_wire_rounded_int) ;
+
+//-------------------------------------EXCEPTION LOGIC---------------------------------------
+
+assign FLOAT_TO_INT_bit_exception_for_max_caught =
+(((!FLOAT_TO_INT_input_wire_float[std])& //If sign is 0 +ve
+(FLOAT_TO_INT_input_wire_float[std-1 : man+1] > 30+bias) & //Exponent is greater than 30
+(~(&FLOAT_TO_INT_input_wire_float[std-1 : man+1]))& //Exponent is not all 1 (INF and NAN)
+(FLOAT_TO_INT_input_opcode_signed)) //Signed operation is being carried out
+|
+((!FLOAT_TO_INT_input_wire_float[std])& //If sign is zero +ve
+(FLOAT_TO_INT_input_wire_float[std-1 : man+1] > 31+bias) & //Exponent is greater than 31
+(~(&FLOAT_TO_INT_input_wire_float[std-1 : man+1]))& //Exponent is not all 1 (INF and NAN)
+(FLOAT_TO_INT_input_opcode_unsigned))); //Unsigned operation is being carried out
+
+assign FLOAT_TO_INT_bit_exception_for_min_caught =
+(((FLOAT_TO_INT_wire_float_mapped[63])&
+(((FLOAT_TO_INT_wire_float_mapped[62 : 52] == 31+1023) & ((|FLOAT_TO_INT_wire_float_mapped[51 : 22]))) | (FLOAT_TO_INT_wire_float_mapped[62 : 52] > 31+1023))&
+(~(&FLOAT_TO_INT_wire_float_mapped[62 : 52]))&
+(FLOAT_TO_INT_input_opcode_signed))
+|
+(FLOAT_TO_INT_input_opcode_unsigned&
+(FLOAT_TO_INT_input_wire_float[std])));
+
+/*
+assign FLOAT_TO_INT_bit_exception_for_min_caught =
+(std == 63) ?
+(((FLOAT_TO_INT_input_wire_float[std])&
+(((FLOAT_TO_INT_input_wire_float[std-1 : man+1] == 31+bias) & ((|FLOAT_TO_INT_input_wire_float[51 : 22]))) | (FLOAT_TO_INT_input_wire_float[std-1 : man+1] > 31+bias))&
+(~(&FLOAT_TO_INT_input_wire_float[std-1 : man+1]))&
+(FLOAT_TO_INT_input_opcode_signed))
+|
+(FLOAT_TO_INT_input_opcode_unsigned&
+(FLOAT_TO_INT_input_wire_float[std])))
+:
+(((FLOAT_TO_INT_input_wire_float[std])&
+(((FLOAT_TO_INT_input_wire_float[std-1 : man+1] == 31+bias) & (|FLOAT_TO_INT_input_wire_float[man : 0])) | (FLOAT_TO_INT_input_wire_float[std-1 : man+1] > 31+bias))&
+(~(&FLOAT_TO_INT_input_wire_float[std-1 : man+1]))&
+(FLOAT_TO_INT_input_opcode_signed))
+|
+(FLOAT_TO_INT_input_opcode_unsigned&
+(FLOAT_TO_INT_input_wire_float[std])))
+;
+*/
+
+//Checking for +ve INF
+assign FLOAT_TO_INT_bit_pos_infinity_caught = ((~FLOAT_TO_INT_input_wire_float[std]) & (&FLOAT_TO_INT_input_wire_float[std-1 : man+1]) & (&(~FLOAT_TO_INT_input_wire_float[man:0])));
+
+//Checking for -ve INF
+assign FLOAT_TO_INT_bit_neg_infinity_caught = ((FLOAT_TO_INT_input_wire_float[std]) & (&FLOAT_TO_INT_input_wire_float[std-1 : man+1]) & (&(~FLOAT_TO_INT_input_wire_float[man:0])));
+
+//Checking for NANs
+assign FLOAT_TO_INT_bit_NaN_caught = ((&FLOAT_TO_INT_input_wire_float[std-1 : man+1]) & (|FLOAT_TO_INT_input_wire_float[man:0]));
+
+//Checking for subnormal numbers
+assign FLOAT_TO_INT_bit_subnormal_caught = (FLOAT_TO_INT_input_wire_float[std-1 : man+1] == 0) & (|FLOAT_TO_INT_input_wire_float[man:0]);
+
+//Exponent is lesser than BIAS means number is a fraction, Exponent is not all zero means number is not zero and number is not a subnormal. Condition of subnormal and zero is added since EXP of these numbers is 0 and 0 is lesser than BIAS
+assign FLOAT_TO_INT_bit_fraction_caught = (FLOAT_TO_INT_input_wire_float[std-1 : man+1] < bias) & (|FLOAT_TO_INT_input_wire_float[std-1 : man+1]) & (!FLOAT_TO_INT_bit_subnormal_caught);
+
+//Number goes out of range due to rounding
+//Signed max
+assign FLOAT_TO_INT_bit_exception_for_max_1_caught =
+((!FLOAT_TO_INT_wire_float_mapped[std])& //If sign is zero +ve
+(FLOAT_TO_INT_wire_float_mapped[62:52] == 30+1023) & //Exponent == 30
+(~(&FLOAT_TO_INT_wire_float_mapped[62:52]))& //Exponent is not all 1 (INF and NAN)
+(&FLOAT_TO_INT_wire_float_mapped[51 : 21])& //MSB 32 are all 1
+(FLOAT_TO_INT_wire_rounding)& //Rounding is to be done
+(FLOAT_TO_INT_input_opcode_signed)); //Signed operation is being carried out
+
+//Unsigned max
+assign FLOAT_TO_INT_bit_exception_for_max_2_caught =
+((!FLOAT_TO_INT_wire_float_mapped[std])& //If sign is zero +ve
+(FLOAT_TO_INT_wire_float_mapped[62:52] == 31+1023) & //Exponent == 31
+(~(&FLOAT_TO_INT_wire_float_mapped[62:52]))& //Exponent is not all 1 (INF and NAN)
+(&FLOAT_TO_INT_wire_float_mapped[51 : 21])& //MSB 32 are all 1
+(FLOAT_TO_INT_wire_rounding)& //Rounding is to be done
+(FLOAT_TO_INT_input_opcode_unsigned)); //Unsigned operation is being carried out
+
+//Signed min, Unsigned min is zero so no need to implement rounding logic for that
+assign FLOAT_TO_INT_bit_exception_for_min_1_caught =
+((FLOAT_TO_INT_wire_float_mapped[std])& //If sign is one -ve
+(FLOAT_TO_INT_wire_float_mapped[62:52] == 31+1023)& //Exponent == 31
+(!(|FLOAT_TO_INT_wire_float_mapped[51 : 21]))& //Integer bits of mantissa are all zero
+(~(&FLOAT_TO_INT_wire_float_mapped[62:52]))& //Exponent is not all 1 (INF and NAN)
+(FLOAT_TO_INT_wire_rounding)& //Rounding up is to done
+(FLOAT_TO_INT_input_opcode_signed)); //Signed operation is to be done
+
+assign FLOAT_TO_INT_wire_max = FLOAT_TO_INT_bit_exception_for_max_caught | FLOAT_TO_INT_bit_pos_infinity_caught | FLOAT_TO_INT_bit_NaN_caught | FLOAT_TO_INT_bit_exception_for_max_1_caught | FLOAT_TO_INT_bit_exception_for_max_2_caught;
+//Subnormal and fraction are removed from min condition since they can be handled by main unit it self
+assign FLOAT_TO_INT_wire_min = FLOAT_TO_INT_bit_exception_for_min_caught | FLOAT_TO_INT_bit_neg_infinity_caught | FLOAT_TO_INT_bit_exception_for_min_1_caught;
+
+assign FLOAT_TO_INT_wire_output_interim_1_1 = (FLOAT_TO_INT_input_opcode_signed) ? 32'b0111_1111_1111_1111_1111_1111_1111_1111 : 32'b1111_1111_1111_1111_1111_1111_1111_1111 ;
+assign FLOAT_TO_INT_wire_output_interim_1_2 = (FLOAT_TO_INT_input_opcode_signed & (FLOAT_TO_INT_bit_exception_for_min_caught | FLOAT_TO_INT_bit_neg_infinity_caught | FLOAT_TO_INT_bit_exception_for_min_1_caught)) ? 32'b1000_0000_0000_0000_0000_0000_0000_0000 : 32'b0000_0000_0000_0000_0000_0000_0000_0000 ;
+
+assign FLOAT_TO_INT_wire_output_exceptions = (FLOAT_TO_INT_wire_max) ? FLOAT_TO_INT_wire_output_interim_1_1 : FLOAT_TO_INT_wire_output_interim_1_2 ;
+
+assign FLOAT_TO_INT_output_int = (FLOAT_TO_INT_wire_max | FLOAT_TO_INT_wire_min) ? FLOAT_TO_INT_wire_output_exceptions : FLOAT_TO_INT_wire_main_output ;
+
+//STICKY bit is getting high for exceptional data therefore in case of exceptional data inexact flag is nulified so that it doesnt get high
+assign FLOAT_TO_INT_output_inexact_flag = ((!FLOAT_TO_INT_wire_min) & (!FLOAT_TO_INT_wire_max)) & (| FLOAT_TO_INT_wire_shifted_data[50] | FLOAT_TO_INT_wire_shifted_data[51] | (|FLOAT_TO_INT_wire_shifted_data[49:0]));
+
+
+assign FLOAT_TO_INT_output_invalid_flag = FLOAT_TO_INT_wire_max | FLOAT_TO_INT_wire_min ;
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FPU_FSM_Control_Decode.v b/verilog/rtl/FPU/FPU_FSM_Control_Decode.v
new file mode 100644
index 0000000..8bd5804
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_FSM_Control_Decode.v
@@ -0,0 +1,104 @@
+module FPU_FSM(clk,rst_l,Active_Process,Activation_Signal,Memory_Activation,PC,Instruction,Instruction_out,Multi_Cycle);
+ input clk,rst_l,Activation_Signal,Active_Process,Multi_Cycle;
+ input [31:0]Instruction;
+ output Memory_Activation;
+ //output [23:0]Output_1_Hot_Encoded_Opcode;
+ output reg[31:0]PC;
+ output [31:0]Instruction_out;
+
+ //wire [23:0]Uncontrolled_Opcode;
+ reg [1:0]State;
+ wire [1:0]Next_State;
+ wire [4:0]Input_Opcode;
+ wire Exception;
+
+ /*
+ sfpu[0] = Fadd
+ sfpu[1] = Fsubb
+ sfpu[2] = Fmul
+ sfpu[3] = Fdiv
+ sfpu[4] = Fsqrt
+ sfpu[5] = Fmin
+ sfpu[6] = Fmax
+ sfpu[7] = Fmvx
+ sfpu[8] = Fmvf
+ sfpu[9] = feq
+ sfpu[10] = flt
+ sfpu[11] = fle
+ sfpu[12] = Fmadd
+ sfpu[13] = Fmsubb
+ sfpu[14] = FCVT.W.P
+ sfpu[15] = FCVT.P.W
+ sfpu[16] = Fnmsubb
+ sfpu[17] = Fnmadd
+ sfpu[18] = fsgnj
+ sfpu[19] = fsgnjn
+ sfpu[20] = fsgnjx
+ sfpu[21] = fclass
+ sfpu[22] = unsign
+ sfpu[23] = sign
+ */
+ /*
+ assign Input_Opcode = Instruction[4:0];
+
+ assign Output_1_Hot_Encoded_Opcode[0] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[1] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[2] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[3] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[4] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[5] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[6] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[7] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[8] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[9] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[10] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[11] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[12] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[13] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[14] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[15] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[16] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[17] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[18] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[19] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[20] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[21] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[22] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
+ assign Output_1_Hot_Encoded_Opcode[23] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
+
+ //assign Single_Cycle = (Output_1_Hot_Encoded_Opcode[0] | Output_1_Hot_Encoded_Opcode[1] | Output_1_Hot_Encoded_Opcode[2] | Output_1_Hot_Encoded_Opcode[5] | Output_1_Hot_Encoded_Opcode[6] | Output_1_Hot_Encoded_Opcode[7] | Output_1_Hot_Encoded_Opcode[8] | Output_1_Hot_Encoded_Opcode[9] | Output_1_Hot_Encoded_Opcode[10] | Output_1_Hot_Encoded_Opcode[11] | Output_1_Hot_Encoded_Opcode[14] | Output_1_Hot_Encoded_Opcode[15] | Output_1_Hot_Encoded_Opcode[18] | Output_1_Hot_Encoded_Opcode[19] | Output_1_Hot_Encoded_Opcode[20] | Output_1_Hot_Encoded_Opcode[21] | Output_1_Hot_Encoded_Opcode[22] | Output_1_Hot_Encoded_Opcode[23]);
+ assign Multi_Cycle = (Output_1_Hot_Encoded_Opcode[3] | Output_1_Hot_Encoded_Opcode[4] | Output_1_Hot_Encoded_Opcode[12] | Output_1_Hot_Encoded_Opcode[13] | Output_1_Hot_Encoded_Opcode[16] | Output_1_Hot_Encoded_Opcode[17]);
+ */
+ //assign Multi_Cycle = 1'b0;
+ assign Memory_Activation = (((~Next_State[1]) & (Next_State[0])) & (Active_Process));
+ assign Next_State[0] = (((~State[0]) & (State[1] | Active_Process)) | ((State[1] & State[0]) & ((~Activation_Signal) | (Activation_Signal & (~Multi_Cycle)))));
+ assign Next_State[1] = (((~State[1]) & (State[0])) | ((State[1]) & (~State[0])) | (State[1] & State[0] & (~Activation_Signal)));
+ assign Instruction_out = (~rst_l) ? 32'h00000000 : (State == 2'b10) ? Instruction : 32'h00000000;
+ always @(posedge clk)
+ PC <= (~rst_l) ? 32'h00000000 : ((State == 2'b01) ? (PC[31:0] + 4'h4) : (Instruction == 32'h00000010) ? 32'h00000000 : PC);
+
+ //sequential State register block
+ always @(posedge clk)
+ State <= (~rst_l) ? 2'b00 : Next_State;
+
+
+ //combinational State assignment block
+ /*always @(posedge clk)
+ begin
+ if(Next_State==2'b00)
+ Output_1_Hot_Encoded_Opcode <= 24'h000000;
+ else if(State==2'b01)
+ Output_1_Hot_Encoded_Opcode <= Uncontrolled_Opcode;
+ else
+ Output_1_Hot_Encoded_Opcode <= Uncontrolled_Opcode;
+ end*/
+
+ /*initial
+ begin
+ $dumpfile("FPU_FSM.vcd");
+ $dumpvars(0);
+ end*/
+
+endmodule
+
+
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
new file mode 100644
index 0000000..dd989dc
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -0,0 +1,174 @@
+`include "FPU_FSM_Control_Decode.v"
+`include "Sky130_SRAM_1kbyte_Memory.v"
+`include "uart_rx_prog.v"
+`include "iccm_controller.v"
+`include "Main_Decode.v"
+`include "Execution.v"
+`include "inst_checker.v"
+
+
+module FPU_FSM_TOP(r_Rx_Serial,clk,rst_l);
+
+ // FPU UART
+ input r_Rx_Serial;
+ // FPU UART
+
+ // FPU FSM
+ input clk,rst_l;
+ // FPU FSM
+
+ wire o_Rx_DV;
+ wire [7:0]o_Rx_Byte;
+ wire Active_Process;
+ wire we_o;
+ wire [31:0]wdata_o;
+ wire [13:0]addr_o;
+ wire [31:0]PC;
+ wire [31:0]Instruction;
+ wire Memory_Activation;
+ wire [31:0]result;
+ wire Activation_Signal;
+ wire Flag_ADDI,Flag_LI,Flag_CSR;
+ wire [31:0]RS1_d,RS2_d;
+ wire [31:0]Instruction_out;
+ wire Flag_Reset;
+ wire Flag_CSR_r;
+ wire Multi_Cycle;
+ wire stall_scalar;
+ wire scan_mode;
+ wire halt_req;
+ wire [3:0]float_control;
+ wire valid_execution;
+ wire illegal_config;
+ wire [15:0] fs1_data,fs2_data,fs3_data;
+ wire [2:0] fpu_pre,fpu_rounding;
+ wire [23:0] sfpu_op;
+ wire fpu_active,fpu_complete;
+ wire [15:0]fpu_result_1;
+ wire dec_i0_rs1_en_d,dec_i0_rs2_en_d;
+ wire [4:0]S_flag;
+ wire IV_exception;
+ wire[2:0]fpu_sel;
+ FPU_FSM FSM(
+ .clk(clk),
+ .rst_l(rst_l),
+ .Active_Process(Active_Process),
+ .Activation_Signal(Activation_Signal | Flag_CSR_r | fpu_complete),
+ .Memory_Activation(Memory_Activation),
+ .PC(PC),
+ .Instruction(Instruction),
+ .Instruction_out(Instruction_out),
+ .Multi_Cycle(stall_scalar)
+ );
+
+ sky130_sram_1kbyte_1rw1r_32x256_8 SKY130(
+ .clk0(clk),
+ .csb0(~we_o),
+ .web0(~we_o),
+ .wmask0(4'hF),
+ .addr0(addr_o[8:1]),
+ .din0(wdata_o),
+ .dout0(),
+ .clk1(clk),
+ .csb1(~Memory_Activation),
+ .addr1(PC[9:2]),
+ .dout1(Instruction)
+ );
+
+ eb1_iccm_controller ICCM_Controller(
+ .clk_i(clk),
+ .rst_ni(rst_l),
+ .rx_dv_i(o_Rx_DV),
+ .rx_byte_i(o_Rx_Byte),
+ .we_o(we_o),
+ .addr_o(addr_o),
+ .wdata_o(wdata_o),
+ .reset_o(Active_Process)
+ );
+ eb1_uart_rx_prog UART(
+ .i_Clock(clk),
+ .rst_ni(rst_l),
+ .i_Rx_Serial(r_Rx_Serial),
+ .CLKS_PER_BIT(16'd348),
+ .o_Rx_DV(o_Rx_DV),
+ .o_Rx_Byte(o_Rx_Byte)
+ );
+
+ Main_Decode Decoder(
+ .clk(clk),
+ .rst_l(rst_l),
+ .Instruction(Instruction_out),
+ .result(result),
+ .Flag_LI(Flag_LI),
+ .Flag_ADDI(Flag_ADDI),
+ .RS1_d(RS1_d),
+ .RS2_d(RS2_d),
+ .Activation_Signal(Activation_Signal),
+ .Flag_Reset(Flag_Reset),
+ .Flag_CSR(Flag_CSR),
+ .S_flag(S_flag),
+ .Flag_CSR_r(Flag_CSR_r),
+ .fpu_active(fpu_active),
+ .fpu_complete(fpu_complete),
+ .sfpu_op(sfpu_op),
+ .fpu_pre(fpu_pre),
+ .fs1_data(fs1_data),
+ .fs2_data(fs2_data),
+ .fs3_data(fs3_data),
+ .valid_execution(valid_execution),
+ .illegal_config(illegal_config),
+ .float_control(float_control),
+ .halt_req(halt_req),
+ .fpu_result_1(fpu_result_1),
+ .fpu_rounding(fpu_rounding),
+ .dec_i0_rs1_en_d(dec_i0_rs1_en_d),
+ .dec_i0_rs2_en_d(dec_i0_rs2_en_d),
+ .fpu_sel(fpu_sel)
+ );
+
+ Execution Excecution_Unit(
+ .clk(clk),
+ .rst_l(rst_l),
+ .RS1_d(RS1_d),
+ .RS2_d(RS2_d),
+ .result(result),
+ .Flag_ADDI(Flag_ADDI),
+ .Flag_LI(Flag_LI),
+ .Activation_Signal(Activation_Signal),
+ .Flag_Reset(Flag_Reset),
+ .fpu_active(fpu_active),
+ .illegal_config(illegal_config),
+ .valid_execution(valid_execution),
+ .fs1_data(fs1_data),
+ .fs2_data(fs2_data),
+ .fs3_data(fs3_data),
+ .sfpu_op(sfpu_op),
+ .fpu_pre(fpu_pre),
+ .fpu_rounding(fpu_rounding),
+ .float_control(float_control),
+ .fpu_result_1(fpu_result_1),
+ .S_flag(S_flag),
+ .dec_i0_rs1_en_d(dec_i0_rs1_en_d),
+ .dec_i0_rs2_en_d(dec_i0_rs2_en_d),
+ .IV_exception(IV_exception),
+ .fpu_complete(fpu_complete),
+ .fpu_sel(fpu_sel)
+ );
+
+ Inst_check Inst_Checker(
+ .clk(clk),
+ .rst_l(rst_l),
+ .inst_opcode(Instruction_out[6:0]),
+ .fpu_complete(fpu_complete),
+ .halt_req(halt_req),
+ .stall_scalar(stall_scalar),
+ .fpu_active(fpu_active)
+ );
+
+ initial
+ begin
+ $dumpfile("FPU_FSM.vcd");
+ $dumpvars(0);
+ end
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FPU_Fclass.v b/verilog/rtl/FPU/FPU_Fclass.v
new file mode 100644
index 0000000..6712098
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_Fclass.v
@@ -0,0 +1,55 @@
+module Parameterized_Classification_32 (Classification_Input,rst_l,Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output,Classification_Output);
+ // Parameters
+ parameter Std = 15; // Std = Std - 1
+ parameter Man = 7; // Mantissa
+ // Inputs
+ input [Std:0] Classification_Input;
+ input rst_l;
+ // Outputs
+ output Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output;
+ output [9:0] Classification_Output;
+
+ // Check to see if reset is either high or low
+ assign Classification_Output = rst_l ? {Classification_Qnan_Output,Classification_Snan_Output,Classification_Pos_Infinity_Output,Classification_Pos_Normal_Output, Classification_Pos_Subnormal_Output,Classification_Pos_Zero_Output,Classification_Neg_Zero_Output,Classification_Neg_Subnormal_Output,Classification_Neg_Normal_Output,Classification_Neg_Infinity_Output} : 10'b0000000000;
+
+
+ // -ve infinity
+ assign Classification_Neg_Infinity_Output = Classification_Input[Std] & (&(Classification_Input[Std-1:Man])) & (&(~Classification_Input[Man-1:0]));
+
+
+ // +ve infinity
+ assign Classification_Pos_Infinity_Output = ~Classification_Input[Std] & (&(Classification_Input[Std-1:Man])) & (&(~Classification_Input[Man-1:0]));
+
+
+ // -ve 0
+ assign Classification_Neg_Zero_Output = Classification_Input[Std] & (&(~Classification_Input[Std-1:0]));
+
+
+ // +ve 0
+ assign Classification_Pos_Zero_Output = ~Classification_Input[Std] & (&(~Classification_Input[Std-1:0]));
+
+
+ // snan
+ assign Classification_Snan_Output = &(Classification_Input[Std-1:Man]) & ~Classification_Input[Man-1] & (|(Classification_Input[Man-2:0]));
+
+
+ // qnan
+ assign Classification_Qnan_Output = &(Classification_Input[Std-1:Man]) & Classification_Input[Man-1] & (|(Classification_Input[Man-2:0]));
+
+
+ // +ve normal
+ assign Classification_Pos_Normal_Output = ~Classification_Input[Man] & (~(&(Classification_Input[Std-1:Man])) & (|(Classification_Input[Std-1:Man])));
+
+
+ // -ve normal
+ assign Classification_Neg_Normal_Output = Classification_Input[Std] & (~(&(Classification_Input[Std-1:Man])) & (|(Classification_Input[Std-1:Man])));
+
+
+ // +ve subnormal
+ assign Classification_Pos_Subnormal_Output = ~Classification_Input[Std] & (&(~Classification_Input[Std-1:Man])) & (|(Classification_Input[Man-1:0]));
+
+
+ // -ve subnormal
+ assign Classification_Neg_Subnormal_Output = Classification_Input[Std] & (&(~Classification_Input[Std-1:Man])) & (|(Classification_Input[Man-1:0]));
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/FPU_Input_Validation.v b/verilog/rtl/FPU/FPU_Input_Validation.v
new file mode 100644
index 0000000..11523fb
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_Input_Validation.v
@@ -0,0 +1,466 @@
+//Created for modular testing of intgeration in SwerV Core
+//synchorunus input validation
+//Created by Ali Raza
+
+
+
+
+
+module FPU_Input_Validation (rst_l,INPUT_VALIDATION_input_ieee_A,INPUT_VALIDATION_input_ieee_B,INPUT_VALIDATION_input_ieee_C,INPUT_VALIDATION_input_opcode,INPUT_VALIDATION_Output_temp_storage,INPUT_VALIDATION_Output_exception_flag_Fadd,INPUT_VALIDATION_Output_exception_flag_Fsub,INPUT_VALIDATION_Output_exception_flag_Fmul,INPUT_VALIDATION_Output_exception_flag_Fdiv,INPUT_VALIDATION_Output_exception_flag_Fsqrt,INPUT_VALIDATION_Output_exception_flag_Fcomp,INPUT_VALIDATION_Output_exception_flag_Fmadd,INPUT_VALIDATION_Output_exception_flag_Fmsub,INPUT_VALIDATION_Output_invalid_flag,INPUT_VALIDATION_Output_Flag_DZ,interupt_Pin);
+
+parameter std=31;
+parameter man= 22;
+parameter exp=7;
+parameter bias=8'b01111111;
+
+
+/*opcode ctivation signals
+
+sfpu[0] = Fadd
+sfpu[1] = Fsubb
+sfpu[2] = Fmul
+sfpu[3] = Fdiv
+sfpu[4] = Fsqrt
+sfpu[5] = Fmin
+sfpu[6] = Fmax
+sfpu[7] = Fmvx
+sfpu[8] = Fmvf
+sfpu[9] = feq
+sfpu[10] = flt
+sfpu[11] = fle
+sfpu[12] = Fmadd
+sfpu[13] = Fmsubb
+sfpu[14] = FCVT.W.P
+sfpu[15] = FCVT.P.W
+sfpu[16] = Fnmsubb
+sfpu[17] = Fnmadd
+sfpu[18] = fsgnj
+sfpu[19] = fsgnjn
+sfpu[20] = fsgnjx
+sfpu[21] = fclass
+sfpu[22] = unsign
+sfpu[23] = sign
+*/
+
+
+
+input [std:0] INPUT_VALIDATION_input_ieee_A;
+input [std:0] INPUT_VALIDATION_input_ieee_B;
+input [std:0] INPUT_VALIDATION_input_ieee_C;
+input [23:0] INPUT_VALIDATION_input_opcode;
+input rst_l;
+
+//respective generted exception output
+output [std:0] INPUT_VALIDATION_Output_temp_storage;
+
+//Flags
+
+//exception flag to handle the termination of further execution in case any exceptional input occur
+output INPUT_VALIDATION_Output_exception_flag_Fadd,INPUT_VALIDATION_Output_exception_flag_Fsub,INPUT_VALIDATION_Output_exception_flag_Fmul,INPUT_VALIDATION_Output_exception_flag_Fdiv,INPUT_VALIDATION_Output_exception_flag_Fsqrt,INPUT_VALIDATION_Output_exception_flag_Fcomp,INPUT_VALIDATION_Output_exception_flag_Fmadd,INPUT_VALIDATION_Output_exception_flag_Fmsub;
+
+// Invalid flag
+output INPUT_VALIDATION_Output_invalid_flag;
+
+// Divided By zero flag
+output INPUT_VALIDATION_Output_Flag_DZ;
+
+//interupt pin
+output interupt_Pin;
+
+//interim register for holding few bolean conditions
+wire INPUT_VALIDATION_Bit_A_infinity;
+wire INPUT_VALIDATION_Bit_B_infinity;
+wire INPUT_VALIDATION_Bit_C_infinity;
+wire INPUT_VALIDATION_Bit_A_SNAN;
+wire INPUT_VALIDATION_Bit_B_SNAN;
+wire INPUT_VALIDATION_Bit_C_SNAN;
+wire INPUT_VALIDATION_Bit_A_QNAN;
+wire INPUT_VALIDATION_Bit_B_QNAN;
+wire INPUT_VALIDATION_Bit_C_QNAN;
+wire INPUT_VALIDATION_Bit_NAN;
+
+wire INPUT_VALIDATION_Mantissa_Zero_A;
+wire INPUT_VALIDATION_Mantissa_Zero_B;
+wire INPUT_VALIDATION_Mantissa_Zero_C;
+
+wire INPUT_VALIDATION_exp_One_A;
+wire INPUT_VALIDATION_exp_One_B;
+wire INPUT_VALIDATION_exp_One_C;
+
+wire INPUT_VALIDATION_Bit_A_zero;
+wire INPUT_VALIDATION_Bit_B_zero;
+wire INPUT_VALIDATION_Bit_C_zero;
+wire INPUT_VALIDATION_Bit_A_1;
+wire INPUT_VALIDATION_Bit_B_1;
+wire INPUT_VALIDATION_Bit_C_1;
+wire INPUT_VALIDATION_Bit_Equal;
+wire INPUT_VALIDATION_Bit_single_infinity;
+wire INPUT_VALIDATION_Bit_double_infinity;
+wire INPUT_VALIDATION_Bit_single_SNAN;
+wire INPUT_VALIDATION_Bit_single_QNAN;
+wire INPUT_VALIDATION_Bit_single_zero;
+wire INPUT_VALIDATION_Bit_double_zero;
+wire INPUT_VALIDATION_Bit_xor_sign;
+
+
+//outptu selection bits
+wire INPUT_VALIDATION_Bit_SNAN_Caught;
+wire INPUT_VALIDATION_Bit_No_Comp_A_Caught;
+wire INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught;
+wire INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught;
+wire INPUT_VALIDATION_Bit_No_Comp_B_Caught;
+wire INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught;
+wire INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught;
+wire INPUT_VALIDATION_Bit_No_Comp_C_Caught;
+wire INPUT_VALIDATION_Bit_Positive_No_Comp_C_Caught;
+wire INPUT_VALIDATION_Bit_Negative_No_Comp_C_Caught;
+wire INPUT_VALIDATION_Bit_Positive_infinity_Caught;
+wire INPUT_VALIDATION_Bit_negative_infinity_Caught;
+wire INPUT_VALIDATION_Bit_positive_zero_Caught;
+wire INPUT_VALIDATION_Bit_negative_zero_Caught;
+wire INPUT_VALIDATION_Bit_Negative_One_Caught;
+wire INPUT_VALIDATION_Bit_Positive_One_Caught;
+
+//Fadd wires
+wire INPUT_VALIDATION_Bit_SNAN_Caught_Fadd;
+wire INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fadd;
+wire INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fadd;
+wire INPUT_VALIDATION_Bit_positive_infinity_Caught_Fadd;
+wire INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fadd;
+wire INPUT_VALIDATION_Bit_positive_zero_Caught_Fadd;
+wire INPUT_VALIDATION_Bit_negitive_zero_Caught_Fadd;
+
+//Fsubb wires
+wire INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb;
+wire INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fsubb;
+wire INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fsubb;
+wire INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fsubb;
+wire INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fsubb;
+wire INPUT_VALIDATION_Bit_positive_zero_Caught_Fsubb;
+wire INPUT_VALIDATION_Bit_negitive_zero_Caught_Fsubb;
+
+//Fmul wires
+wire INPUT_VALIDATION_Bit_SNAN_Caught_Fmul;
+wire INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmul;
+wire INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmul;
+wire INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmul;
+wire INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmul;
+wire INPUT_VALIDATION_Bit_negative_zero_Caught_Fmul;
+wire INPUT_VALIDATION_Bit_positive_zero_Caught_Fmul;
+
+//Fdiv wires
+wire INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv;
+wire INPUT_VALIDATION_Bit_positive_zero_Caught_Fdiv;
+wire INPUT_VALIDATION_Bit_negative_zero_Caught_Fdiv;
+wire INPUT_VALIDATION_Bit_positive_infinity_Caught_Fdiv;
+wire INPUT_VALIDATION_Bit_negative_infinity_Caught_Fdiv;
+wire INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fdiv;
+wire INPUT_VALIDATION_Bit_Positive_One_Caught_Fdiv;
+wire INPUT_VALIDATION_Bit_Negative_One_Caught_Fdiv;
+
+//Fsqrt Wires
+wire INPUT_VALIDATION_Bit_SNAN_Caught_Fsqrt;
+wire INPUT_VALIDATION_Bit_zero_Caught_Fsqrt;
+wire INPUT_VALIDATION_Bit_positive_infinity_Caught_Fsqrt;
+wire INPUT_VALIDATION_Bit_Positive_One_Caught_Fsqrt;
+
+//Fmin Wires
+wire INPUT_VALIDATION_Bit_SNAN_Caught_Fmin;
+wire INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmin;
+wire INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmin;
+
+//Fmax Wires
+wire INPUT_VALIDATION_Bit_SNAN_Caught_Fmax;
+wire INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmax;
+wire INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmax;
+
+//Flt wires
+wire INPUT_VALIDATION_Bit_zero_Caught_Flt;
+
+//Fle wires
+wire INPUT_VALIDATION_Bit_zero_Caught_Fle;
+
+//Feq wires
+wire INPUT_VALIDATION_Bit_zero_Caught_Feq;
+
+//Fmadd wires
+wire INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd;
+wire INPUT_VALIDATION_Bit_Positive_Zero_Caught_Fmadd;
+wire INPUT_VALIDATION_Bit_negative_Zero_Caught_Fmadd;
+wire INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmadd;
+wire INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmadd;
+wire INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught_Fmadd;
+wire INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught_Fmadd;
+wire INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fmadd;
+wire INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fmadd;
+wire INPUT_VALIDATION_Bit_No_Comp_C_Caught_Fmadd;
+
+//Fmsubb wires
+wire INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb;
+wire INPUT_VALIDATION_Bit_Positive_Zero_Caught_Fmsubb ;
+wire INPUT_VALIDATION_Bit_Negative_Zero_Caught_Fmsubb;
+wire INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmsubb;
+wire INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmsubb;
+wire INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught_Fmsubb;
+wire INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught_Fmsubb;
+wire INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fmsubb;
+wire INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fmsubb;
+wire INPUT_VALIDATION_Bit_Positive_No_Comp_C_Caught_Fmsubb;
+wire INPUT_VALIDATION_Bit_Negative_No_Comp_C_Caught_Fmsubb;
+
+ //check for 0 mantissa
+ assign INPUT_VALIDATION_Mantissa_Zero_A = ( & ( ~INPUT_VALIDATION_input_ieee_A[man:0] ));
+ assign INPUT_VALIDATION_Mantissa_Zero_B = ( & ( ~INPUT_VALIDATION_input_ieee_B[man:0] ));
+ assign INPUT_VALIDATION_Mantissa_Zero_C = ( & ( ~INPUT_VALIDATION_input_ieee_B[man:0] ));
+
+ //check for all one exponent
+ assign INPUT_VALIDATION_exp_One_A = ( & INPUT_VALIDATION_input_ieee_A[std-1:man+1] );
+ assign INPUT_VALIDATION_exp_One_B = ( & INPUT_VALIDATION_input_ieee_B[std-1:man+1] );
+ assign INPUT_VALIDATION_exp_One_C = ( & INPUT_VALIDATION_input_ieee_C[std-1:man+1] );
+
+ //Bolean checks for XOR of sign
+ assign INPUT_VALIDATION_Bit_xor_sign = INPUT_VALIDATION_input_ieee_A[std] ^ INPUT_VALIDATION_input_ieee_B[std] ;
+
+
+ //Bolean check for checkin wather or not a spcific operand is infinity
+ assign INPUT_VALIDATION_Bit_A_infinity = ( INPUT_VALIDATION_exp_One_A & INPUT_VALIDATION_Mantissa_Zero_A );
+
+ assign INPUT_VALIDATION_Bit_B_infinity = ( INPUT_VALIDATION_exp_One_B & INPUT_VALIDATION_Mantissa_Zero_B );
+
+ assign INPUT_VALIDATION_Bit_C_infinity = ( INPUT_VALIDATION_exp_One_C & INPUT_VALIDATION_Mantissa_Zero_C );
+
+ //Boolean variables for detecting wether or not a single operand in the ijsntrustion is QNAN or not
+ assign INPUT_VALIDATION_Bit_A_QNAN = ( INPUT_VALIDATION_exp_One_A & ( INPUT_VALIDATION_input_ieee_A[man] ) );
+
+ assign INPUT_VALIDATION_Bit_B_QNAN = ( INPUT_VALIDATION_exp_One_B & ( INPUT_VALIDATION_input_ieee_B[man] ) );
+
+ assign INPUT_VALIDATION_Bit_C_QNAN = ( INPUT_VALIDATION_exp_One_C & ( INPUT_VALIDATION_input_ieee_C[man] ) );
+
+ //Bolean variables for checking weateher or not the either of incoming operands is SNAN
+ assign INPUT_VALIDATION_Bit_A_SNAN = ( INPUT_VALIDATION_exp_One_A & ( ~( INPUT_VALIDATION_input_ieee_A[man] ) & ( |INPUT_VALIDATION_input_ieee_A[man-1:0] ) ) );
+
+ assign INPUT_VALIDATION_Bit_B_SNAN = ( INPUT_VALIDATION_exp_One_B & ( ~( INPUT_VALIDATION_input_ieee_B[man] ) & ( |INPUT_VALIDATION_input_ieee_B[man-1:0] ) ) );
+
+ assign INPUT_VALIDATION_Bit_C_SNAN = ( INPUT_VALIDATION_exp_One_C & ( ~( INPUT_VALIDATION_input_ieee_C[man] ) & ( |INPUT_VALIDATION_input_ieee_C[man-1:0] ) ) );
+
+ assign INPUT_VALIDATION_Bit_NAN = INPUT_VALIDATION_Bit_A_SNAN | INPUT_VALIDATION_Bit_B_SNAN | INPUT_VALIDATION_Bit_A_QNAN | INPUT_VALIDATION_Bit_B_QNAN;
+
+ //Bolean check sfor checking weather or not a spcific operand is zero
+ assign INPUT_VALIDATION_Bit_A_zero = (&(~INPUT_VALIDATION_input_ieee_A[std-1:man+1])) & (INPUT_VALIDATION_Mantissa_Zero_A);
+ assign INPUT_VALIDATION_Bit_B_zero = (&(~INPUT_VALIDATION_input_ieee_B[std-1:man+1])) & (INPUT_VALIDATION_Mantissa_Zero_B);
+ assign INPUT_VALIDATION_Bit_C_zero = (&(~INPUT_VALIDATION_input_ieee_C[std-1:man+1])) & (INPUT_VALIDATION_Mantissa_Zero_C);
+
+ //Bolean checks for cheking watehr or not a spcific operand is 1
+ assign INPUT_VALIDATION_Bit_A_1 = ((INPUT_VALIDATION_input_ieee_A[std-1:man+1]==bias) && INPUT_VALIDATION_Mantissa_Zero_A);
+ assign INPUT_VALIDATION_Bit_B_1 = ((INPUT_VALIDATION_input_ieee_B[std-1:man+1]==bias) && INPUT_VALIDATION_Mantissa_Zero_B);
+ assign INPUT_VALIDATION_Bit_C_1 = ((INPUT_VALIDATION_input_ieee_C[std-1:man+1]==bias) && INPUT_VALIDATION_Mantissa_Zero_C);
+
+ // Check for quality of two numbers
+ assign INPUT_VALIDATION_Bit_Equal = ( INPUT_VALIDATION_input_ieee_A [std-1:0] == INPUT_VALIDATION_input_ieee_B[std-1:0] );
+
+
+ //Bolean checks for checking weather two or one or three operands are related to a specific exception (such as single infinity means one of the two opernds inputed are ininfiyt)
+
+ //check for number of infinity pernds
+ assign INPUT_VALIDATION_Bit_single_infinity = (INPUT_VALIDATION_Bit_A_infinity) || (INPUT_VALIDATION_Bit_B_infinity);
+ assign INPUT_VALIDATION_Bit_double_infinity = (INPUT_VALIDATION_Bit_A_infinity) && (INPUT_VALIDATION_Bit_B_infinity);
+
+
+
+ //check for number of zero pernds
+ assign INPUT_VALIDATION_Bit_single_zero = (INPUT_VALIDATION_Bit_A_zero) || (INPUT_VALIDATION_Bit_B_zero);
+ assign INPUT_VALIDATION_Bit_double_zero = (INPUT_VALIDATION_Bit_A_zero) && (INPUT_VALIDATION_Bit_B_zero);
+
+//Bolean check for indication of type of exceptions occured (as a function of input)
+
+// Fadd Exceptional casses
+assign INPUT_VALIDATION_Bit_SNAN_Caught_Fadd = ( INPUT_VALIDATION_input_opcode[0] & ( INPUT_VALIDATION_Bit_NAN | ( INPUT_VALIDATION_Bit_double_infinity & INPUT_VALIDATION_Bit_xor_sign ) ) ) ;
+
+assign INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fadd = ( INPUT_VALIDATION_input_opcode[0] & ( (INPUT_VALIDATION_Bit_B_zero & ~INPUT_VALIDATION_Bit_double_zero) | (INPUT_VALIDATION_Bit_A_infinity & (~INPUT_VALIDATION_Bit_double_infinity) ) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fadd);
+
+assign INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fadd = ( INPUT_VALIDATION_input_opcode[0] & ( (INPUT_VALIDATION_Bit_A_zero & ~INPUT_VALIDATION_Bit_double_zero) | (INPUT_VALIDATION_Bit_B_infinity & (~INPUT_VALIDATION_Bit_double_infinity) ) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fadd);
+
+assign INPUT_VALIDATION_Bit_positive_infinity_Caught_Fadd = ( INPUT_VALIDATION_input_opcode[0] & ( INPUT_VALIDATION_Bit_double_infinity & (~INPUT_VALIDATION_input_ieee_A[std] & ~INPUT_VALIDATION_input_ieee_B[std]) ) ) ;
+
+assign INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fadd = ( INPUT_VALIDATION_input_opcode[0] & ( INPUT_VALIDATION_Bit_double_infinity & (INPUT_VALIDATION_input_ieee_A[std] & INPUT_VALIDATION_input_ieee_B[std]) ) );
+
+assign INPUT_VALIDATION_Bit_positive_zero_Caught_Fadd = (INPUT_VALIDATION_input_opcode[0] & (INPUT_VALIDATION_Bit_double_zero & ( (~INPUT_VALIDATION_input_ieee_A[std]) & (~INPUT_VALIDATION_input_ieee_B[std]) ) ) ) ;
+
+assign INPUT_VALIDATION_Bit_negitive_zero_Caught_Fadd = (INPUT_VALIDATION_input_opcode[0] & (INPUT_VALIDATION_Bit_double_zero & ( INPUT_VALIDATION_Bit_xor_sign ) ) ) ;
+
+// Exception flag of fadd made high here
+assign INPUT_VALIDATION_Output_exception_flag_Fadd = INPUT_VALIDATION_Bit_SNAN_Caught_Fadd | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fadd | INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fadd | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fadd | INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fadd | INPUT_VALIDATION_Bit_positive_zero_Caught_Fadd | INPUT_VALIDATION_Bit_negitive_zero_Caught_Fadd;
+
+//Fsub exceptionl cases
+assign INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb = ( INPUT_VALIDATION_input_opcode[1] & (INPUT_VALIDATION_Bit_NAN | ( INPUT_VALIDATION_Bit_double_infinity & (~INPUT_VALIDATION_Bit_xor_sign) ) ) ) ;
+
+assign INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fsubb = ( INPUT_VALIDATION_input_opcode[1] & ( (INPUT_VALIDATION_Bit_B_zero & (~INPUT_VALIDATION_Bit_double_zero) ) | (INPUT_VALIDATION_Bit_A_infinity & (~INPUT_VALIDATION_Bit_double_infinity) ) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb);
+
+assign INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fsubb = ( (INPUT_VALIDATION_input_opcode[1] & INPUT_VALIDATION_input_ieee_B[std] ) & ( (INPUT_VALIDATION_Bit_A_zero & (~INPUT_VALIDATION_Bit_double_zero) ) | (INPUT_VALIDATION_Bit_B_infinity & (~INPUT_VALIDATION_Bit_double_infinity) ) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb); // sign of this operand in th resultant will be checked based on the sign of this operand: 0 -(-B) = B hnce thisis dealed seperately in output selection logic
+
+assign INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fsubb = ( (INPUT_VALIDATION_input_opcode[1] & (~INPUT_VALIDATION_input_ieee_B[std]) ) & ( (INPUT_VALIDATION_Bit_A_zero & (~INPUT_VALIDATION_Bit_double_zero) ) | (INPUT_VALIDATION_Bit_B_infinity & (~INPUT_VALIDATION_Bit_double_infinity) ) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb);
+
+assign INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fsubb = ( INPUT_VALIDATION_input_opcode[1] & ( INPUT_VALIDATION_Bit_double_infinity & (INPUT_VALIDATION_Bit_xor_sign) ) ); //the resulting infinicty in this case would be a negative infinity
+
+assign INPUT_VALIDATION_Bit_positive_zero_Caught_Fsubb = (INPUT_VALIDATION_input_opcode[1] & ( (INPUT_VALIDATION_Bit_Equal) | ( ( (~INPUT_VALIDATION_input_ieee_A[std]) | (INPUT_VALIDATION_input_ieee_A[std] & (INPUT_VALIDATION_input_ieee_B[std]) ) ) & INPUT_VALIDATION_Bit_double_zero) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb);
+
+assign INPUT_VALIDATION_Bit_negitive_zero_Caught_Fsubb = (INPUT_VALIDATION_input_opcode[1] & (INPUT_VALIDATION_Bit_double_zero & (INPUT_VALIDATION_input_ieee_A[std] & (~INPUT_VALIDATION_input_ieee_B[std])) ) );
+
+// Exeption Flag for Fsub
+assign INPUT_VALIDATION_Output_exception_flag_Fsub = INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fsubb | INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fsubb | INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fsubb | INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fsubb | INPUT_VALIDATION_Bit_positive_zero_Caught_Fsubb | INPUT_VALIDATION_Bit_negitive_zero_Caught_Fsubb;
+
+//Fmul exceptional casses
+assign INPUT_VALIDATION_Bit_SNAN_Caught_Fmul = ( INPUT_VALIDATION_input_opcode[2] & ( INPUT_VALIDATION_Bit_NAN | (INPUT_VALIDATION_Bit_single_zero & INPUT_VALIDATION_Bit_single_infinity) ) );
+
+assign INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmul = ( INPUT_VALIDATION_input_opcode[2] & ( INPUT_VALIDATION_Bit_B_1 ) ) & (~INPUT_VALIDATION_Bit_A_zero) & (~INPUT_VALIDATION_Bit_A_infinity) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmul) ;
+
+assign INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmul = ( INPUT_VALIDATION_input_opcode[2] & ( INPUT_VALIDATION_Bit_A_1 ) ) & (~INPUT_VALIDATION_Bit_B_zero) & (~INPUT_VALIDATION_Bit_B_infinity) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmul) & (~INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmul) ;
+
+assign INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmul = ( INPUT_VALIDATION_input_opcode[2] & ( INPUT_VALIDATION_Bit_single_infinity & (~INPUT_VALIDATION_Bit_xor_sign) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmul);
+
+assign INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmul = ( INPUT_VALIDATION_input_opcode[2] & ( INPUT_VALIDATION_Bit_single_infinity & (INPUT_VALIDATION_Bit_xor_sign) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmul);
+
+assign INPUT_VALIDATION_Bit_positive_zero_Caught_Fmul = ( INPUT_VALIDATION_input_opcode[2] & (INPUT_VALIDATION_Bit_single_zero & (~INPUT_VALIDATION_Bit_xor_sign) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmul);
+
+assign INPUT_VALIDATION_Bit_negative_zero_Caught_Fmul = ( INPUT_VALIDATION_input_opcode[2] & ( (INPUT_VALIDATION_Bit_single_zero & (INPUT_VALIDATION_Bit_xor_sign) ) )) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmul);
+
+// exception Flag for Fmul
+assign INPUT_VALIDATION_Output_exception_flag_Fmul = INPUT_VALIDATION_Bit_SNAN_Caught_Fmul | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmul | INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmul | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmul | INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmul | INPUT_VALIDATION_Bit_positive_zero_Caught_Fmul | INPUT_VALIDATION_Bit_negative_zero_Caught_Fmul ;
+
+
+//Fdiv cases
+assign INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv = (INPUT_VALIDATION_input_opcode[3] & ( ( INPUT_VALIDATION_Bit_NAN ) | ( INPUT_VALIDATION_Bit_double_infinity ) | (INPUT_VALIDATION_Bit_double_zero ) ) );
+
+assign INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fdiv = ( INPUT_VALIDATION_input_opcode[3] & ( INPUT_VALIDATION_Bit_B_1 ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv)) & (~INPUT_VALIDATION_Bit_Positive_One_Caught_Fdiv) & (~INPUT_VALIDATION_Bit_Negative_One_Caught_Fdiv);
+
+assign INPUT_VALIDATION_Bit_Positive_One_Caught_Fdiv = ( INPUT_VALIDATION_input_opcode[3] & ( INPUT_VALIDATION_Bit_Equal ) & (~INPUT_VALIDATION_Bit_xor_sign) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv) ;
+
+assign INPUT_VALIDATION_Bit_Negative_One_Caught_Fdiv = ( INPUT_VALIDATION_input_opcode[3] & ( INPUT_VALIDATION_Bit_Equal ) & (INPUT_VALIDATION_Bit_xor_sign) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv) ;
+
+assign INPUT_VALIDATION_Bit_positive_infinity_Caught_Fdiv = ( INPUT_VALIDATION_input_opcode[3] & ( ( INPUT_VALIDATION_Bit_B_zero & ( ~INPUT_VALIDATION_Bit_double_zero ) & (~INPUT_VALIDATION_input_ieee_B[std]) ) | ( INPUT_VALIDATION_Bit_A_infinity & (~INPUT_VALIDATION_Bit_double_infinity) & (~INPUT_VALIDATION_input_ieee_A[std]) ) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv);
+
+assign INPUT_VALIDATION_Bit_negative_infinity_Caught_Fdiv = ( INPUT_VALIDATION_input_opcode[3] & ( ( INPUT_VALIDATION_Bit_B_zero & ( ~INPUT_VALIDATION_Bit_double_zero ) & (INPUT_VALIDATION_input_ieee_B[std]) ) | ( INPUT_VALIDATION_Bit_A_infinity & (~INPUT_VALIDATION_Bit_double_infinity) & (INPUT_VALIDATION_input_ieee_A[std]) ) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv);
+
+assign INPUT_VALIDATION_Bit_positive_zero_Caught_Fdiv = (INPUT_VALIDATION_input_opcode[3] & ( ( INPUT_VALIDATION_Bit_A_zero & (~INPUT_VALIDATION_Bit_double_zero) & (~INPUT_VALIDATION_input_ieee_A[std]) ) | ( INPUT_VALIDATION_Bit_B_infinity & (~INPUT_VALIDATION_Bit_double_infinity) & (~INPUT_VALIDATION_input_ieee_B[std]) ) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv);
+
+assign INPUT_VALIDATION_Bit_negative_zero_Caught_Fdiv = (INPUT_VALIDATION_input_opcode[3] & ( ( INPUT_VALIDATION_Bit_A_zero & (~INPUT_VALIDATION_Bit_double_zero) & (INPUT_VALIDATION_input_ieee_A[std]) ) | ( INPUT_VALIDATION_Bit_B_infinity & (~INPUT_VALIDATION_Bit_double_infinity) & (INPUT_VALIDATION_input_ieee_B[std]) ) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv);
+
+// exception Flag for Fdiv
+assign INPUT_VALIDATION_Output_exception_flag_Fdiv = INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fdiv | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fdiv | INPUT_VALIDATION_Bit_negative_infinity_Caught_Fdiv | INPUT_VALIDATION_Bit_positive_zero_Caught_Fdiv | INPUT_VALIDATION_Bit_negative_zero_Caught_Fdiv | INPUT_VALIDATION_Bit_Positive_One_Caught_Fdiv | INPUT_VALIDATION_Bit_Negative_One_Caught_Fdiv;
+
+//Fsqrt Cases
+assign INPUT_VALIDATION_Bit_SNAN_Caught_Fsqrt = ( INPUT_VALIDATION_input_opcode[4] & ( INPUT_VALIDATION_Bit_A_SNAN | INPUT_VALIDATION_Bit_A_QNAN | INPUT_VALIDATION_input_ieee_A[std] ) ) ;
+
+assign INPUT_VALIDATION_Bit_zero_Caught_Fsqrt = ( INPUT_VALIDATION_input_opcode[4] & ( INPUT_VALIDATION_Bit_A_zero & (~INPUT_VALIDATION_input_ieee_A[std]) ) ) ;
+
+assign INPUT_VALIDATION_Bit_Positive_One_Caught_Fsqrt = (INPUT_VALIDATION_input_opcode[4] & ( ( INPUT_VALIDATION_Bit_A_1) & (~INPUT_VALIDATION_input_ieee_A[std]) ) );
+
+assign INPUT_VALIDATION_Bit_positive_infinity_Caught_Fsqrt = ( INPUT_VALIDATION_input_opcode[4] & ( (INPUT_VALIDATION_Bit_A_infinity) & (~INPUT_VALIDATION_input_ieee_A[std]) ) );
+
+// exception flag for square root
+assign INPUT_VALIDATION_Output_exception_flag_Fsqrt = INPUT_VALIDATION_Bit_SNAN_Caught_Fsqrt | INPUT_VALIDATION_Bit_zero_Caught_Fsqrt | INPUT_VALIDATION_Bit_Positive_One_Caught_Fsqrt | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fsqrt ;
+
+//Fmin cases
+assign INPUT_VALIDATION_Bit_SNAN_Caught_Fmin = ( INPUT_VALIDATION_input_opcode[5] & ( INPUT_VALIDATION_Bit_NAN ) ) ;
+
+assign INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmin = ( INPUT_VALIDATION_input_opcode[5] & ( INPUT_VALIDATION_Bit_B_QNAN) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmin);
+
+assign INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmin = ( INPUT_VALIDATION_input_opcode[5] & ( INPUT_VALIDATION_Bit_A_QNAN) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmin);
+
+//Fmax cases
+assign INPUT_VALIDATION_Bit_SNAN_Caught_Fmax = ( INPUT_VALIDATION_input_opcode[6] & ( INPUT_VALIDATION_Bit_NAN ) ) ;
+
+assign INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmax = ( INPUT_VALIDATION_input_opcode[6] & ( INPUT_VALIDATION_Bit_B_QNAN) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmax);
+
+assign INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmax = ( INPUT_VALIDATION_input_opcode[6] & ( INPUT_VALIDATION_Bit_A_QNAN) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmax);
+
+//Feq Cases
+ assign INPUT_VALIDATION_Bit_zero_Caught_Feq = ( INPUT_VALIDATION_input_opcode[9] & ( INPUT_VALIDATION_Bit_NAN ) ) ;
+
+//Flt Cases
+ assign INPUT_VALIDATION_Bit_zero_Caught_Flt = ( INPUT_VALIDATION_input_opcode[10] & ( INPUT_VALIDATION_Bit_NAN ) ) ;
+
+//Fle Cases
+ assign INPUT_VALIDATION_Bit_zero_Caught_Fle = ( INPUT_VALIDATION_input_opcode[11] & ( INPUT_VALIDATION_Bit_NAN ) ) ;
+
+// exception flag for comparision block
+assign INPUT_VALIDATION_Output_exception_flag_Fcomp = INPUT_VALIDATION_Bit_SNAN_Caught_Fmin | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmin | INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmin | INPUT_VALIDATION_Bit_SNAN_Caught_Fmax | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmax | INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmax | INPUT_VALIDATION_Bit_zero_Caught_Feq | INPUT_VALIDATION_Bit_zero_Caught_Flt | INPUT_VALIDATION_Bit_zero_Caught_Fle;
+
+//FMADD Casses
+assign INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd = ( INPUT_VALIDATION_input_opcode[12] & ( (INPUT_VALIDATION_Bit_single_infinity & INPUT_VALIDATION_Bit_single_zero) | ( INPUT_VALIDATION_Bit_NAN | INPUT_VALIDATION_Bit_C_SNAN | INPUT_VALIDATION_Bit_C_QNAN ) | ( ( INPUT_VALIDATION_Bit_single_infinity & INPUT_VALIDATION_Bit_C_infinity ) & ( ( INPUT_VALIDATION_Bit_xor_sign & (~INPUT_VALIDATION_input_ieee_C[std]) ) | ( (~INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_input_ieee_C[std] ) ) ) ) ) ;
+assign INPUT_VALIDATION_Bit_Positive_Zero_Caught_Fmadd = ( INPUT_VALIDATION_input_opcode[12] & ( (INPUT_VALIDATION_Bit_single_zero & INPUT_VALIDATION_Bit_C_zero) & ( (~INPUT_VALIDATION_input_ieee_C[std]) | ( (~INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_input_ieee_C[std] ) ) )) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd);
+assign INPUT_VALIDATION_Bit_negative_Zero_Caught_Fmadd =( INPUT_VALIDATION_input_opcode[12] & ( INPUT_VALIDATION_Bit_single_zero & (INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_Bit_C_zero & (INPUT_VALIDATION_input_ieee_C[std]) )) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd);
+assign INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmadd = ( INPUT_VALIDATION_input_opcode[12] & (INPUT_VALIDATION_Bit_single_infinity & (~INPUT_VALIDATION_Bit_xor_sign))) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd);
+assign INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmadd = ( INPUT_VALIDATION_input_opcode[12] & (INPUT_VALIDATION_Bit_single_infinity & (INPUT_VALIDATION_Bit_xor_sign))) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd);
+assign INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught_Fmadd = ( INPUT_VALIDATION_input_opcode[12] & ( INPUT_VALIDATION_Bit_B_1 & (~INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_Bit_C_zero & (~INPUT_VALIDATION_Bit_A_infinity) & (~INPUT_VALIDATION_Bit_A_zero) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd);
+assign INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught_Fmadd = (INPUT_VALIDATION_input_opcode[12] & ( INPUT_VALIDATION_Bit_B_1 & (INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_Bit_C_zero & (~INPUT_VALIDATION_Bit_A_infinity) & (~INPUT_VALIDATION_Bit_A_zero) )) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd) ;
+assign INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fmadd = (INPUT_VALIDATION_input_opcode[12] & ( INPUT_VALIDATION_Bit_A_1 & (~INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_Bit_C_zero & (~INPUT_VALIDATION_Bit_B_infinity) & (~INPUT_VALIDATION_Bit_B_zero) )) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd);
+assign INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fmadd = (INPUT_VALIDATION_input_opcode[12] & ( INPUT_VALIDATION_Bit_A_1 & (INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_Bit_C_zero & (~INPUT_VALIDATION_Bit_B_infinity) & (~INPUT_VALIDATION_Bit_B_zero) )) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd);
+assign INPUT_VALIDATION_Bit_No_Comp_C_Caught_Fmadd = ( INPUT_VALIDATION_input_opcode[12] & ( INPUT_VALIDATION_Bit_double_zero & (~INPUT_VALIDATION_Bit_C_zero) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd);
+
+// exception flag for fmadd
+assign INPUT_VALIDATION_Output_exception_flag_Fmadd = INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd | INPUT_VALIDATION_Bit_Positive_Zero_Caught_Fmadd | INPUT_VALIDATION_Bit_negative_Zero_Caught_Fmadd | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmadd | INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmadd | INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught_Fmadd | INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught_Fmadd | INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fmadd | INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fmadd | INPUT_VALIDATION_Bit_No_Comp_C_Caught_Fmadd;
+
+//Fmsub Casses
+assign INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb = (INPUT_VALIDATION_input_opcode[13] & ( (INPUT_VALIDATION_Bit_single_infinity & INPUT_VALIDATION_Bit_single_zero) | ( INPUT_VALIDATION_Bit_NAN | INPUT_VALIDATION_Bit_C_SNAN | INPUT_VALIDATION_Bit_C_QNAN) | ( ( INPUT_VALIDATION_Bit_single_infinity & INPUT_VALIDATION_Bit_C_infinity ) & ( ( (~INPUT_VALIDATION_Bit_xor_sign) & (~INPUT_VALIDATION_input_ieee_C[std]) ) | ( INPUT_VALIDATION_Bit_xor_sign & INPUT_VALIDATION_input_ieee_C[std] ) ) ) ) );
+assign INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmsubb = ( INPUT_VALIDATION_input_opcode[13] & (INPUT_VALIDATION_Bit_single_infinity & (~INPUT_VALIDATION_Bit_xor_sign))) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb);
+assign INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmsubb = ( INPUT_VALIDATION_input_opcode[13] & (INPUT_VALIDATION_Bit_single_infinity & (INPUT_VALIDATION_Bit_xor_sign))) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb);
+assign INPUT_VALIDATION_Bit_Positive_Zero_Caught_Fmsubb = ( INPUT_VALIDATION_input_opcode[13] & ( ( (INPUT_VALIDATION_Bit_single_zero & INPUT_VALIDATION_Bit_C_zero) & ( (~INPUT_VALIDATION_Bit_xor_sign) | ( INPUT_VALIDATION_Bit_xor_sign & INPUT_VALIDATION_input_ieee_C[std]) )) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb) ;
+assign INPUT_VALIDATION_Bit_Negative_Zero_Caught_Fmsubb = ( INPUT_VALIDATION_input_opcode[13] & ( INPUT_VALIDATION_Bit_single_zero & INPUT_VALIDATION_Bit_xor_sign & INPUT_VALIDATION_Bit_C_zero & (~INPUT_VALIDATION_input_ieee_C[std]) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb) ;
+assign INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught_Fmsubb = ( INPUT_VALIDATION_input_opcode[13] & ( INPUT_VALIDATION_Bit_B_1 & (~INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_Bit_C_zero & (~INPUT_VALIDATION_Bit_A_infinity) & (~INPUT_VALIDATION_Bit_A_zero) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb);
+assign INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught_Fmsubb = (INPUT_VALIDATION_input_opcode[13] & ( INPUT_VALIDATION_Bit_B_1 & (INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_Bit_C_zero & (~INPUT_VALIDATION_Bit_A_infinity) & (~INPUT_VALIDATION_Bit_A_zero) )) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb) ;
+assign INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fmsubb = (INPUT_VALIDATION_input_opcode[13] & ( INPUT_VALIDATION_Bit_A_1 & (~INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_Bit_C_zero & (~INPUT_VALIDATION_Bit_B_infinity) & (~INPUT_VALIDATION_Bit_B_zero) )) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb);
+assign INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fmsubb = (INPUT_VALIDATION_input_opcode[13] & ( INPUT_VALIDATION_Bit_A_1 & (INPUT_VALIDATION_Bit_xor_sign) & INPUT_VALIDATION_Bit_C_zero & (~INPUT_VALIDATION_Bit_B_infinity) & (~INPUT_VALIDATION_Bit_B_zero) )) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb);
+assign INPUT_VALIDATION_Bit_Positive_No_Comp_C_Caught_Fmsubb = (INPUT_VALIDATION_input_opcode[13] & (INPUT_VALIDATION_Bit_double_zero & INPUT_VALIDATION_input_ieee_C[std] & (~INPUT_VALIDATION_Bit_C_zero) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb) ;
+assign INPUT_VALIDATION_Bit_Negative_No_Comp_C_Caught_Fmsubb = (INPUT_VALIDATION_input_opcode[13] & (INPUT_VALIDATION_Bit_double_zero & (~INPUT_VALIDATION_input_ieee_C[std]) & (~INPUT_VALIDATION_Bit_C_zero) ) ) & (~INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb) ;
+
+// exception flag for fmsubb
+assign INPUT_VALIDATION_Output_exception_flag_Fmsub = INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb |INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmsubb |INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmsubb |INPUT_VALIDATION_Bit_Positive_Zero_Caught_Fmsubb |INPUT_VALIDATION_Bit_Negative_Zero_Caught_Fmsubb |INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught_Fmsubb |INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught_Fmsubb | INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fmsubb | INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fmsubb | INPUT_VALIDATION_Bit_Positive_No_Comp_C_Caught_Fmsubb | INPUT_VALIDATION_Bit_Negative_No_Comp_C_Caught_Fmsubb;
+//################################################ OUTPUT slections ##########################################
+//output selection bits
+assign INPUT_VALIDATION_Bit_SNAN_Caught = INPUT_VALIDATION_Bit_SNAN_Caught_Fadd | INPUT_VALIDATION_Bit_SNAN_Caught_Fsubb | INPUT_VALIDATION_Bit_SNAN_Caught_Fmul | INPUT_VALIDATION_Bit_SNAN_Caught_Fdiv | INPUT_VALIDATION_Bit_SNAN_Caught_Fsqrt | INPUT_VALIDATION_Bit_SNAN_Caught_Fmin | INPUT_VALIDATION_Bit_SNAN_Caught_Fmax | INPUT_VALIDATION_Bit_SNAN_Caught_Fmadd | INPUT_VALIDATION_Bit_SNAN_Caught_Fmsubb;
+
+assign INPUT_VALIDATION_Bit_No_Comp_A_Caught = INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fadd | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fsubb | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmul | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fdiv | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmin | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmax ;
+
+assign INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught = INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught_Fmadd | INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught_Fmsubb ;
+
+assign INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught = INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught_Fmadd | INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught_Fmsubb ;
+
+assign INPUT_VALIDATION_Bit_No_Comp_B_Caught = INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fadd | INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmul | INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmin | INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmax ;
+
+assign INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught = INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fmadd | INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fmsubb | INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught_Fsubb ;
+
+assign INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught = INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fmadd | INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fmsubb | INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught_Fsubb ;
+
+assign INPUT_VALIDATION_Bit_No_Comp_C_Caught = INPUT_VALIDATION_Bit_No_Comp_C_Caught_Fmadd ;
+
+assign INPUT_VALIDATION_Bit_Negative_No_Comp_C_Caught = INPUT_VALIDATION_Bit_Negative_No_Comp_C_Caught_Fmsubb;
+
+assign INPUT_VALIDATION_Bit_Positive_No_Comp_C_Caught = INPUT_VALIDATION_Bit_Positive_No_Comp_C_Caught_Fmsubb;
+
+assign INPUT_VALIDATION_Bit_Positive_infinity_Caught = INPUT_VALIDATION_Bit_positive_infinity_Caught_Fadd | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmul | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fdiv | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fsqrt | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmadd | INPUT_VALIDATION_Bit_positive_infinity_Caught_Fmsubb;
+
+assign INPUT_VALIDATION_Bit_negative_infinity_Caught = INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fsubb | INPUT_VALIDATION_Bit_negitive_infinity_Caught_Fadd | INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmul | INPUT_VALIDATION_Bit_negative_infinity_Caught_Fdiv | INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmadd | INPUT_VALIDATION_Bit_negative_infinity_Caught_Fmsubb;
+
+assign INPUT_VALIDATION_Bit_positive_zero_Caught = INPUT_VALIDATION_Bit_positive_zero_Caught_Fadd | INPUT_VALIDATION_Bit_positive_zero_Caught_Fsubb | INPUT_VALIDATION_Bit_positive_zero_Caught_Fmul | INPUT_VALIDATION_Bit_positive_zero_Caught_Fdiv | INPUT_VALIDATION_Bit_zero_Caught_Fsqrt | INPUT_VALIDATION_Bit_zero_Caught_Feq | INPUT_VALIDATION_Bit_zero_Caught_Flt | INPUT_VALIDATION_Bit_zero_Caught_Fle | INPUT_VALIDATION_Bit_Positive_Zero_Caught_Fmadd | INPUT_VALIDATION_Bit_Positive_Zero_Caught_Fmsubb ;
+
+assign INPUT_VALIDATION_Bit_negative_zero_Caught = INPUT_VALIDATION_Bit_negitive_zero_Caught_Fadd | INPUT_VALIDATION_Bit_negitive_zero_Caught_Fsubb | INPUT_VALIDATION_Bit_negative_zero_Caught_Fmul | INPUT_VALIDATION_Bit_negative_zero_Caught_Fdiv | INPUT_VALIDATION_Bit_negative_Zero_Caught_Fmadd | INPUT_VALIDATION_Bit_Negative_Zero_Caught_Fmsubb ;
+
+assign INPUT_VALIDATION_Bit_Positive_One_Caught = INPUT_VALIDATION_Bit_Positive_One_Caught_Fdiv | INPUT_VALIDATION_Bit_Positive_One_Caught_Fsqrt;
+
+assign INPUT_VALIDATION_Bit_Negative_One_Caught = INPUT_VALIDATION_Bit_Negative_One_Caught_Fdiv;
+
+
+//Exceptional Flag logic
+
+assign INPUT_VALIDATION_Output_invalid_flag = (rst_l) ? (INPUT_VALIDATION_Bit_SNAN_Caught | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmin | INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmin | INPUT_VALIDATION_Bit_No_Comp_A_Caught_Fmax | INPUT_VALIDATION_Bit_No_Comp_B_Caught_Fmax | ( (INPUT_VALIDATION_Bit_zero_Caught_Feq) & (INPUT_VALIDATION_Bit_A_SNAN | INPUT_VALIDATION_Bit_B_SNAN) ) | ( (INPUT_VALIDATION_input_opcode[10] | INPUT_VALIDATION_input_opcode[11]) & (INPUT_VALIDATION_Bit_A_SNAN | INPUT_VALIDATION_Bit_B_SNAN | INPUT_VALIDATION_Bit_A_QNAN | INPUT_VALIDATION_Bit_B_QNAN) ) ) : 1'b0 ;
+
+assign INPUT_VALIDATION_Output_Flag_DZ = (rst_l) ? INPUT_VALIDATION_Bit_positive_infinity_Caught_Fdiv : 1'b0;
+
+// Mux for sleection of coresponding exceptional output and FLags (P.S: Refer to coments against each bolen check)
+assign INPUT_VALIDATION_Output_temp_storage = (rst_l) ? (INPUT_VALIDATION_Bit_SNAN_Caught ? 32'h7fa00000 : INPUT_VALIDATION_Bit_No_Comp_A_Caught ? INPUT_VALIDATION_input_ieee_A : INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught ? {1'b0,INPUT_VALIDATION_input_ieee_A[std-1:0]} : INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught ? {1'b1,INPUT_VALIDATION_input_ieee_A[std-1:0]} : INPUT_VALIDATION_Bit_No_Comp_B_Caught ? INPUT_VALIDATION_input_ieee_B: INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught ? {1'b0,INPUT_VALIDATION_input_ieee_B[std-1:0]} : INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught ? {1'b1,INPUT_VALIDATION_input_ieee_B[std-1:0]}: INPUT_VALIDATION_Bit_No_Comp_C_Caught ? INPUT_VALIDATION_input_ieee_C : INPUT_VALIDATION_Bit_Positive_No_Comp_C_Caught ? {1'b0,INPUT_VALIDATION_input_ieee_C[std-1:0]} : INPUT_VALIDATION_Bit_Negative_No_Comp_C_Caught ? {1'b1,INPUT_VALIDATION_input_ieee_C[std-1:0]} : INPUT_VALIDATION_Bit_negative_infinity_Caught ? 32'hff800000 : INPUT_VALIDATION_Bit_Positive_infinity_Caught ? 32'h7f800000 : INPUT_VALIDATION_Bit_positive_zero_Caught ? 32'h00000000 : INPUT_VALIDATION_Bit_negative_zero_Caught ? 32'h80000000 : INPUT_VALIDATION_Bit_Positive_One_Caught ? 32'h3f800000 : INPUT_VALIDATION_Bit_Negative_One_Caught ? 32'hbf800000 : 32'h00000000) : 32'h00000000 ;
+
+//interupt pin assignment, this will be High if at least one input is either SNAN or QNAN
+assign interupt_Pin = (rst_l) ? INPUT_VALIDATION_Bit_SNAN_Caught : 1'b0 ;
+
+endmodule
diff --git a/verilog/rtl/FPU/FPU_Top_Single_Cycle.v b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
new file mode 100644
index 0000000..1b54a37
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
@@ -0,0 +1,343 @@
+//Created by : Ali Raza Zaidi
+// This is the top most leevel module of FPU
+//This is designed as per the latest architechtural updates, dissucssed with MERL's RTL team heads
+
+/*`include "F_F_T_I.v"
+`include "F_I_T_F.v"
+`include "F_M.v"
+`include "F_Comp.v"
+`include "F_S.v"
+`include "F_Cl.v"
+`include "F_IV.v"
+`include "FMA_S_Top_Single_Cycle.v"
+`include "LZD_comb.v"
+`include "LZD_mux.v"*/
+
+module FPU_Top (Operand_A,Operand_B,Operand_C, clk,rst_l, frm, sfpu_op,vfpu_op,fpu_sel,FPU_resultant, S_Flags, Exception_flag, interupt_Pin,FPU_Result_rd,Operand_Int);
+
+parameter std= 15;
+parameter man = 9;
+parameter exp = 4;
+parameter Bias = 15 /*8'b01111111*/;
+parameter lzd = 3;
+
+
+//inputs
+input [std:0] Operand_A,Operand_B,Operand_C;
+input clk,rst_l;
+input [2:0] frm;
+input [23:0] sfpu_op;
+input [2:0] fpu_sel;
+input [27:0] vfpu_op;
+input [31:0] Operand_Int;
+
+//output
+output [std:0] FPU_resultant;
+output [4:0] S_Flags;
+output Exception_flag;
+output interupt_Pin;
+output [31:0]FPU_Result_rd;
+
+//interim register
+reg [std:0] FPU_resultant_reg;
+reg[31:0] FPU_Result_rd_reg;
+reg [4:0] S_Flags_reg;
+
+//assigment of interim register on outptu ports
+assign FPU_resultant = (rst_l) ? FPU_resultant_reg:32'h00000000;
+assign S_Flags = (rst_l) ? S_Flags_reg:5'b00000 ;
+assign FPU_Result_rd = (rst_l) ? FPU_Result_rd_reg : 32'h00000000;
+
+
+/*opcode ctivation signals
+
+sfpu[0] = Fadd
+sfpu[1] = Fsubb
+sfpu[2] = Fmul
+sfpu[3] = Fdiv
+sfpu[4] = Fsqrt
+sfpu[5] = Fmin
+sfpu[6] = Fmax
+sfpu[7] = Fmvx
+sfpu[8] = Fmvf
+sfpu[9] = feq
+sfpu[10] = flt
+sfpu[11] = fle
+sfpu[12] = Fmadd
+sfpu[13] = Fmsubb
+sfpu[14] = FCVT.W.P
+sfpu[15] = FCVT.P.W
+sfpu[16] = Fnmsubb
+sfpu[17] = Fnmadd
+sfpu[18] = fsgnj
+sfpu[19] = fsgnjn
+sfpu[20] = fsgnjx
+sfpu[21] = fclass
+sfpu[22] = unsign
+sfpu[23] = sign
+*/
+
+
+/* CSR flag registers adrsses
+CSR[4] = NV
+CSR[3] = DZ
+CSR[2] = OF
+CSR[1] = UF
+CSR[0] = NX
+*/
+
+//Module instantiation for input vlaidation stage of the FPU
+wire [std:0] output_interim_input_validation_temp_storage;
+wire output_interim_input_validation_exception_flag_Fadd,output_interim_input_validation_exception_flag_Fsub,output_interim_input_validation_exception_flag_Fmul ,output_interim_input_validation_exception_flag_Fdiv, output_interim_input_validation_exception_flag_Fsqrt, output_interim_input_validation_exception_flag_Fcomp, output_interim_input_validation_exception_flag_Fmadd, output_interim_input_validation_exception_flag_Fmsub;
+wire Exception_flag_interim ;
+wire output_interim_input_validation_Divide_By_Zero;
+wire output_interim_input_validation_invalid_flag;
+FPU_Input_Validation input_Validation (
+ .INPUT_VALIDATION_input_ieee_A(Operand_A),
+ .INPUT_VALIDATION_input_ieee_B(Operand_B),
+ .INPUT_VALIDATION_input_ieee_C(Operand_C),
+ .INPUT_VALIDATION_input_opcode(sfpu_op),
+ .INPUT_VALIDATION_Output_temp_storage (output_interim_input_validation_temp_storage),
+ .INPUT_VALIDATION_Output_exception_flag_Fadd (output_interim_input_validation_exception_flag_Fadd),
+ .INPUT_VALIDATION_Output_exception_flag_Fsub (output_interim_input_validation_exception_flag_Fsub),
+ .INPUT_VALIDATION_Output_exception_flag_Fmul (output_interim_input_validation_exception_flag_Fmul),
+ .INPUT_VALIDATION_Output_exception_flag_Fdiv (output_interim_input_validation_exception_flag_Fdiv),
+ .INPUT_VALIDATION_Output_exception_flag_Fsqrt (output_interim_input_validation_exception_flag_Fsqrt),
+ .INPUT_VALIDATION_Output_exception_flag_Fcomp (output_interim_input_validation_exception_flag_Fcomp),
+ .INPUT_VALIDATION_Output_exception_flag_Fmadd (output_interim_input_validation_exception_flag_Fmadd),
+ .INPUT_VALIDATION_Output_exception_flag_Fmsub (output_interim_input_validation_exception_flag_Fmsub),
+ .INPUT_VALIDATION_Output_Flag_DZ (output_interim_input_validation_Divide_By_Zero),
+ .INPUT_VALIDATION_Output_invalid_flag (output_interim_input_validation_invalid_flag),
+ .interupt_Pin(interupt_Pin),
+ .rst_l(rst_l)
+);
+
+assign Exception_flag_interim = output_interim_input_validation_exception_flag_Fadd | output_interim_input_validation_exception_flag_Fsub | output_interim_input_validation_exception_flag_Fmul | output_interim_input_validation_exception_flag_Fdiv | output_interim_input_validation_exception_flag_Fsqrt | output_interim_input_validation_exception_flag_Fcomp | output_interim_input_validation_exception_flag_Fmadd |output_interim_input_validation_exception_flag_Fmsub ;
+assign Exception_flag = Exception_flag_interim ;
+
+defparam input_Validation.std=std;
+defparam input_Validation.man=man;
+defparam input_Validation.exp=exp;
+defparam input_Validation.bias=Bias;
+
+//module instantiation for Fmove instruction
+wire [std:0] output_interim_Fmove;
+
+FPU_move Floating_move (
+ .rst_l(rst_l),
+ .opcode({(sfpu_op[8]),(sfpu_op[7] | vfpu_op[4])}),
+ .Move_Input_IEEE(Operand_A),
+ .Move_Output_IEEE(output_interim_Fmove)
+);
+defparam Floating_move.Std = std;
+
+
+//module instantiation of FPU_sign injection instructions
+wire [std:0] output_interim_FPU_sign;
+FPU_sign Floating_sign_injection (
+ .rst_l(rst_l),
+ .op({(sfpu_op[20] | vfpu_op[24]),(sfpu_op[19] | vfpu_op[23]),(sfpu_op[18] | vfpu_op[22])}),
+ .IEEE_A(Operand_A),
+ .IEEE_B(Operand_B),
+ .IEEE_out(output_interim_FPU_sign)
+);
+defparam Floating_sign_injection.Std=std;
+defparam Floating_sign_injection.Man=man;
+defparam Floating_sign_injection.Exp=exp;
+
+//module instatiation of Float to int instrution
+wire [31:0] output_interim_FLOAT_to_Int;
+wire output_interim_Invalid_Flag_Float_To_Int;
+wire output_interim_Inexact_Flag_Float_To_Int;
+FPU_Float_to_Int Floating_Float2Int(
+ .FLOAT_TO_INT_input_float(Operand_A),
+ .FLOAT_TO_INT_input_rm(frm),
+ .FLOAT_TO_INT_input_opcode_FI (sfpu_op[14] | vfpu_op[18]),
+ .FLOAT_TO_INT_input_opcode_unsigned(sfpu_op[22] | vfpu_op[26]),
+ .FLOAT_TO_INT_input_opcode_signed(sfpu_op[23] | vfpu_op[27]),
+ .FLOAT_TO_INT_output_int(output_interim_FLOAT_to_Int),
+ .FLOAT_TO_INT_output_invalid_flag(output_interim_Invalid_Flag_Float_To_Int),
+ .FLOAT_TO_INT_output_inexact_flag(output_interim_Inexact_Flag_Float_To_Int),
+ .rst_l(rst_l)
+);
+defparam Floating_Float2Int.std=std;
+defparam Floating_Float2Int.man=man;
+defparam Floating_Float2Int.exp=exp;
+defparam Floating_Float2Int.bias=Bias;
+
+//module instantiation of In to FLoat istruction
+wire [std:0] output_interim_Int_to_Float;
+wire output_interim_Invalid_Flag_Int_To_Float;
+wire output_interim_Inexact_Flag_Int_To_Float;
+
+FPU_Int_to_Float floating_Int2Float (
+ .INT_TO_FLOAT_input_int(Operand_Int),
+ .INT_TO_FLOAT_input_rm(frm),
+ .INT_TO_FLOAT_input_opcode_IF (sfpu_op[15] | vfpu_op[19]),
+ .INT_TO_FLOAT_input_opcode_signed (sfpu_op[23] | vfpu_op[27]),
+ .INT_TO_FLOAT_input_opcode_unsigned (sfpu_op[22] | vfpu_op[26]),
+ .INT_TO_FLOAT_output_float(output_interim_Int_to_Float),
+ .INT_TO_FLOAT_output_invalid_flag(output_interim_Invalid_Flag_Int_To_Float),
+ .INT_TO_FLOAT_output_inexact_flag (output_interim_Inexact_Flag_Int_To_Float),
+ .rst_l(rst_l)
+);
+defparam floating_Int2Float.std=std;
+defparam floating_Int2Float.man=man;
+defparam floating_Int2Float.exp=exp;
+defparam floating_Int2Float.bias=Bias;
+
+
+//module instatniation of comparision instructions
+wire [31:0] output_interim_Comparison;
+wire [7:0] input_Opcode_Fcomp;
+wire [std:0] output_interim_Fmax_Fmin;
+assign input_Opcode_Fcomp = {(sfpu_op[6] | vfpu_op[3]),(sfpu_op[5] | vfpu_op[2]),vfpu_op[10],vfpu_op[9],(sfpu_op[11] | vfpu_op[6]),(sfpu_op[10] | vfpu_op[7]),vfpu_op[8],(sfpu_op[9] | vfpu_op[5])};
+
+FPU_Comparison Floating_Comparison (
+ .rst_l(rst_l),
+ .opcode(input_Opcode_Fcomp),
+ .Comparator_Input_IEEE_A(Operand_A),
+ .Comparator_Input_IEEE_B(Operand_B),
+ .Comparator_Output_IEEE(output_interim_Comparison),
+ .Min_Max_Output_IEEE(output_interim_Fmax_Fmin)
+);
+defparam Floating_Comparison.Std=std;
+defparam Floating_Comparison.Man=man;
+defparam Floating_Comparison.Exp=exp;
+
+/*//module instantiation for FCLASS instruction
+wire [std:0] output_interim_Fclass;
+
+FPU_Fclass Floating_Classify (
+ .rst_l (rst_l),
+ .Classification_Output (output_interim_Fclass),
+ .Classification_Input (Operand_A),
+ .opcode (sfpu_op[21] | vfpu_op[25])
+);
+defparam Floating_Classify.Std=std;
+defparam Floating_Classify.man=man;
+defparam Floating_Classify.exp=exp;
+*/
+// module instantiation for Fmadd/fmsub/fnmadd/fnmsub/fadd/fsub/fmul instruction
+wire [std:0] output_interim_FMADD,output_interim_Fmul;
+wire [2:0] output_interim_S_Flags_Fmul, output_interim_S_Flags_Fmadd;
+wire output_FMADD_interim_ready_Flagg;
+
+FPU_FMADD_SUBB_Top Floating_FMADD (
+ .FMADD_SUBB_input_IEEE_A(Operand_A),
+ .FMADD_SUBB_input_IEEE_B(Operand_B),
+ .FMADD_SUBB_input_IEEE_C(Operand_C),
+ .FMADD_SUBB_input_opcode( { (sfpu_op[16] | vfpu_op[20]),(sfpu_op[17] | vfpu_op[21]),(sfpu_op[13] | vfpu_op[14]),(sfpu_op[12] | vfpu_op[13]),(sfpu_op[2] | vfpu_op[12]),(sfpu_op[1] | vfpu_op[1]),(sfpu_op[0] | vfpu_op[0])} ),
+ .rst_l(rst_l),
+ .FMADD_SUBB_input_Frm(frm),
+ .FMADD_SUBB_output_IEEE_FMADD (output_interim_FMADD),
+ .FMADD_SUBB_output_S_Flags_FMADD(output_interim_S_Flags_Fmadd),
+ .FMADD_SUBB_output_IEEE_FMUL(output_interim_Fmul),
+ .FMADD_SUBB_output_S_Flags_FMUL(output_interim_S_Flags_Fmul)
+
+);
+defparam Floating_FMADD.std=std;
+defparam Floating_FMADD.man=man;
+defparam Floating_FMADD.exp=exp;
+defparam Floating_FMADD.bias=Bias;
+defparam Floating_FMADD.lzd=lzd;
+
+
+//block for declartion of register output port
+// THis port is anmed as FPU_reusltant_reg and would be assigned a 0 on reset of the FPU however the asssignent to this would be controlled by the opcode bits if the rsrt condition is not true.
+
+always @ (posedge clk)
+begin
+
+ if (~rst_l)
+ begin
+ FPU_resultant_reg <= 32'h00000000;
+ FPU_Result_rd_reg <= 32'h00000000;
+ S_Flags_reg <= 5'b00000;
+ end
+else if (Exception_flag_interim)
+ begin
+ FPU_resultant_reg <= output_interim_input_validation_temp_storage;
+ FPU_Result_rd_reg <= output_interim_input_validation_temp_storage;
+ S_Flags_reg <= { output_interim_input_validation_invalid_flag , output_interim_input_validation_Divide_By_Zero , 3'b000 } ;
+ end
+
+else if (rst_l & (~Exception_flag_interim) )
+begin
+
+ if ( sfpu_op[0] | sfpu_op[1] | sfpu_op[12] | sfpu_op[13] | sfpu_op[16] | sfpu_op[17] | vfpu_op[0] | vfpu_op[1] | vfpu_op[13] | vfpu_op[14] | vfpu_op[20] | vfpu_op[21]) //output selection for FMADD FMSUB FNMADD FNMSUBB FADD FSUB
+ begin
+ FPU_resultant_reg <= output_interim_FMADD;
+ FPU_Result_rd_reg <= 32'h00000000;
+ S_Flags_reg <= {2'b00,output_interim_S_Flags_Fmadd};
+ end
+
+ else if (sfpu_op[2] | vfpu_op[12]) //output selection for FMUL
+ begin
+ FPU_resultant_reg <= output_interim_Fmul;
+ FPU_Result_rd_reg <= 32'h00000000;
+ S_Flags_reg <= {2'b00,output_interim_S_Flags_Fmul};
+ end
+
+
+ else if (sfpu_op[15] | vfpu_op[19]) //otuput selection for Int to float intruction FCVT.S.W
+ begin
+ FPU_resultant_reg <= output_interim_Int_to_Float;
+ FPU_Result_rd_reg <= 32'h00000000;
+ S_Flags_reg <= {(output_interim_Invalid_Flag_Int_To_Float),3'b000,(output_interim_Inexact_Flag_Int_To_Float)};
+ end
+
+ else if (sfpu_op[18] | sfpu_op[19] | sfpu_op[20] | vfpu_op[22] | vfpu_op[23] |vfpu_op[24]) //output selection for sign injection instructions
+ begin
+ FPU_resultant_reg <= output_interim_FPU_sign;
+ FPU_Result_rd_reg <= 32'h00000000;
+ S_Flags_reg <= 5'b00000;
+ end
+
+ else if (sfpu_op[7] | sfpu_op[8] | vfpu_op[4]) //output selection for move instruction, FMOVE
+ begin
+ FPU_resultant_reg <= output_interim_Fmove;
+ FPU_Result_rd_reg <= (std==15) ? {16'h0000,output_interim_Fmove[15:0]} : output_interim_Fmove;
+ S_Flags_reg <= 5'b00000;
+ end
+
+ else if (sfpu_op[14] | vfpu_op[18]) //output selection logic for Float to int instruction FCVT.W.S
+ begin
+ FPU_resultant_reg <= 32'h00000000;
+ FPU_Result_rd_reg <= output_interim_FLOAT_to_Int;
+ S_Flags_reg <= {output_interim_Invalid_Flag_Float_To_Int,3'b000,output_interim_Inexact_Flag_Float_To_Int};
+ end
+
+ else if (sfpu_op[9] | sfpu_op[10] | sfpu_op[11] | (|vfpu_op[10:5])) //output selection for comparision instructions
+ begin
+ FPU_resultant_reg <= 32'h00000000;
+ FPU_Result_rd_reg <= output_interim_Comparison;
+ S_Flags_reg <= 5'b00000;
+ end
+
+ else if (sfpu_op[6] | sfpu_op[5] | vfpu_op[2] | vfpu_op[3]) // otuput sleection for Fmin,Max
+ begin
+ FPU_resultant_reg <= output_interim_Fmax_Fmin;
+ FPU_Result_rd_reg <= 32'h00000000;
+ S_Flags_reg <= 5'b00000;
+ end
+
+ /*else if (sfpu_op[21] | vfpu_op[25]) //output slection for Fclass instructions
+ begin
+ FPU_resultant_reg <= 32'h00000000;
+ FPU_Result_rd_reg <= output_interim_Fclass;
+ S_Flags_reg <= 5'b00000;
+ end*/
+ else
+ begin
+ FPU_resultant_reg <= 32'h00000000;
+ FPU_Result_rd_reg <= 32'h00000000;
+ S_Flags_reg <= 5'b00000;
+ end
+end
+
+end //end
+
+
+endmodule
+
diff --git a/verilog/rtl/FPU/FPU_comparison.v b/verilog/rtl/FPU/FPU_comparison.v
new file mode 100644
index 0000000..fc72822
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_comparison.v
@@ -0,0 +1,231 @@
+module FPU_Comparison(rst_l,opcode,Comparator_Input_IEEE_A,Comparator_Input_IEEE_B,Comparator_Output_IEEE,Min_Max_Output_IEEE);
+ //Standard Defination For Parameterization
+
+ parameter Std = 31; // Means IEEE754 Std 32 Bit Single Precision -1 for bits
+ parameter Exp = 7; // Means IEEE754 8 Bit For Exponents in Single Precision -1 for bits
+ parameter Man = 22; // Means IEEE754 23 Bit For Mantissa in Single Precision -1 for bits
+
+ input [Std : 0] Comparator_Input_IEEE_A, Comparator_Input_IEEE_B; // Std + 1 is for IEEE754 Hidden Bit inclusion
+ input [7:0]opcode;// opcode for selections
+ input rst_l;
+ output [31 : 0] Comparator_Output_IEEE;
+ output[Std:0] Min_Max_Output_IEEE;
+
+ reg [31 : 0] Comparator_Output_IEEE_reg;
+ reg [Std:0] Min_Max_Output_IEEE_reg;
+ wire Comparator_Sign_A, Comparator_Sign_B;
+ wire [Exp : 0] Comparator_Exp_A, Comparator_Exp_B;
+ wire [Man + 1 : 0] Comparator_Mantissa_A, Comparator_Mantissa_B;
+
+
+ //==========OPCODES============
+ // opcode [0] = feq
+ // opcode [1] = fne
+ // opcode [2] = flt
+ // opcode [3] = fle
+ // opcode [4] = fgt
+ // opcode [5] = fge
+ // opcode [6] = fmin
+ // opcode [7] = fmax
+
+ //============INPUTS=============
+ // Comparator_Input_IEEE_A
+ // Comparator_Input_IEEE_B
+
+ //============OUTPUTS============
+ // Comparator_Output_IEEE
+ // Min_Max_Output_IEEE
+
+ //=================FLAGS=========
+ // INVALID FLAG (NV)
+
+ assign Comparator_Sign_A = (rst_l) ? Comparator_Input_IEEE_A[Std] : 1'b0; // Sign Bit Assigning Std + 1 Because it contain IEEE754 hidden bit also
+ assign Comparator_Sign_B = (rst_l) ? Comparator_Input_IEEE_B[Std] : 1'b0; // Sign Bit Assigning Std + 1 Because it contain IEEE754 hidden bit also
+ assign Comparator_Exp_A = (rst_l) ? Comparator_Input_IEEE_A[Std - 1 : Std - Exp - 1] : {1'b0,{Exp{1'b0}}};
+ assign Comparator_Exp_B = (rst_l) ? Comparator_Input_IEEE_B[Std - 1 : Std - Exp - 1] : {1'b0,{Exp{1'b0}}};
+ assign Comparator_Mantissa_A = (rst_l) ? {1'b1,Comparator_Input_IEEE_A[Man : 0]} : {1'b0,{Man{1'b0}}};
+ assign Comparator_Mantissa_B = (rst_l) ? {1'b1,Comparator_Input_IEEE_B[Man : 0]} : {1'b0,{Man{1'b0}}};
+
+ assign Comparator_Output_IEEE = (rst_l==1'b0) ? 32'h00000000 : (opcode[0] == 1'b1) ? ((Comparator_Input_IEEE_A == Comparator_Input_IEEE_B) ? 32'h00000001 : 32'h00000000) : // Equal
+ (opcode[1] == 1'b1) ? ((Comparator_Input_IEEE_A != Comparator_Input_IEEE_B) ? 32'h00000001 : 32'h00000000) : // Not Equal
+
+ (opcode[2] == 1'b1) ? (((Comparator_Sign_A & Comparator_Sign_B) ? (((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A > Comparator_Mantissa_B))) ? 32'h00000001 : 32'h00000000) : (Comparator_Sign_A < Comparator_Sign_B) ? 32'h00000000 : (Comparator_Sign_A > Comparator_Sign_B) ? 32'h00000001 : (((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A < Comparator_Mantissa_B))) ? 32'h00000001 : 32'h00000000))) : // less than
+
+ (opcode[3] == 1'b1) ? (((Comparator_Sign_A & Comparator_Sign_B) ? (((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & ((Comparator_Mantissa_A > Comparator_Mantissa_B) | (Comparator_Mantissa_A == Comparator_Mantissa_B)))) ? 32'h00000001 : 32'h00000000) : (Comparator_Sign_A < Comparator_Sign_B) ? 32'h00000000 : (Comparator_Sign_A > Comparator_Sign_B) ? 32'h00000001 : (((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) && ((Comparator_Mantissa_A < Comparator_Mantissa_B) | (Comparator_Mantissa_A == Comparator_Mantissa_B)))) ? 32'h00000001 : 32'h00000000))) : // less and equal
+
+ (opcode[4] == 1'b1) ? (((Comparator_Sign_A & Comparator_Sign_B) ? (((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A < Comparator_Mantissa_B))) ? 32'h00000001 : 32'h00000000) : (Comparator_Sign_A > Comparator_Sign_B) ? 32'h00000000 : (Comparator_Sign_A < Comparator_Sign_B) ? 32'h00000001 : (((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A > Comparator_Mantissa_B))) ? 32'h00000001 : 32'h00000000))) : // greater than
+
+ (opcode[5] == 1'b1) ? (((Comparator_Sign_A & Comparator_Sign_B) ? (((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & ((Comparator_Mantissa_A < Comparator_Mantissa_B) | (Comparator_Mantissa_A == Comparator_Mantissa_B)))) ? 32'h00000001 : 32'h00000000) : (Comparator_Sign_A > Comparator_Sign_B) ? 32'h00000000 : (Comparator_Sign_A < Comparator_Sign_B) ? 32'h00000001 : (((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) && ((Comparator_Mantissa_A > Comparator_Mantissa_B) | (Comparator_Mantissa_A == Comparator_Mantissa_B)))) ? 32'h00000001 : 32'h00000000))) : // greater and equal
+
+ 32'h00000000;
+
+ assign Min_Max_Output_IEEE = (rst_l==1'b0) ? {Std+1{1'b0}} : (opcode[6] == 1'b1) ? (((Comparator_Sign_A & Comparator_Sign_B) ? (((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A > Comparator_Mantissa_B))) ? Comparator_Input_IEEE_A : Comparator_Input_IEEE_B) : (Comparator_Sign_A < Comparator_Sign_B) ? Comparator_Input_IEEE_B : (Comparator_Sign_A > Comparator_Sign_B) ? Comparator_Input_IEEE_A : (((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A < Comparator_Mantissa_B))) ? Comparator_Input_IEEE_A : Comparator_Input_IEEE_B))) : // Fmin
+ (opcode[7] == 1'b1) ? (((Comparator_Sign_A & Comparator_Sign_B) ? (((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A < Comparator_Mantissa_B))) ? Comparator_Input_IEEE_A : Comparator_Input_IEEE_B) : (Comparator_Sign_A > Comparator_Sign_B) ? Comparator_Input_IEEE_B : (Comparator_Sign_A < Comparator_Sign_B) ? Comparator_Input_IEEE_A : (((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A > Comparator_Mantissa_B))) ? Comparator_Input_IEEE_A : Comparator_Input_IEEE_B))) : // Fmax
+ {Std+1{1'b0}};
+
+
+ /* always @(*)
+ begin
+ */
+ /*if(rst_l == 1'b0)
+ begin
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000; // if reset the output will be 32 bit 0
+ Min_Max_Output_IEEE_reg = 32'b00000000000000000000000000000000; // if reset the output will be 32 bit 0
+ end
+
+
+
+ else if (opcode[0] == 1'b1) // A Equal to B
+ begin
+ if (Comparator_Input_IEEE_A == Comparator_Input_IEEE_B) // if both input is same the output is 32 bit 1 in Equal condition
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000; //if both input is not same the output is 32 bit 0
+ end
+
+ else if (opcode[1] == 1'b1) // A Not Equal to B
+ begin
+ if (Comparator_Input_IEEE_A != Comparator_Input_IEEE_B) //if both input is not same the output is 32 bit 1 in Not Equal condition
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000;//if both input is same the output is 32 bit 0 in Not Equal condition
+ end
+ */
+ /* else if (opcode[2] == 1'b1) // A Less than B
+ begin
+ if((Comparator_Sign_A & Comparator_Sign_B)==1) //check when both inputs are Negative
+ begin
+ if ((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A > Comparator_Mantissa_B))) // check when both inputs are negative and compare its exponent and mantissa when A is less than B the output is 32 bit 1.
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else // else when A is not less than B the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b0000000000000000000000000000000;
+ end
+ // check when both inputs are Positive and either one input is Negative
+ else if(Comparator_Sign_A < Comparator_Sign_B) // if input B is Negative and its Sign Bit is 1 the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000;
+ else if (Comparator_Sign_A > Comparator_Sign_B)// if input A is Negative and its Sign Bit is 1 the output is 32 bit 1's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+
+ //when both Inputs are Positive then compare its Exponent and Mantissa
+ else if ((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A < Comparator_Mantissa_B)))// if Exponent_A is less than Exponent_B the Output is 32 bit 1 and also check when Both Exponents are Equal and Mantissa_A is less than Mantissa_B then the output is 32 bit 1
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else// else when A is not less than B the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000;
+ end
+*/
+ /* else if (opcode[3] == 1'b1) // A Less than Equal to B
+ begin
+ if((Comparator_Sign_A & Comparator_Sign_B)==1)//check when both inputs are Negative
+ begin
+ if ((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & ((Comparator_Mantissa_A > Comparator_Mantissa_B) | (Comparator_Mantissa_A == Comparator_Mantissa_B))))// check when both inputs are negative and compare its exponent and mantissa when A is less than Equal to B the output is 32 bit 1.
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else // else when A is not less than Equal to B the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b0000000000000000000000000000000;
+ end
+ // check when both inputs are Positive and either one input is Negative
+ else if(Comparator_Sign_A < Comparator_Sign_B)// if input B is Negative and its Sign Bit is 1 the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000;
+ else if (Comparator_Sign_A > Comparator_Sign_B)// if input A is Negative and its Sign Bit is 1 the output is 32 bit 1's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+
+ //when both Inputs are Positive then compare its Exponent and Mantissa
+ else if ((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) && ((Comparator_Mantissa_A < Comparator_Mantissa_B) | (Comparator_Mantissa_A == Comparator_Mantissa_B))))// if Exponent_A is less than Exponent_B the Output is 32 bit 1 and also check when Both Exponents are Equal and Mantissa_A is less than Mantissa_B and also both Mantissa's are Equal then the output is 32 bit 1
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else // else when A is not less than B the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000;
+ end
+*/
+ /* else if (opcode[4] == 1'b1) // A Greter than B
+ begin
+ if((Comparator_Sign_A & Comparator_Sign_B)==1)//check when both inputs are Negative
+ begin
+ if ((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A < Comparator_Mantissa_B)))// check when both inputs are negative and compare its exponent and mantissa when A is Greater than B the output is 32 bit 1.
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else // else when A is not Greater than B the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b0000000000000000000000000000000;
+ end
+ // check when both inputs are Positive and either one input is Negative
+ else if(Comparator_Sign_A > Comparator_Sign_B)// if input A is Negative and its Sign Bit is 1 the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000;
+ else if (Comparator_Sign_A < Comparator_Sign_B)// if input B is Negative and its Sign Bit is 1 the output is 32 bit 1's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+
+ //when both Inputs are Positive then compare its Exponent and Mantissa
+ else if ((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A > Comparator_Mantissa_B)))// if Exponent_A is Greater than Exponent_B the Output is 32 bit 1 and also check when Both Exponents are Equal and Mantissa_A is Greater than Mantissa_B then the output is 32 bit 1
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else// else when A is not less than B the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000;
+
+ end
+*/
+/* else if (opcode[5] == 1'b1) // A Greater than Equal to B
+ begin
+ if((Comparator_Sign_A & Comparator_Sign_B)==1)//check when both inputs are Negative
+ begin
+ if ((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & ((Comparator_Mantissa_A < Comparator_Mantissa_B) | (Comparator_Mantissa_A == Comparator_Mantissa_B))))// check when both inputs are negative and compare its exponent and mantissa when A is Greater than Equal to B the output is 32 bit 1.
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else // else when A is not Greater than B the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b0000000000000000000000000000000;
+ end
+
+ // check when both inputs are Positive and either one input is Negative
+ else if(Comparator_Sign_A > Comparator_Sign_B)// if input A is Negative and its Sign Bit is 1 the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000;
+ else if (Comparator_Sign_A < Comparator_Sign_B)// if input B is Negative and its Sign Bit is 1 the output is 32 bit 1's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+
+ //when both Inputs are Positive then compare its Exponent and Mantissa
+ else if ((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) && ((Comparator_Mantissa_A > Comparator_Mantissa_B) | (Comparator_Mantissa_A == Comparator_Mantissa_B))))// if Exponent_A is Greater than Exponent_B the Output is 32 bit 1 and also check when Both Exponents are Equal and Mantissa_A is Greater than Mantissa_B and also both Mantissa's are Equal then the output is 32 bit 1
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000001;
+ else // else when A is not less than B the output is 32 bit 0's
+ Comparator_Output_IEEE_reg = 32'b00000000000000000000000000000000;
+ end
+ */
+ /*else if (opcode[6] == 1'b1) // Min
+ begin
+ if((Comparator_Sign_A & Comparator_Sign_B)==1)//check when both inputs are Negative
+ begin
+ if ((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A > Comparator_Mantissa_B)))// check when both inputs are negative and compare its exponent and mantissa when A is Minimum to B the output is Input A.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_A;
+ else // else when A is not Minimum to B the output is Input B.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_B;
+ end
+
+ // check when both inputs are Positive and either one input is Negative
+ else if(Comparator_Sign_A < Comparator_Sign_B) // if input B is Negative and its Sign Bit is 1 the output is Input B.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_B;
+ else if (Comparator_Sign_A > Comparator_Sign_B) // if input A is Negative and its Sign Bit is 1 the output is Input A.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_A;
+
+ //when both Inputs are Positive then compare its Exponent and Mantissa
+ else if ((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A < Comparator_Mantissa_B)))// if Exponent_A is less than Exponent_B the Output is Input A and also check when Both Exponents are Equal and Mantissa_A is less than Mantissa_B then the output is Input A.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_A;
+ else// else when A is not Minimum to B the output is Input B.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_B;
+ end
+
+ */
+ /* else if (opcode[7] == 1'b1) // Max
+ begin
+ if((Comparator_Sign_A & Comparator_Sign_B)==1)//check when both inputs are Negative
+ begin
+ if ((Comparator_Exp_A < Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A < Comparator_Mantissa_B)))// check when both inputs are negative and compare its exponent and mantissa when A is Maximum than B the output is Input A.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_A;
+ else // else when A is not Maximum to B the output is Input B.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_B;
+ end
+ //when both Inputs are Positive then compare its Exponent and Mantissa
+ else if(Comparator_Sign_A > Comparator_Sign_B) // if input A is Negative and its Sign Bit is 1 the output is Input B.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_B;
+ else if (Comparator_Sign_A < Comparator_Sign_B) // if input B is Negative and its Sign Bit is 1 the output is Input A.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_A;
+
+ //when both Inputs are Positive then compare its Exponent and Mantissa
+ else if ((Comparator_Exp_A > Comparator_Exp_B) | ((Comparator_Exp_A == Comparator_Exp_B) & (Comparator_Mantissa_A > Comparator_Mantissa_B)))// if Exponent_A is Greater than Exponent_B the Output is Input A and also check when Both Exponents are Equal and Mantissa_A is Greater than Mantissa_B then the output is Input A.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_A;
+ else// else when A is not Maximum to B the output is Input B.
+ Min_Max_Output_IEEE_reg = Comparator_Input_IEEE_B;
+ end
+ end
+*/
+endmodule
diff --git a/verilog/rtl/FPU/FPU_dec_ctl.v b/verilog/rtl/FPU/FPU_dec_ctl.v
new file mode 100644
index 0000000..bc0a59b
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_dec_ctl.v
@@ -0,0 +1,1050 @@
+module FPU_dec_ctl (
+input fpu_active,
+input [31:0] instr,
+output [114:0] out
+);
+
+wire [31:0] i;
+assign i[31:0] = (fpu_active) ? instr[31:0] : {32{1'b0}};
+
+localparam rs1 = 0;
+localparam rs2 = 1;
+localparam rd = 2;
+localparam vs1 = 3;
+localparam vs2 = 4;
+localparam vs3 = 5;
+localparam vd = 6;
+localparam imm12 = 7;
+localparam simm = 8;
+localparam vm = 9;
+localparam vsetvl = 10;
+localparam valu = 11;
+localparam vmul = 12;
+localparam vdiv = 13;
+localparam vrem = 14;
+localparam vlsu = 15;
+localparam vload = 16;
+localparam vstore = 17;
+localparam vadd = 18;
+localparam vsub = 19;
+localparam vand = 20;
+localparam vor = 21;
+localparam vxor = 22;
+localparam vsll = 23;
+localparam vsra = 24;
+localparam vsrl = 25;
+localparam vmslt = 26;
+localparam vmseq = 27;
+localparam vmsne = 28;
+localparam vmsle = 29;
+localparam vmsgt = 30;
+localparam unsign = 31;
+localparam sign = 32;
+localparam by = 33;
+localparam half = 34;
+localparam word = 35;
+localparam element = 36;
+localparam csr_read = 37;
+localparam csr_write_1 = 38;
+localparam csr_write_2 = 39;
+localparam rs1_sign = 40;
+localparam rs2_sign = 41;
+localparam vs1_sign = 42;
+localparam vs2_sign = 43;
+localparam low = 44;
+localparam unit_st = 45;
+localparam stride = 46;
+localparam indexed = 47;
+localparam zero_extend = 48;
+localparam sign_extend = 49;
+localparam i0_only = 50;
+localparam legal = 51;
+localparam vmin = 52;
+localparam vmax = 53;
+localparam fs1 = 54;
+localparam fs2 = 55;
+localparam fs3 = 56;
+localparam fd = 57;
+localparam vfadd = 58;
+localparam vfsub = 59;
+localparam vfmin = 60;
+localparam vfmax = 61;
+localparam vfmv = 62;
+localparam vmfeq = 63;
+localparam vmfle = 64;
+localparam vmflt = 65;
+localparam vmfne = 66;
+localparam vmfgt = 67;
+localparam vmfge = 68;
+localparam vfdiv = 69;
+localparam vfmul = 70;
+localparam vfmadd = 71;
+localparam vfmsub = 72;
+localparam vfsqrt = 73;
+localparam vfpu = 74;
+localparam fadd = 75;
+localparam fsub = 76;
+localparam fmul = 77;
+localparam fdiv = 78;
+localparam fsqrt = 79;
+localparam fmin = 80;
+localparam fmax = 81;
+localparam fmvx = 82;
+localparam fmvf = 83;
+localparam feq = 84;
+localparam flt = 85;
+localparam fle = 86;
+localparam fmadd = 87;
+localparam fmsub = 88;
+localparam single_p = 89;
+localparam double_p = 90;
+localparam half_p = 91;
+localparam scalar_fpu = 92;
+localparam vector_fpu = 93;
+localparam vfmvs = 94;
+localparam vfmvf = 95;
+localparam vfcvt_x_f = 96;
+localparam vfcvt_f_x = 97;
+localparam fcvt_w_p = 98;
+localparam fcvt_p_w = 99;
+localparam fnmsub = 100;
+localparam fnmadd = 101;
+localparam fsgnj = 102;
+localparam fsgnjn = 103;
+localparam fsgnjx = 104;
+localparam fclass = 105;
+localparam vfnmadd = 106;
+localparam vfnmsub = 107;
+localparam vfsgnj = 108;
+localparam vfsgnjn = 109;
+localparam vfsgnjx = 110;
+localparam vfclass = 111;
+localparam flsu = 112;
+localparam fload = 113;
+localparam fstore = 114;
+
+assign out[rs1] = (!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]&i[14]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[27]&i[25]
+ &i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[29]&!i[28]&i[26]&i[25]&i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (i[31]&i[30]&i[28]&!i[27]&!i[25]&!i[24]&!i[23]
+ &!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]
+ &i[1]&i[0]) | (i[31]&i[30]&i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]
+ &i[0]) | (i[31]&i[30]&!i[29]&i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]
+ &i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]&i[4]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&!i[14]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]
+ &i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[12]&!i[6]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&i[13]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]
+ &i[25]&i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[29]&i[28]&i[25]&i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&!i[29]&i[25]&i[14]&i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]
+ &!i[27]&i[25]&i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[25]&i[14]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&!i[14]&!i[6]
+ &!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[12]&!i[6]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[13]&!i[6]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (i[15]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (i[16]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (i[17]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (i[18]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (i[19]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[14]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[14]&i[13]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[rs2] = (i[31]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&i[27]&!i[26]&i[25]&!i[14]&!i[13]&!i[12]&!i[6]&!i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[28]&i[27]&!i[26]&i[25]&i[14]&i[13]&!i[6]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[28]&i[27]&!i[26]&i[25]&i[14]&i[12]&!i[6]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]);
+
+assign out[rd] = (i[31]&i[29]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &!i[14]&!i[13]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[29]
+ &!i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]
+ &i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]&!i[28]
+ &!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]&i[4]&!i[3]&!i[2]
+ &i[1]&i[0]) | (i[31]&i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]
+ &!i[22]&!i[21]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[14]&i[13]
+ &i[12]&i[7]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[14]&i[13]
+ &i[12]&i[8]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[14]&i[13]
+ &i[12]&i[9]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[14]&i[13]
+ &i[12]&i[10]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[14]&i[13]
+ &i[12]&i[11]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]
+ &i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]
+ &i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[14]&!i[13]
+ &i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]
+ &!i[27]&!i[26]&!i[14]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]&i[4]
+ &!i[3]&!i[2]&i[1]&i[0]) | (i[15]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (i[16]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (i[17]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (i[18]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (i[19]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vs1] = (!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]&!i[14]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[26]&i[25]
+ &!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[29]&!i[28]&i[27]&i[25]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[26]&!i[14]&!i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]
+ &!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]
+ &!i[30]&!i[29]&i[25]&!i[14]&i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[27]&i[25]&!i[14]&!i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]
+ &i[26]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[29]&i[28]&i[25]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[27]&!i[26]&!i[14]
+ &!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]
+ &i[29]&!i[28]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[25]&!i[14]&!i[13]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&!i[29]&!i[27]&!i[26]
+ &!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &!i[30]&!i[29]&!i[26]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[25]&!i[14]&!i[13]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vs2] = (!i[31]&!i[28]&!i[27]&!i[26]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]
+ &!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]
+ &!i[29]&i[28]&!i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&i[26]&i[25]&!i[14]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]
+ &!i[27]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&i[29]&!i[28]&i[27]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[27]&i[25]&!i[13]
+ &!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]
+ &!i[27]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[29]&!i[28]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&!i[28]&i[27]&i[26]&!i[18]
+ &!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&i[27]&!i[26]&!i[19]&!i[18]&!i[17]
+ &!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]
+ &i[27]&i[26]&i[25]&i[14]&i[13]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&i[27]&i[26]&i[25]&i[14]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&i[27]&i[26]&i[25]&!i[14]&!i[13]&!i[12]&!i[6]&!i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (i[31]&!i[30]&!i[29]&i[25]&i[13]&!i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&!i[29]&i[28]&!i[27]&i[26]
+ &i[25]&!i[14]&i[13]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[30]&i[29]&i[28]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[25]&i[14]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[27]
+ &i[25]&!i[14]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[30]&i[29]&!i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&i[28]&i[25]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]
+ &!i[27]&!i[26]&i[25]&!i[14]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[31]&i[30]&i[29]&i[26]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[25]
+ &!i[13]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&!i[29]&!i[27]
+ &!i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[30]&i[29]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[25]&!i[13]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&!i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]
+ &!i[28]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[30]&i[29]&!i[28]&i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]);
+
+assign out[vs3] = (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[13]
+ &!i[6]&i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]
+ &!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&!i[12]&!i[6]&i[5]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&i[14]&i[12]&!i[6]&i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[31]&!i[30]&i[29]&!i[28]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&!i[14]&!i[13]&!i[12]&!i[6]
+ &i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[12]
+ &!i[6]&i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vd] = (!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[27]&i[25]&!i[14]
+ &i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]
+ &!i[28]&!i[27]&i[26]&i[25]&!i[14]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]&i[27]&i[25]&!i[14]&i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]
+ &i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&i[29]&!i[28]&i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[28]
+ &i[27]&i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]
+ &!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[13]&!i[6]&!i[5]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&i[14]&i[12]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]
+ &!i[12]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&!i[28]
+ &i[27]&i[26]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&i[27]&!i[26]
+ &!i[19]&!i[18]&!i[17]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[31]&!i[30]&!i[29]&i[25]&i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[28]&i[25]&!i[14]&i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&!i[29]&i[28]&!i[27]
+ &i[26]&i[25]&!i[14]&i[13]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&i[27]&i[25]&i[14]&i[13]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&i[30]&i[29]&i[25]&i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[25]&!i[14]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]
+ &!i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[29]&i[28]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[12]&!i[6]&!i[5]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[26]&i[14]&!i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&!i[14]
+ &!i[13]&!i[12]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]
+ &i[29]&!i[28]&!i[27]&i[25]&!i[13]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&i[25]&!i[14]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&!i[29]&!i[27]
+ &!i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[30]&i[29]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[25]&!i[13]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]
+ &!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]
+ &i[29]&!i[28]&i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[imm12] = (!i[31]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[14]&i[13]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[14]&i[12]&!i[6]
+ &!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[simm] = (!i[30]&i[29]&!i[28]&!i[27]&i[26]&i[25]&!i[14]&i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&!i[29]&i[28]&!i[27]
+ &i[26]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&i[25]&!i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[28]
+ &i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]&i[27]&i[25]
+ &!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[30]&i[29]&!i[27]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]);
+
+assign out[vm ] = 1'b0;
+
+assign out[vsetvl] = (i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[valu] = (!i[30]&i[29]&!i[28]&!i[27]&i[26]&i[25]&!i[14]&i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[26]&i[25]
+ &!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[29]
+ &!i[28]&i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (i[31]&!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]&!i[14]&i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]
+ &!i[28]&!i[27]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[28]&i[25]&!i[14]&i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&!i[29]&i[28]&!i[27]&i[26]
+ &i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&i[25]&!i[14]&i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[27]&i[25]
+ &!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &!i[30]&i[29]&!i[28]&i[27]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[25]&!i[13]
+ &!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]
+ &i[28]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[25]&i[14]&!i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[27]
+ &i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmul] = (i[31]&!i[30]&!i[29]&i[28]&i[25]&i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]);
+
+assign out[vdiv] = (i[31]&!i[30]&!i[29]&!i[28]&i[25]&i[13]&!i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vrem] = (i[31]&!i[30]&!i[29]&!i[28]&i[27]&i[25]&i[13]&!i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vlsu] = (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]
+ &!i[13]&!i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]
+ &i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[13]&!i[6]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&i[14]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&i[27]&i[25]&!i[14]&!i[13]&!i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[13]&!i[6]&!i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vload] = (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]
+ &!i[13]&!i[12]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]
+ &!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[13]&!i[6]
+ &!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]
+ &!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[12]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[28]&i[27]&i[25]&!i[14]&!i[13]&!i[12]&!i[6]&!i[5]
+ &!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[13]&!i[6]
+ &!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[12]
+ &!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vstore] = (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]
+ &!i[13]&!i[12]&!i[6]&i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]
+ &i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[13]&!i[6]&i[5]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&i[14]&i[12]&!i[6]&i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&i[27]&i[25]&!i[14]&!i[13]&!i[12]&!i[6]&i[5]&!i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[12]&!i[6]&i[5]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vadd] = (!i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&i[25]&!i[14]&i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]
+ &!i[28]&!i[27]&!i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]);
+
+assign out[vsub] = (!i[31]&i[30]&i[29]&!i[27]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[28]&i[25]&!i[14]
+ &i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]
+ &!i[29]&i[27]&!i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&i[28]&i[25]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]&i[25]
+ &!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]
+ &i[29]&i[25]&i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&i[30]&i[29]&!i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]);
+
+assign out[vand] = (!i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[26]&i[25]&!i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]
+ &!i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vor] = (!i[31]&!i[30]&i[29]&!i[28]&i[27]&!i[26]&i[25]&!i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]
+ &i[27]&!i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vxor] = (!i[31]&!i[30]&i[29]&!i[28]&i[27]&i[26]&i[25]&!i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]
+ &i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vsll] = (i[31]&!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]&!i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&!i[29]&i[28]
+ &!i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vsra] = (i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[26]&i[25]&!i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]
+ &!i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vsrl] = (i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[26]&i[25]&!i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]
+ &!i[27]&!i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vmslt] = (!i[31]&i[30]&i[29]&!i[28]&i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmseq] = (!i[31]&i[30]&i[29]&!i[28]&!i[27]&!i[26]&i[25]&!i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]
+ &!i[27]&!i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vmsne] = (!i[31]&i[30]&i[29]&!i[28]&!i[27]&i[26]&i[25]&!i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]
+ &!i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vmsle] = (!i[31]&i[30]&i[29]&i[28]&!i[27]&i[25]&!i[14]&i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[28]&!i[27]
+ &i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmsgt] = (!i[31]&i[30]&i[29]&i[28]&i[27]&i[25]&i[14]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[28]&i[27]
+ &i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[unsign] = (!i[31]&i[30]&i[29]&i[27]&!i[26]&i[25]&i[14]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&!i[29]&!i[28]&i[27]
+ &!i[26]&!i[19]&!i[18]&!i[17]&!i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]&!i[27]&!i[25]&!i[24]
+ &!i[23]&!i[22]&!i[21]&i[20]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&!i[29]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&i[20]
+ &i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[28]
+ &!i[26]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&i[30]&i[29]&!i[28]&i[27]&!i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&!i[29]&!i[26]&i[25]&i[13]
+ &!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]
+ &i[28]&!i[27]&!i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&i[28]&!i[26]&i[25]&!i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[sign] = (!i[31]&i[30]&i[29]&i[27]&i[26]&i[25]&i[14]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&!i[29]&!i[28]&i[27]
+ &!i[26]&!i[19]&!i[18]&!i[17]&i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]&!i[27]&!i[25]&!i[24]
+ &!i[23]&!i[22]&!i[21]&!i[20]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&!i[29]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[28]
+ &i[26]&i[25]&!i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&i[30]&i[29]&!i[28]&i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&!i[29]&i[26]&i[25]&i[13]
+ &!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]
+ &i[28]&!i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&i[28]&i[26]&i[25]&!i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[by] = (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]
+ &!i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&!i[14]
+ &!i[13]&!i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[half] = (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]
+ &!i[13]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]
+ &i[14]&!i[13]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[word] = (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]
+ &i[13]&!i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]
+ &i[14]&i[13]&!i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[element] = (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]
+ &i[13]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]
+ &i[14]&i[13]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[csr_read] = (!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&i[14]&i[13]&i[12]&!i[11]
+ &!i[10]&!i[9]&!i[8]&!i[7]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[csr_write_1] = (i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[csr_write_2] = (i[14]&i[13]&i[12]&i[7]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (i[14]&i[13]&i[12]&i[8]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[14]&i[13]&i[12]&i[9]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[14]&i[13]&i[12]&i[10]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[14]&i[13]&i[12]&i[11]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[15]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[16]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[17]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[18]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[19]&i[14]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[rs1_sign] = (i[31]&!i[30]&!i[29]&i[28]&i[27]&i[26]&i[25]&i[14]&i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[rs2_sign ] = 1'b0;
+
+assign out[vs1_sign] = (i[31]&!i[30]&!i[29]&i[28]&i[27]&i[26]&i[25]&!i[14]&i[13]
+ &!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vs2_sign] = (i[31]&!i[30]&!i[29]&i[28]&i[27]&i[25]&i[13]&!i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[low] = (i[31]&!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]&i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[unit_st] = (!i[28]&!i[27]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &!i[14]&!i[13]&!i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]
+ &!i[27]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[13]
+ &!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[27]&!i[26]&i[25]
+ &!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[12]&!i[6]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]);
+
+assign out[stride] = (!i[28]&i[27]&!i[26]&i[25]&!i[14]&!i[13]&!i[12]&!i[6]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[28]&i[27]&!i[26]&i[25]&i[14]&i[13]&!i[6]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&!i[26]&i[25]&i[14]&i[12]&!i[6]
+ &!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[indexed] = (!i[28]&i[27]&i[26]&i[25]&!i[14]&!i[13]&!i[12]&!i[6]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[26]&i[25]&i[14]&i[13]&!i[6]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[26]&i[25]&i[14]&i[12]&!i[6]
+ &!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[zero_extend] = (i[31]&!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]&!i[14]&i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]
+ &!i[28]&!i[27]&!i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[25]&!i[14]&i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[sign_extend] = (i[31]&!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]&!i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]
+ &!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[13]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &!i[14]&!i[13]&!i[12]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&i[12]
+ &!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]
+ &!i[27]&i[26]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[13]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[28]&i[27]&i[25]&!i[14]&!i[13]&!i[12]&!i[6]&!i[5]
+ &!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[14]&i[12]&!i[6]
+ &!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[i0_only] = (i[31]&!i[30]&!i[29]&!i[28]&i[25]&i[13]&!i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmin] = (!i[31]&!i[30]&!i[29]&i[28]&!i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmax] = (!i[31]&!i[30]&!i[29]&i[28]&i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[fs1] = (i[31]&i[29]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[29]&!i[28]
+ &!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[26]&i[14]
+ &!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]
+ &!i[27]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[30]&i[29]&!i[28]&!i[27]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[28]&i[27]&i[26]&i[25]&!i[24]&!i[23]
+ &!i[22]&!i[21]&!i[20]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&i[14]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (i[31]
+ &i[30]&!i[29]&!i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]&!i[28]&!i[27]
+ &!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&i[30]&i[29]&i[26]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[12]
+ &i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]
+ &!i[26]&!i[14]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
+ &!i[30]&!i[29]&!i[26]&i[14]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[1]&i[0]) | (
+ !i[30]&!i[29]&!i[27]&!i[26]&i[14]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[28]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&i[14]&!i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]
+ &!i[26]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]
+ &i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]
+ &i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[14]&!i[13]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[29]&i[28]&i[27]&!i[25]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[29]&i[28]&i[27]&!i[26]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[25]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[25]&i[6]&!i[5]&!i[4]&i[1]&i[0]) | (
+ !i[26]&i[6]&!i[5]&!i[4]&i[1]&i[0]);
+
+assign out[fs2] = (!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[12]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[14]&!i[12]
+ &i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]
+ &!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]
+ &i[29]&!i[28]&!i[27]&!i[26]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]
+ &i[0]) | (!i[31]&!i[30]&!i[28]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]&!i[26]&!i[14]&!i[13]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&i[13]&!i[6]&i[5]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[14]&i[12]&!i[6]&i[5]&!i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[31]&!i[30]&!i[29]&!i[25]&i[6]&!i[5]&!i[3]&!i[2]&i[1]
+ &i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[6]&!i[5]&!i[3]&!i[2]&i[1]
+ &i[0]) | (!i[25]&i[6]&!i[5]&!i[4]&i[1]&i[0]) | (!i[26]&i[6]&!i[5]
+ &!i[4]&i[1]&i[0]);
+
+assign out[fs3] = (!i[25]&i[6]&!i[5]&!i[4]&i[1]&i[0]) | (!i[26]&i[6]&!i[5]&!i[4]&i[1]
+ &i[0]);
+
+assign out[fd] = (!i[31]&i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[19]&!i[18]&!i[17]&!i[16]
+ &!i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &!i[14]&!i[13]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]
+ &i[30]&i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]
+ &!i[13]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]
+ &i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[24]
+ &!i[23]&!i[22]&!i[21]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
+ &!i[30]&!i[28]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[28]&!i[26]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]
+ &i[0]) | (!i[31]&!i[30]&!i[28]&!i[27]&!i[25]&!i[14]&!i[12]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]&!i[27]&!i[26]&!i[14]
+ &!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&i[13]&!i[6]&!i[5]
+ &!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[29]&i[28]&i[27]&!i[25]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[29]&i[28]&i[27]&!i[26]
+ &i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&i[12]&!i[6]&!i[5]&!i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[25]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[25]&i[6]&!i[5]&!i[4]&i[1]&i[0]) | (!i[26]
+ &i[6]&!i[5]&!i[4]&i[1]&i[0]);
+
+assign out[vfadd] = (!i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfsub] = (!i[31]&!i[30]&!i[29]&!i[28]&i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfmin] = (!i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfmax] = (!i[31]&!i[30]&!i[29]&i[28]&i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfmv] = (!i[31]&i[30]&!i[29]&i[28]&i[27]&i[26]&i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vfmvs] = (!i[31]&i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vfmvf] = (!i[31]&i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[19]&!i[18]&!i[17]
+ &!i[16]&!i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vmfeq] = (!i[31]&i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmfle] = (!i[31]&i[30]&i[29]&!i[28]&!i[27]&i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmflt] = (!i[31]&i[30]&i[29]&!i[28]&i[27]&i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmfne] = (!i[31]&i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmfgt] = (!i[31]&i[30]&i[29]&i[28]&!i[27]&i[26]&i[14]&!i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vmfge] = (!i[31]&i[30]&i[29]&i[28]&i[27]&i[26]&i[14]&!i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfdiv] = (i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfmul] = (i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfmadd] = (i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfmsub] = (i[31]&!i[30]&i[29]&!i[28]&i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfnmadd] = (i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfnmsub] = (i[31]&!i[30]&i[29]&!i[28]&i[27]&i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfsqrt] = (!i[31]&i[30]&!i[29]&!i[28]&i[27]&i[26]&!i[19]&!i[18]&!i[17]
+ &!i[16]&!i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vfcvt_x_f] = (!i[31]&i[30]&!i[29]&!i[28]&i[27]&!i[26]&!i[19]&!i[18]&!i[17]
+ &!i[16]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfcvt_f_x] = (!i[31]&i[30]&!i[29]&!i[28]&i[27]&!i[26]&!i[19]&!i[18]&!i[17]
+ &i[16]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfsgnj] = (!i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfsgnjn] = (!i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfsgnjx] = (!i[31]&!i[30]&i[29]&!i[28]&i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[vfclass] = (!i[31]&i[30]&!i[29]&!i[28]&i[27]&i[26]&i[19]&!i[18]&!i[17]
+ &!i[16]&!i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]);
+
+assign out[vfpu] = (!i[31]&!i[28]&!i[27]&!i[26]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]
+ &!i[14]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&i[29]
+ &!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]
+ &i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[29]&!i[28]&!i[27]&!i[25]
+ &!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[14]&!i[13]
+ &i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[26]
+ &!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]
+ &!i[27]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[30]&i[29]&!i[28]&!i[27]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&i[30]&i[28]&i[27]&i[26]&i[25]&!i[24]&!i[23]
+ &!i[22]&!i[21]&!i[20]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (i[31]&i[30]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]
+ &!i[13]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]
+ &!i[28]&i[27]&i[26]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&i[27]
+ &!i[26]&!i[19]&!i[18]&!i[17]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[31]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&i[14]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&!i[29]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]&!i[27]&!i[26]
+ &!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]
+ &i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[14]&!i[12]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[26]&i[14]&!i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]
+ &!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
+ &!i[30]&!i[28]&!i[26]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&!i[30]&i[29]&!i[28]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &!i[3]&i[1]&i[0]) | (!i[30]&!i[29]&!i[27]&!i[26]&!i[13]&i[12]&i[6]
+ &!i[5]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[27]&!i[26]
+ &!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]
+ &!i[28]&i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&!i[29]&i[28]&i[27]&!i[25]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&!i[29]&i[28]&i[27]&!i[26]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[29]&!i[25]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[29]&!i[26]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[25]&i[6]&!i[5]&!i[4]&i[1]&i[0]) | (!i[26]&i[6]&!i[5]&!i[4]&i[1]
+ &i[0]);
+
+assign out[fadd] = (!i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[25]&i[6]&!i[5]&i[4]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&i[6]
+ &!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fsub] = (!i[31]&!i[30]&!i[29]&!i[28]&i[27]&!i[25]&i[6]&!i[5]&i[4]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&i[27]&!i[26]&i[6]
+ &!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fmul] = (!i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[25]&i[6]&!i[5]&i[4]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&i[6]
+ &!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fdiv] = (!i[31]&!i[30]&!i[29]&i[28]&i[27]&!i[25]&i[6]&!i[5]&i[4]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&i[28]&i[27]&!i[26]&i[6]
+ &!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fsqrt] = (!i[31]&i[30]&!i[29]&i[28]&i[27]&!i[25]&i[6]&!i[5]&i[4]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&i[30]&!i[29]&i[28]&i[27]&!i[26]&i[6]&!i[5]
+ &i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fmin] = (!i[31]&!i[30]&i[29]&!i[28]&i[27]&!i[25]&!i[14]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]
+ &i[27]&!i[26]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]
+ &i[0]);
+
+assign out[fmax] = (!i[31]&!i[30]&i[29]&!i[28]&i[27]&!i[25]&!i[14]&!i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]
+ &i[27]&!i[26]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]
+ &i[0]);
+
+assign out[fmvx] = (i[31]&i[30]&i[29]&i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fmvf] = (i[31]&i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[feq] = (i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[27]
+ &!i[26]&!i[14]&i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[flt] = (i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[27]
+ &!i[26]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fle] = (i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[13]&!i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[27]
+ &!i[26]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fmadd] = (!i[25]&i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[26]&i[6]
+ &!i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fmsub] = (!i[25]&i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[26]&i[6]
+ &!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[fnmsub] = (!i[25]&i[6]&!i[5]&!i[4]&i[3]&!i[2]&i[1]&i[0]) | (!i[26]&i[6]
+ &!i[5]&!i[4]&i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fnmadd] = (!i[25]&i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[26]&i[6]
+ &!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]);
+
+assign out[fsgnj] = (!i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]
+ &!i[27]&!i[26]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]
+ &i[0]);
+
+assign out[fsgnjn] = (!i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]
+ &!i[27]&!i[26]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]
+ &i[0]);
+
+assign out[fsgnjx] = (!i[31]&!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&i[29]&!i[28]
+ &!i[27]&!i[26]&!i[14]&i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]
+ &i[0]);
+
+assign out[fcvt_w_p] = (i[31]&i[30]&!i[29]&!i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]
+ &!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]&i[4]
+ &!i[3]&!i[2]&i[1]&i[0]);
+
+assign out[fcvt_p_w] = (i[31]&i[30]&!i[29]&i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]
+ &i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]&i[4]&!i[3]
+ &!i[2]&i[1]&i[0]);
+
+assign out[fclass] = (i[31]&i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]
+ &i[0]) | (i[31]&i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&!i[2]&i[1]
+ &i[0]);
+
+assign out[flsu] = (!i[14]&i[13]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[14]&i[12]
+ &!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[fload] = (!i[14]&i[13]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[14]
+ &i[12]&!i[6]&!i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[fstore] = (!i[14]&i[13]&!i[6]&i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[14]
+ &i[12]&!i[6]&i[5]&!i[4]&!i[3]&i[2]&i[1]&i[0]);
+
+assign out[single_p] = (i[31]&i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &!i[14]&!i[13]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]
+ &i[30]&!i[29]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]&!i[26]&!i[25]
+ &!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&i[13]
+ &!i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]
+ &!i[27]&!i[26]&!i[25]&!i[14]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[29]&i[28]&i[27]&!i[26]&!i[25]
+ &i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]
+ &!i[25]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[26]&!i[25]&i[6]&!i[5]
+ &!i[4]&i[1]&i[0]);
+
+assign out[double_p] = (i[31]&i[29]&!i[28]&!i[27]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&!i[27]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &!i[14]&!i[13]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]
+ &i[30]&!i[29]&!i[27]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&i[13]&i[12]&!i[6]&!i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]&!i[26]&i[25]&!i[14]&!i[13]
+ &i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]
+ &!i[26]&i[25]&!i[14]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[30]&i[29]&!i[28]&!i[27]&!i[26]&i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&!i[29]&i[28]&i[27]&!i[26]&i[25]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[25]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[26]&i[25]&i[6]&!i[5]&!i[4]&i[1]
+ &i[0]);
+
+assign out[half_p] = (i[31]&i[29]&!i[28]&!i[27]&i[26]&!i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ i[31]&i[30]&!i[27]&i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &!i[14]&!i[13]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]
+ &i[30]&!i[29]&!i[27]&i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]&i[26]&!i[25]
+ &!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&i[29]
+ &!i[28]&!i[27]&i[26]&!i[25]&!i[14]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]
+ &i[0]) | (!i[14]&!i[13]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[30]&i[29]&!i[28]&!i[27]&i[26]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&!i[29]&i[28]&i[27]&i[26]&!i[25]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&i[26]&!i[25]&i[6]
+ &!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[26]&!i[25]&i[6]&!i[5]&!i[4]&i[1]
+ &i[0]);
+
+assign out[scalar_fpu] = (i[31]&i[29]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]
+ &i[29]&!i[28]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]
+ &!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[27]&!i[25]
+ &!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[27]&!i[26]&!i[24]&!i[23]
+ &!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]
+ &i[1]&i[0]) | (i[31]&i[30]&!i[29]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]
+ &!i[21]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[29]&!i[27]
+ &!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[28]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]
+ &i[0]) | (!i[31]&!i[30]&!i[28]&!i[26]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[12]
+ &i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]
+ &!i[26]&!i[14]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]
+ &i[29]&!i[28]&!i[27]&!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]
+ &i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[14]&!i[13]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&i[13]&!i[6]&!i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[14]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &!i[29]&i[28]&i[27]&!i[25]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&!i[29]&i[28]&i[27]&!i[26]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[29]&!i[25]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&!i[29]&!i[26]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[25]&i[6]&!i[5]&!i[4]&i[1]&i[0]) | (!i[26]&i[6]&!i[5]&!i[4]&i[1]
+ &i[0]);
+
+assign out[vector_fpu] = (!i[31]&!i[28]&!i[27]&!i[26]&!i[19]&!i[18]&!i[17]&!i[16]
+ &!i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[30]&i[29]&!i[28]&!i[27]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[26]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[28]&i[27]&i[26]&i[25]
+ &!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[13]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&!i[28]&i[27]&i[26]&!i[18]
+ &!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&!i[29]&!i[28]&i[27]&!i[26]&!i[19]&!i[18]&!i[17]&!i[14]&!i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]
+ &i[26]&i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[30]&!i[29]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (i[31]&!i[30]&i[29]&!i[28]&!i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&!i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[27]
+ &!i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]
+ &i[30]&i[29]&!i[28]&i[26]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]);
+
+assign out[legal] = (i[31]&i[29]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]
+ &!i[20]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
+ &!i[28]&!i[27]&!i[26]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]
+ &i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&i[29]&!i[28]&!i[27]
+ &!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]
+ &!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]
+ &i[29]&i[25]&i[14]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[31]&!i[30]&i[29]&!i[28]&!i[27]&i[25]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&i[26]&i[14]&i[12]&i[6]&!i[5]
+ &i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[25]
+ &!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]
+ &!i[28]&!i[26]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (
+ !i[31]&!i[30]&i[29]&!i[28]&i[27]&i[25]&i[13]&i[12]&i[6]&!i[5]&i[4]
+ &!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&i[26]&i[25]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&i[29]
+ &!i[28]&!i[27]&i[25]&!i[13]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&i[30]&i[29]&!i[27]&i[25]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[26]&!i[14]&!i[13]
+ &i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]
+ &i[26]&i[25]&!i[13]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]
+ &i[29]&!i[28]&!i[26]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[31]&i[29]&!i[28]&i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]&i[26]&!i[13]&i[12]&i[6]
+ &!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[13]
+ &i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[14]&i[13]&i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[27]&!i[25]
+ &!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (i[31]&i[30]&!i[27]&!i[26]&!i[24]&!i[23]
+ &!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]
+ &i[1]&i[0]) | (!i[31]&i[30]&i[28]&i[27]&i[26]&i[25]&!i[24]&!i[23]
+ &!i[22]&!i[21]&!i[20]&i[14]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]
+ &i[13]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[28]&!i[26]&i[25]&!i[24]
+ &!i[23]&!i[22]&!i[21]&!i[20]&!i[14]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&!i[26]&i[25]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[12]&!i[6]
+ &!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&i[30]&!i[28]&i[27]&i[26]&!i[18]
+ &!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&i[27]&!i[26]&!i[19]&!i[18]&!i[17]
+ &!i[14]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&i[30]
+ &!i[29]&!i[27]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]&!i[3]
+ &!i[2]&i[1]&i[0]) | (!i[31]&!i[28]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]
+ &!i[21]&!i[20]&i[14]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (i[31]
+ &i[30]&!i[29]&!i[27]&!i[26]&!i[24]&!i[23]&!i[22]&!i[21]&i[6]&!i[5]
+ &!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]&!i[25]&!i[14]
+ &!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[28]&i[27]&i[25]&i[13]
+ &!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]&!i[30]&!i[29]&i[25]&i[13]
+ &!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]
+ &!i[25]&!i[14]&!i[13]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
+ &i[30]&i[29]&i[28]&i[25]&i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]
+ &i[0]) | (!i[28]&i[27]&i[25]&!i[14]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[28]&i[27]&i[25]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (i[31]
+ &!i[30]&!i[29]&i[28]&!i[27]&i[26]&i[25]&i[13]&i[6]&!i[5]&i[4]&!i[3]
+ &i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&i[28]&i[25]&!i[13]&!i[12]
+ &i[6]&!i[5]&i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[30]&i[29]&!i[28]&!i[27]
+ &!i[26]&!i[14]&!i[12]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
+ &i[30]&i[29]&!i[27]&i[25]&!i[13]&!i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[25]&!i[13]&i[6]&!i[5]
+ &!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&i[25]
+ &i[12]&i[6]&!i[5]&!i[3]&i[1]&i[0]) | (!i[30]&!i[29]&!i[27]&!i[26]
+ &!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]
+ &!i[26]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[1]&i[0]) | (!i[31]&!i[29]
+ &i[28]&i[27]&!i[25]&i[6]&!i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]
+ &i[29]&!i[27]&!i[26]&!i[13]&i[12]&i[6]&!i[5]&!i[3]&i[2]&i[1]&i[0]) | (
+ i[31]&!i[30]&i[29]&!i[28]&!i[13]&i[12]&i[6]&!i[5]&i[4]&!i[3]&i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[25]&i[6]&!i[5]&!i[3]&!i[2]
+ &i[1]&i[0]) | (!i[31]&!i[29]&i[28]&i[27]&!i[26]&i[6]&!i[5]&!i[3]&!i[2]
+ &i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[26]&i[6]&!i[5]&!i[3]&!i[2]
+ &i[1]&i[0]) | (!i[14]&i[13]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (
+ !i[14]&i[12]&!i[6]&!i[4]&!i[3]&i[2]&i[1]&i[0]) | (!i[25]&i[6]&!i[5]
+ &!i[4]&i[1]&i[0]) | (!i[26]&i[6]&!i[5]&!i[4]&i[1]&i[0]);
+
+
+
+
+
+endmodule
diff --git a/verilog/rtl/FPU/FPU_decode.v b/verilog/rtl/FPU/FPU_decode.v
new file mode 100644
index 0000000..9b5d3c5
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_decode.v
@@ -0,0 +1,151 @@
+`include "FPU_fpr_ctl.v"
+`include "FPU_dec_ctl.v"
+
+module FPU_decode #(parameter FPLEN = 16)
+ (
+ input clk,
+ input rst_l,
+ input [31:0] instr,
+ input fpu_active,
+ input fpu_complete,
+ input [FPLEN-1:0]fpu_result_1,
+ output [2:0] scalar_control,
+ output [4:0] rs1_address,
+ output [4:0] rs2_address,
+ output [4:0] rd_address,
+ output illegal_instr,
+ output [23:0] sfpu_op,
+ output [2:0] fpu_rnd,
+ output [2:0] fpu_pre,
+ output [FPLEN-1:0] fs1_data,
+ output [FPLEN-1:0] fs2_data,
+ output [FPLEN-1:0] fs3_data,
+ output valid_execution,
+ output illegal_config,
+ input scan_mode,
+ output [3:0] float_control,
+ output halt_req,
+ output[2:0]fpu_sel
+ );
+
+ // Internal Wire and Reg decleration
+ wire [114:0] control_signals;
+ reg [114:0] control_signals_r;
+ wire [4:0] fs1_addr, fs2_addr, fs3_addr;
+ wire [FPLEN-1:0] fs1_data_w, fs2_data_w, fs3_data_w;
+ wire [4:0] fd_reg;
+ wire [1:0] fdest_pkg; // bit 1 = Floating Load, bit 0 = Floating Execution
+
+ // Floating Destination Register FLops
+ rvdffsc #(5) fd_reg_ff_x (.clk(clk), .rst_l(rst_l), .en(valid_execution & control_signals[51] & fpu_active), .clear(((~valid_execution | ~fpu_active) & fpu_complete)), .din(control_signals[57] ? instr[11:7] : 5'h00), .dout(fd_reg));
+
+ //rvdffsc #(5) fd_reg_ff_wb (.clk(clk), .rst_l(rst_l), .en(fpu_complete_w), .clear(~fpu_active & ~fpu_complete_w & fpu_complete), .din(fd_reg_x), .dout(fd_reg));
+
+ // Floating Destination write signal
+ rvdffsc #(2) fdest_pkg_ff_x (.clk(clk), .rst_l(rst_l), .en(valid_execution & control_signals[51] & fpu_active), .clear(((~valid_execution | ~fpu_active) & fpu_complete)), .din({control_signals[113],(control_signals[57] & ~control_signals[112])}), .dout(fdest_pkg));
+
+ //rvdffsc #(2) fdest_pkg_ff_wb (.clk(clk), .rst_l(rst_l), .en(fpu_complete_w), .clear(~fpu_active & ~fpu_complete_w & fpu_complete), .din(fdest_pkg_x), .dout(fdest_pkg));
+
+
+
+ // Initiating Floating Decode Controller
+ FPU_dec_ctl FPU_decode_controller (
+ .fpu_active(fpu_active),
+ .instr(instr),
+ .out(control_signals)
+ );
+
+
+ // Initiating Floating Point Register File
+ FPU_fpr_ctl floating_point_register_file (
+ .clk(clk),
+ .rst_l(rst_l),
+ .rden0(control_signals[54]),
+ .rden1(control_signals[55]),
+ .rden2(control_signals[56]),
+ .raddr0(fs1_addr),
+ .raddr1(fs2_addr),
+ .raddr2(fs3_addr),
+ .wen0(fpu_complete & fdest_pkg[0]), // single cycle port
+ .waddr0(fd_reg),
+ .wd0(fpu_result_1),
+ .rd0(fs1_data_w), // read data
+ .rd1(fs2_data_w),
+ .rd2(fs3_data_w),
+ .scan_mode(scan_mode)
+ );
+
+
+
+ assign illegal_instr = (rst_l == 1'b0) ? 1'b0 : ((fpu_active) & (control_signals[51] == 1'b0) & (~control_signals_r[51])) ? 1'b1 : 1'b0;
+
+ // For half precision
+ assign valid_execution = (rst_l == 1'b0) ? 1'b0 : (illegal_instr) ? 1'b0 : (fpu_active & control_signals[92] & control_signals_r[92] & ~control_signals[91] & ~control_signals_r[91]) ? 1'b0 : (fpu_active & (control_signals[91] | control_signals_r[91])) ? 1'b1 : 1'b0;
+
+ assign scalar_control = (rst_l == 1'b0) ? 3'b00 : control_signals[2:0]; // Contain the active signals for rs1, rs2, rd
+
+ // for half precision
+ assign illegal_config = (rst_l == 1'b0) ? 1'b0 : (fpu_active & (control_signals[89] | control_signals[90])) ? 1'b1 : 1'b0;
+
+ // Scalar Register address
+ assign rs1_address = (rst_l == 1'b0) ? 5'h00 : (valid_execution | control_signals[10]) ? instr[19:15] : 5'h00;
+ assign rs2_address = (rst_l == 1'b0) ? 5'h00 : (valid_execution | control_signals[10]) ? instr[24:20] : 5'h00;
+ assign rd_address = (rst_l == 1'b0) ? 5'h00 : (valid_execution | control_signals[10]) ? instr[11:7] : 5'h00;
+
+ // Floating Control
+ assign float_control = (rst_l == 1'b0) ? 4'b0000 : control_signals[57:54]; // Contain the active signals for fs1, fs2, fs3 and fd
+ // Floating Point Register address
+ assign fs1_addr = (rst_l == 1'b0) ? 5'h00 : (valid_execution & control_signals[54]) ? instr[19:15] : 5'h00;
+ assign fs2_addr = (rst_l == 1'b0) ? 5'h00 : (valid_execution & control_signals[55]) ? instr[24:20] : 5'h00;
+ assign fs3_addr = (rst_l == 1'b0) ? 5'h00 : (valid_execution & control_signals[56]) ? instr[31:27] : 5'h00;
+ // Scalar or Vector operation signals
+ assign fpu_sel = (rst_l == 1'b0 | illegal_config) ? 3'h0 : (valid_execution & fpu_active & control_signals[51]) ? {control_signals[93:92],control_signals[74]} : (~valid_execution | ~fpu_active | fpu_complete) ? 3'h0 : 3'h0;
+
+ always @(posedge clk) begin
+ if(rst_l == 1'b0 | illegal_config)
+ begin
+ control_signals_r <= 114'h0;
+ end
+
+ else
+ begin
+ // Execution Unit Valid signals and operands
+ if((valid_execution & control_signals[51] & fpu_active))
+ begin
+ control_signals_r <= control_signals;
+ end
+ else if((~valid_execution) | ((~fpu_active) & (fpu_complete)))
+ begin
+ control_signals_r <= 114'h0;
+ end
+ else
+ begin
+ control_signals_r <= control_signals_r;
+ end
+ end
+ end
+
+ // FP Execution Operands
+ assign fs1_data = (rst_l == 1'b0 | illegal_config) ? {FPLEN{1'b0}} : (valid_execution & control_signals[51] & fpu_active) ? fs1_data_w : (~valid_execution | ~fpu_active | fpu_complete) ? {FPLEN{1'b0}} : {FPLEN{1'b0}};
+
+ assign fs2_data = (rst_l == 1'b0 | illegal_config) ? {FPLEN{1'b0}} : (valid_execution & control_signals[51] & fpu_active) ? fs2_data_w : (~valid_execution | ~fpu_active | fpu_complete) ? {FPLEN{1'b0}} : {FPLEN{1'b0}};
+
+ assign fs3_data = (rst_l == 1'b0 | illegal_config) ? {FPLEN{1'b0}} : (valid_execution & control_signals[51] & fpu_active) ? fs3_data_w : (~valid_execution | ~fpu_active | fpu_complete) ? {FPLEN{1'b0}} : {FPLEN{1'b0}};
+
+ // Scalar Floating point Control Signals
+ assign sfpu_op = (rst_l == 1'b0 | illegal_config) ? 24'h0 : (valid_execution & fpu_active & control_signals[51] & control_signals[92]) ? {control_signals[32:31],control_signals[105:98],control_signals[88:75]} : (~valid_execution | ~fpu_active | fpu_complete) ? 24'h0 : 24'h0;
+
+ // Floating Rounding mode
+ assign fpu_rnd = (rst_l == 1'b0 | illegal_config) ? 3'h0 : (valid_execution & fpu_active & control_signals[51] & control_signals[92]) ? instr[14:12] : (~valid_execution | ~fpu_active | fpu_complete) ? 3'h0 : 3'h0;
+
+ // Precision info {half,double,single}
+ assign fpu_pre = (rst_l == 1'b0 | illegal_config) ? 3'h0 : (valid_execution & fpu_active & control_signals[51]) ? control_signals[91:89] : (~valid_execution | ~fpu_active | fpu_complete) ? 3'h0 : 3'h0;
+
+ // Halt the core when fdiv/fsqrt
+ assign halt_req = (rst_l == 1'b0 | illegal_config) ? 1'b0 : (control_signals[78] | control_signals[79]);
+
+
+
+endmodule
+
+
diff --git a/verilog/rtl/FPU/FPU_exu.v b/verilog/rtl/FPU/FPU_exu.v
new file mode 100644
index 0000000..86b1506
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_exu.v
@@ -0,0 +1,149 @@
+`include "FPU_comparison.v"
+`include "FPU_F2I.v"
+`include "FPU_Fclass.v"
+`include "FPU_Input_Validation.v"
+`include "FPU_move.v"
+`include "FPU_sign_injection.v"
+`include "FPU_Top_Single_Cycle.v"
+`include "FMADD_Add_Post_Normalization.v"
+`include "FMADD_exponent_addition.v"
+`include "FMADD_Exponent_Matching.v"
+`include "FMADD_extender.v"
+`include "FMADD_LZD_L0.v"
+`include "FMADD_LZD_L1.v"
+`include "FMADD_LZD_L2.v"
+`include "FMADD_LZD_L3.v"
+`include "FMADD_LZD_L4.v"
+`include "FMADD_LZD_main.v"
+`include "FMADD_mantissa_addition.v"
+`include "FMADD_mantissa_generator.v"
+`include "FMADD_mantissa_multiplication.v"
+`include "FMADD_Mul_Post_Normalization.v"
+`include "FMADD_rounding_block_Addition.v"
+`include "FMADD_rounding_block_Multiplication.v"
+`include "FMADD_Top_Single_Cycle.v"
+`include "I2F_main.v"
+`include "LZD_layer0.v"
+`include "LZD_layer1.v"
+`include "LZD_layer2.v"
+`include "LZD_layer3.v"
+`include "LZD_layer4.v"
+`include "LZD_main.v"
+`include "LZD_mux.v"
+`include "LZD_comb.v"
+
+
+module FPU_exu #(parameter FPLEN = 16) (
+input clk,
+input rst_l,
+input scan_mode,
+input valid_execution,
+input [3:0] float_control,
+input [23:0] sfpu_op,
+input [2:0] fpu_rnd,
+input [2:0] fpu_pre,
+input dec_i0_rs1_en_d, // Qualify GPR RS1 data
+input dec_i0_rs2_en_d, // Qualify GPR RS2 data
+input [31:0] gpr_i0_rs1_d, // DEC data gpr
+input [31:0] gpr_i0_rs2_d, // DEC data gpr
+input [FPLEN-1:0] fs1_data,
+input [FPLEN-1:0] fs2_data,
+input [FPLEN-1:0] fs3_data,
+input [2:0]fpu_sel,
+
+output [FPLEN-1:0] fpu_result_1, // single cycle result
+output [31:0] fpu_result_rd, // integer result
+output fpu_complete,
+output [4:0] sflags,
+output IV_exception
+);
+
+reg [23:0] sfpu_op_r;
+reg sfpu_alu_valid_r;
+wire [FPLEN-1:0] fs1_d;
+wire [FPLEN-1:0] fs2_d;
+wire [FPLEN-1:0] fs3_d;
+//wire [FPLEN-1:0] fpu_result_exu;
+wire [FPLEN-1:0] fpu_result_top;
+wire [FPLEN-1:0] fpu_result_rx;
+wire [4:0] fpu_flags;
+wire [31:0]FPU_Result_rd,Operand_Int;
+// sfpu_op [0] = fadd
+// sfpu_op [1] = fsub
+// sfpu_op [2] = fmul
+// sfpu_op [3] = fdiv
+// sfpu_op [4] = fsqrt
+// sfpu_op [5] = fmin
+// sfpu_op [6] = fmax
+// sfpu_op [7] = fmvx // int to float
+// sfpu_op [8] = fmvf // float to int
+// sfpu_op [9] = feq // result in rd
+// sfpu_op [10] = flt // result in rd
+// sfpu_op [11] = fle // result in rd
+// sfpu_op [12] = fmadd
+// sfpu_op [13] = fmsub
+// sfpu_op [14] = fcvt_w_p // float to int
+// sfpu_op [15] = fcvt_p_w // int to float
+// sfpu_op [16] = fnmsub
+// sfpu_op [17] = fnmadd
+// sfpu_op [18] = fsgnj
+// sfpu_op [19] = fsgnjn
+// sfpu_op [20] = fsgnjx
+// sfpu_op [21] = fclass // result store in rd
+// sfpu_op [22] = unsign
+// sfpu_op [23] = sign
+
+ rvdffe #(24) sfpu_op_ff (.*, .clk(clk), .en(valid_execution & fpu_sel[0]), .din(sfpu_op), .dout(sfpu_op_r));
+ //rvdffe #(FPLEN) fpu_result_ff (.*, .clk(clk), .en(fpu_complete), .din(fpu_result_exu), .dout(fpu_result_1));
+ rvdffs #(5) fpu_flags_ff (.*, .clk(clk), .en(fpu_complete), .din(fpu_flags), .dout(sflags));
+
+ always @(posedge clk) begin
+ if(rst_l == 1'b0) begin
+ sfpu_alu_valid_r <= 1'b0;
+ end
+ else begin
+ sfpu_alu_valid_r <= (|sfpu_op[2:0]) | (|sfpu_op[17:5]) | (|sfpu_op[21:18]);
+ end
+ end
+
+ // FPU operands
+ assign fs1_d[15:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & dec_i0_rs1_en_d & ~float_control[0]}} & gpr_i0_rs1_d[31:0] ) |
+ ({FPLEN{valid_execution & ~dec_i0_rs1_en_d & float_control[0] }} & fs1_data ));
+ assign Operand_Int = (rst_l == 1'b0) ? 32'h00000000 : (({32{valid_execution & dec_i0_rs1_en_d & ~float_control[0]}} & gpr_i0_rs1_d[31:0] )) ;
+ assign fs2_d[15:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & float_control[1] }} & fs2_data ));
+
+ assign fs3_d[15:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & float_control[2] }} & fs3_data ));
+
+
+ // FPU Top Module
+ FPU_Top Floating_Top (
+ .clk(clk),
+ .rst_l(rst_l),
+ .frm(fpu_rnd),
+ .sfpu_op(sfpu_op),
+ .vfpu_op(28'h0000000),
+ .fpu_sel(fpu_sel),
+ .Operand_A(fs1_d),
+ .Operand_B(fs2_d),
+ .Operand_C(fs3_d),
+ .FPU_resultant(fpu_result_top),
+ .S_Flags(fpu_flags),
+ .Exception_flag(IV_exception),
+ .interupt_Pin(),
+ .FPU_Result_rd(FPU_Result_rd),
+ .Operand_Int(Operand_Int)
+ );
+
+
+
+ assign fpu_complete = (rst_l == 1'b0) ? 1'b0 : (sfpu_alu_valid_r) ? 1'b1 : 1'b0;
+
+ // FPU FPR Result
+ assign fpu_result_1 = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (fpu_complete & (|sfpu_op_r[2:0] | (|sfpu_op_r[17:15]) | sfpu_op_r[7] | (|sfpu_op_r[20:18]) | (|sfpu_op_r[6:5]) | (|sfpu_op_r[13:12]))) ? fpu_result_top : {FPLEN{1'b0}};
+
+
+ // FPU GPR result
+ assign fpu_result_rd = (rst_l == 1'b0) ? {32{1'b0}} : (fpu_complete & ((|sfpu_op_r[11:9]) | sfpu_op_r[14] | sfpu_op_r[8] | sfpu_op_r[21])) ? FPU_Result_rd :
+ {32{1'b0}};
+
+endmodule
diff --git a/verilog/rtl/FPU/FPU_fpr_ctl.v b/verilog/rtl/FPU/FPU_fpr_ctl.v
new file mode 100644
index 0000000..7b1c185
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_fpr_ctl.v
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2020 MERL Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module FPU_fpr_ctl
+#(
+ parameter FPLEN = 16
+ ) (
+
+ input rden0,
+ input rden1,
+ input rden2,
+
+ input [4:0] raddr0, // logical read addresses
+ input [4:0] raddr1,
+ input [4:0] raddr2,
+
+ input wen0, // write enable
+ input [4:0] waddr0, // write address
+ input [FPLEN-1:0] wd0, // write data
+
+ input clk,
+ input rst_l,
+
+ output [FPLEN-1:0] rd0, // read data
+ output [FPLEN-1:0] rd1,
+ output [FPLEN-1:0] rd2,
+
+ input scan_mode
+);
+
+ wire [FPLEN-1:0] fpr_out [31:0]; // 32 x 32 bit FPRs
+ reg [FPLEN-1:0] fpr_in [31:0];
+ reg [31:0] w0v;
+ wire [31:0] fpr_wr_en;
+
+ // FPR Write Enables
+ assign fpr_wr_en[31:0] = (rst_l == 1'b0) ? {32{1'b1}} : (w0v[31:0]);
+
+generate
+ for (genvar j=0; j<32; j++) begin : fpr
+ rvdffe #(16) fprff (.*, .en(fpr_wr_en[j]), .din(fpr_in[j][FPLEN-1:0]), .dout(fpr_out[j][FPLEN-1:0]));
+ end : fpr
+endgenerate
+
+
+ // FPR Read logic
+ assign rd0 = (rst_l == 1'b0) ? {FPLEN{1'b0}} : ((rden0 == 1'b1)) ? fpr_out[raddr0][FPLEN-1:0] : {FPLEN{1'b0}};
+ assign rd1 = (rst_l == 1'b0) ? {FPLEN{1'b0}} : ((rden1 == 1'b1)) ? fpr_out[raddr1][FPLEN-1:0] : {FPLEN{1'b0}};
+ assign rd2 = (rst_l == 1'b0) ? {FPLEN{1'b0}} : ((rden2 == 1'b1)) ? fpr_out[raddr2][FPLEN-1:0] : {FPLEN{1'b0}};
+
+ // FPR write logic
+integer j;
+ always @(*) begin
+ if(rst_l == 1'b0) begin
+ w0v = 32'h00000000;
+ for(j=0; j<32; j=j+1) begin
+ fpr_in[j] = {FPLEN{1'b0}};
+ end
+ end
+ else begin
+ for (int j=0; j<32; j++ ) begin
+ w0v[j] = wen0 & (waddr0[4:0] == j );
+ fpr_in[j] = ({FPLEN{w0v[j]}} & wd0[FPLEN-1:0]);
+ end
+ end
+ end
+
+endmodule
diff --git a/verilog/rtl/FPU/FPU_move.v b/verilog/rtl/FPU/FPU_move.v
new file mode 100644
index 0000000..59320b6
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_move.v
@@ -0,0 +1,16 @@
+module FPU_move(rst_l,opcode,Move_Input_IEEE,Move_Output_IEEE);
+ //Standard Defination For Parameterization
+
+ parameter Std = 31; // Means IEEE754 Std 32 Bit Single Precision -1 for bits
+
+ input [Std : 0] Move_Input_IEEE; // Input of IEEE754 32 Move Instruction
+ input [1:0] opcode; // opcode for selection
+ input rst_l; // clock & reset for Synchronizations
+ output [Std : 0] Move_Output_IEEE; // Output of IEEE754 32 Move Instruction
+
+ wire [Std : 0] Move_Output_IEEE; // Define reg becuase it is Output of IEEE754 32 Move Instruction
+
+ // New logic will be
+ assign Move_Output_IEEE = (rst_l == 1'b0) ? 32'h00000000 : (opcode[0] == 1'b1) ? Move_Input_IEEE : (opcode[1] == 1'b1) ? Move_Input_IEEE : 32'h00000000;
+
+endmodule
diff --git a/verilog/rtl/FPU/FPU_sign_injection.v b/verilog/rtl/FPU/FPU_sign_injection.v
new file mode 100644
index 0000000..8110b58
--- /dev/null
+++ b/verilog/rtl/FPU/FPU_sign_injection.v
@@ -0,0 +1,26 @@
+module FPU_sign (rst_l,op,IEEE_A,IEEE_B,IEEE_out);
+
+ parameter Std = 31; // Means IEEE754 Std 32 Bit Single Precision -1 for bits
+ parameter Exp = 7; // Means IEEE754 8 Bit For Exponents in Single Precision -1 for bits
+ parameter Man = 22; // Means IEEE754 23 Bit For Mantissa in Single Precision -1 for bits
+
+ input rst_l;
+ input [2:0] op; // bit 0 sgnj, bit 1 sgnjn, bit 2 sgnjx
+ input [Std : 0] IEEE_A;
+ input [Std : 0] IEEE_B;
+ output [Std : 0] IEEE_out;
+
+ wire [2:0] op_r;
+ wire Sign_A, Sign_B;
+ wire [Exp : 0] Exp_A;
+ wire [Man : 0] Mantissa_A;
+
+
+ // New logic
+ assign Sign_A = (rst_l == 1'b0) ? 1'b0 : IEEE_A[Std];
+ assign Sign_B = (rst_l == 1'b0) ? 1'b0 : IEEE_B[Std];
+ assign Exp_A = (rst_l == 1'b0) ? 8'h00 : IEEE_A[Std - 1 : Std - Exp - 1];
+ assign Mantissa_A = (rst_l == 1'b0) ? 23'h0 : IEEE_A[Man : 0];
+ assign IEEE_out = (rst_l == 1'b0) ? 32'h0 : (op[0]) ? {Sign_B,Exp_A,Mantissa_A} : (op[1]) ? {~Sign_B,Exp_A,Mantissa_A} : (op[2]) ? {(Sign_A ^ Sign_B),Exp_A,Mantissa_A} : 32'h0;
+
+endmodule
diff --git a/verilog/rtl/FPU/I2F_main.v b/verilog/rtl/FPU/I2F_main.v
new file mode 100644
index 0000000..52a8137
--- /dev/null
+++ b/verilog/rtl/FPU/I2F_main.v
@@ -0,0 +1,120 @@
+`include "I2F_LZD.v"
+
+module FPU_Int_to_Float(INT_TO_FLOAT_input_int, INT_TO_FLOAT_input_rm, INT_TO_FLOAT_input_opcode_IF, INT_TO_FLOAT_input_opcode_signed, INT_TO_FLOAT_input_opcode_unsigned, INT_TO_FLOAT_output_float, INT_TO_FLOAT_output_invalid_flag, INT_TO_FLOAT_output_inexact_flag, rst_l);
+
+parameter std = 15; //Bfloat16 + IEEE16
+//parameter std = 31; //IEEE32
+//parameter std = 63; //IEEE64
+
+//parameter man = 6; // bfloat16
+parameter man = 9; // IEEE16
+//parameter man = 22; // IEEE32
+//parameter man = 51; //
+
+parameter exp = 4; // IEEE16
+//parameter exp = 7; // IEEE32 + Bfloat16
+//parameter exp = 10 // IEEE64
+
+//parameter bias = 127; // IEEE32 + Bfloat16
+parameter bias = 15; // IEEE16
+//parameter bias = 1023 // IEEE64
+
+parameter lzd = 4; //Constant for all STD since LZD is dealing this INT and INT is always of 32 bit
+parameter exp_cal = 31;
+
+
+
+//INPUTS
+input [31 : 0] INT_TO_FLOAT_input_int;
+input [2 : 0] INT_TO_FLOAT_input_rm;
+input INT_TO_FLOAT_input_opcode_IF, INT_TO_FLOAT_input_opcode_signed, INT_TO_FLOAT_input_opcode_unsigned;
+input rst_l;
+
+//OUTPUTS
+output [std : 0]INT_TO_FLOAT_output_float;
+output INT_TO_FLOAT_output_invalid_flag;
+output INT_TO_FLOAT_output_inexact_flag;
+
+//WIRES
+wire [31 : 0] INT_TO_FLOAT_input_wire_int;
+wire [31 : 0]INT_TO_FLOAT_reg_magnitude;
+wire [lzd : 0]INT_TO_FLOAT_wire_shifts; wire INT_TO_FLOAT_wire_lzd_valid;
+wire [31 : 0]INT_TO_FLOAT_wire_shifted_int;
+wire INT_TO_FLOAT_wire_guard, INT_TO_FLOAT_wire_round, INT_TO_FLOAT_wire_sticky;
+wire INT_TO_FLOAT_wire_condition_inf, INT_TO_FLOAT_wire_condition_rnte, INT_TO_FLOAT_wire_condition_rntmm;
+wire INT_TO_FLOAT_wire_inc_or_trunc;
+wire INT_TO_FLOAT_wire_carry_prediction;
+wire [man+1 : 0]INT_TO_FLOAT_rounded_h_man; wire INT_TO_FLOAT_rounded_h_man_carry;
+wire [51 : 0] INT_TO_FLOAT_wire_man_output_interim;
+wire [lzd : 0]INT_TO_FLOAT_wire_shifts_for_exp_cal;
+wire [exp : 0]INT_TO_FLOAT_wire_bias_toadd;
+wire [lzd : 0] INT_TO_FLOAT_wire_exp_interm_1;
+wire [exp : 0] INT_TO_FLOAT_wire_exp_output;
+wire [51 : 0]INT_TO_FLOAT_wire_man_output;
+wire INT_TO_FLOAT_wire_sign_output;
+wire [63 : 0]INT_TO_FLOAT_wire_64std_output;
+wire [std : 0]INT_TO_FLOAT_wire_rest_std_output;
+
+//If rst_l is low and if opcode is low then input is set zero and so is the output.
+assign INT_TO_FLOAT_input_wire_int = (INT_TO_FLOAT_input_opcode_IF && rst_l) ? INT_TO_FLOAT_input_int : 32'b0000_0000_0000_0000_0000_0000_0000_0000;
+
+//Checking MSB to check whether the number is -ve or +ve and then converting negative number to magnitude
+//Conversion is done only when unsigned opcode is high
+assign INT_TO_FLOAT_reg_magnitude = (INT_TO_FLOAT_input_wire_int[31] & INT_TO_FLOAT_input_opcode_signed) ?
+(~INT_TO_FLOAT_input_wire_int) + 1'b1 : INT_TO_FLOAT_input_wire_int;
+//Converting to 2's compliment by taking 2's compliment if sign == 1
+
+//Module instantiation of LZD
+FPU_I2F_LZD LZD (.I2F_LZD_input_int(INT_TO_FLOAT_reg_magnitude), .I2F_LZD_output_pos(INT_TO_FLOAT_wire_shifts), .I2F_LZD_output_val(INT_TO_FLOAT_wire_lzd_valid));
+
+assign INT_TO_FLOAT_wire_shifted_int = INT_TO_FLOAT_reg_magnitude << INT_TO_FLOAT_wire_shifts;
+
+//man in case of double precision will be 51 and 31-man will be a negative no (2's compliment) this will be a trash value however it will not be effecting our actual result since for that std 0 will be selected for all G, R, and S
+assign INT_TO_FLOAT_wire_guard = (std==63) ? 1'b0 : (INT_TO_FLOAT_wire_shifted_int[5'b11111 - (man+2'b10)]);
+assign INT_TO_FLOAT_wire_round = (std==63) ? 1'b0 : (INT_TO_FLOAT_wire_shifted_int[5'b11111 - (man+2'b11)]);
+assign INT_TO_FLOAT_wire_sticky = (std==63) ? 1'b0 : (|(INT_TO_FLOAT_wire_shifted_int[(5'b11111 - (man+3'b100)) : 0]));
+
+assign INT_TO_FLOAT_wire_condition_inf = ((INT_TO_FLOAT_wire_round | INT_TO_FLOAT_wire_guard | (INT_TO_FLOAT_wire_sticky)) & ((INT_TO_FLOAT_input_rm == 3'b011 & ~(INT_TO_FLOAT_input_wire_int[31] & INT_TO_FLOAT_input_opcode_signed))|(INT_TO_FLOAT_input_rm == 3'b010 & (INT_TO_FLOAT_input_wire_int[31] & INT_TO_FLOAT_input_opcode_signed))));
+assign INT_TO_FLOAT_wire_condition_rnte = (INT_TO_FLOAT_input_rm == 3'b000 & ((INT_TO_FLOAT_wire_guard & (INT_TO_FLOAT_wire_round | INT_TO_FLOAT_wire_sticky)) | (INT_TO_FLOAT_wire_guard & ((~INT_TO_FLOAT_wire_round) & ~(INT_TO_FLOAT_wire_sticky)) & INT_TO_FLOAT_wire_shifted_int[5'b11111 - (man+2'b01)])));
+assign INT_TO_FLOAT_wire_condition_rntmm = (INT_TO_FLOAT_input_rm == 3'b100 & ((INT_TO_FLOAT_wire_guard & (INT_TO_FLOAT_wire_round | INT_TO_FLOAT_wire_sticky)) | (INT_TO_FLOAT_wire_guard & ((~INT_TO_FLOAT_wire_round) & (~INT_TO_FLOAT_wire_sticky)))));
+
+assign INT_TO_FLOAT_wire_inc_or_trunc = INT_TO_FLOAT_wire_condition_inf | INT_TO_FLOAT_wire_condition_rnte | INT_TO_FLOAT_wire_condition_rntmm;
+
+//man in case of double precision will be 51 and 31-man will be a negative no (2's compliment) this will be a trash value however it will not be effecting our actual result since for that std 0 will be selected for carry
+assign INT_TO_FLOAT_wire_carry_prediction = (std == 64) ? (1'b0) : ((&INT_TO_FLOAT_wire_shifted_int[31 : 31-(man+1'b1)]) & (INT_TO_FLOAT_wire_inc_or_trunc));
+
+//Extra zero is added to make the size of LHS == RHS
+assign {INT_TO_FLOAT_rounded_h_man_carry, INT_TO_FLOAT_rounded_h_man} = {1'b0, INT_TO_FLOAT_wire_shifted_int[31 : 31-(man+1'b1)]} + INT_TO_FLOAT_wire_inc_or_trunc;
+
+// ({(51-man)}{1'b0}) is used to add zero at the end to make the mantissa same size as mantissa of DOUBLE PRECISION
+assign INT_TO_FLOAT_wire_man_output_interim = (std == 64) ?
+({INT_TO_FLOAT_wire_shifted_int[30 : 0], 21'b0_0000_0000_0000_0000_0000}) :
+({ (INT_TO_FLOAT_rounded_h_man[man : 0]), ({(51-man){1'b0}}) });
+
+//In case data is all zero output of LZD is zero in this case exponent will be 31-0 which is not ok therfore setting the exponent to all 1 so that exp will be 31-31 = 0
+assign INT_TO_FLOAT_wire_shifts_for_exp_cal = (!INT_TO_FLOAT_wire_lzd_valid) ? (exp_cal[lzd : 0]) : INT_TO_FLOAT_wire_shifts;
+
+//Subtracting shifts from 31 and adding carry_prediction in it.
+assign INT_TO_FLOAT_wire_exp_interm_1 = exp_cal[lzd : 0] - INT_TO_FLOAT_wire_shifts_for_exp_cal + INT_TO_FLOAT_wire_carry_prediction;
+
+//In case data is all zero than bias is not added
+assign INT_TO_FLOAT_wire_bias_toadd = (!INT_TO_FLOAT_wire_lzd_valid) ? ({(exp+1){1'b0}}) : (bias[exp : 0]);
+
+// ({(exp-lzd)}{1'b0}) using this command 7-4 = 3 times zeros are added into the exp_interm_1 to make it of the same size as expoent and bias
+assign INT_TO_FLOAT_wire_exp_output = ({ ({(exp-lzd){1'b0}}) ,INT_TO_FLOAT_wire_exp_interm_1}) + INT_TO_FLOAT_wire_bias_toadd;
+
+assign INT_TO_FLOAT_wire_man_output = (&INT_TO_FLOAT_wire_exp_output) ? ({52{1'b0}}) : (INT_TO_FLOAT_wire_man_output_interim) ;
+
+//Calculating sign of the output on the basis on input MSB and opcode, since incase of signed MSB is a negative number and is high only incase of negative number but this is not the case when dealing with unsigned numbers.
+assign INT_TO_FLOAT_wire_sign_output = (INT_TO_FLOAT_input_wire_int[31] & INT_TO_FLOAT_input_opcode_signed);
+
+assign INT_TO_FLOAT_output_float = {INT_TO_FLOAT_wire_sign_output, INT_TO_FLOAT_wire_exp_output, (INT_TO_FLOAT_wire_man_output[51 : (51-man)])};
+
+//INT_TO_FLOAT_output_reg_invalid_flag = 1'b0;//valid flag will always be low for single precision as 32 wire int can easily be
+//represented in single precision. flag will only come into play when deailing with IEEE16.
+assign INT_TO_FLOAT_output_invalid_flag = (std == 15) & (&INT_TO_FLOAT_wire_exp_output) ;
+
+//Inexact Flag
+assign INT_TO_FLOAT_output_inexact_flag = INT_TO_FLOAT_wire_guard | INT_TO_FLOAT_wire_round | INT_TO_FLOAT_wire_sticky;
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/LZD_comb.v b/verilog/rtl/FPU/LZD_comb.v
new file mode 100644
index 0000000..dbe5323
--- /dev/null
+++ b/verilog/rtl/FPU/LZD_comb.v
@@ -0,0 +1,11 @@
+module FPU_LZD_comb (in_bits, out_pos, out_val);
+
+input [1:0]in_bits;
+
+output out_pos;
+output out_val;
+
+assign out_pos = !in_bits[1];
+assign out_val = |in_bits;
+
+endmodule
diff --git a/verilog/rtl/FPU/LZD_layer0.v b/verilog/rtl/FPU/LZD_layer0.v
new file mode 100644
index 0000000..345c091
--- /dev/null
+++ b/verilog/rtl/FPU/LZD_layer0.v
@@ -0,0 +1,61 @@
+module LZD_layer_0 (L0_input_int, L0_output_pos_val);
+
+input [31:0] L0_input_int;
+output [31:0] L0_output_pos_val;
+
+wire L0_wire_pos_0 , L0_wire_val_0 ;
+wire L0_wire_pos_1 , L0_wire_val_1 ;
+wire L0_wire_pos_2 , L0_wire_val_2 ;
+wire L0_wire_pos_3 , L0_wire_val_3 ;
+wire L0_wire_pos_4 , L0_wire_val_4 ;
+wire L0_wire_pos_5 , L0_wire_val_5 ;
+wire L0_wire_pos_6 , L0_wire_val_6 ;
+wire L0_wire_pos_7 , L0_wire_val_7 ;
+wire L0_wire_pos_8 , L0_wire_val_8;
+wire L0_wire_pos_9 , L0_wire_val_9 ;
+wire L0_wire_pos_10 , L0_wire_val_10 ;
+wire L0_wire_pos_11 , L0_wire_val_11 ;
+wire L0_wire_pos_12 , L0_wire_val_12 ;
+wire L0_wire_pos_13 , L0_wire_val_13 ;
+wire L0_wire_pos_14 , L0_wire_val_14 ;
+wire L0_wire_pos_15 , L0_wire_val_15 ;
+
+//Layer 0
+FPU_LZD_comb L0_0 (.in_bits(L0_input_int[1:0]), .out_pos(L0_wire_pos_0), .out_val(L0_wire_val_0));
+FPU_LZD_comb L0_1 (.in_bits(L0_input_int[3:2]), .out_pos(L0_wire_pos_1), .out_val(L0_wire_val_1));
+FPU_LZD_comb L0_2 (.in_bits(L0_input_int[5:4]), .out_pos(L0_wire_pos_2), .out_val(L0_wire_val_2));
+FPU_LZD_comb L0_3 (.in_bits(L0_input_int[7:6]), .out_pos(L0_wire_pos_3), .out_val(L0_wire_val_3));
+FPU_LZD_comb L0_4 (.in_bits(L0_input_int[9:8]), .out_pos(L0_wire_pos_4), .out_val(L0_wire_val_4));
+FPU_LZD_comb L0_5 (.in_bits(L0_input_int[11:10]), .out_pos(L0_wire_pos_5), .out_val(L0_wire_val_5));
+FPU_LZD_comb L0_6 (.in_bits(L0_input_int[13:12]), .out_pos(L0_wire_pos_6), .out_val(L0_wire_val_6));
+FPU_LZD_comb L0_7 (.in_bits(L0_input_int[15:14]), .out_pos(L0_wire_pos_7), .out_val(L0_wire_val_7));
+FPU_LZD_comb L0_8 (.in_bits(L0_input_int[17:16]), .out_pos(L0_wire_pos_8), .out_val(L0_wire_val_8));
+FPU_LZD_comb L0_9 (.in_bits(L0_input_int[19:18]), .out_pos(L0_wire_pos_9), .out_val(L0_wire_val_9));
+FPU_LZD_comb L0_10 (.in_bits(L0_input_int[21:20]), .out_pos(L0_wire_pos_10), .out_val(L0_wire_val_10));
+FPU_LZD_comb L0_11 (.in_bits(L0_input_int[23:22]), .out_pos(L0_wire_pos_11), .out_val(L0_wire_val_11));
+FPU_LZD_comb L0_12 (.in_bits(L0_input_int[25:24]), .out_pos(L0_wire_pos_12), .out_val(L0_wire_val_12));
+FPU_LZD_comb L0_13 (.in_bits(L0_input_int[27:26]), .out_pos(L0_wire_pos_13), .out_val(L0_wire_val_13));
+FPU_LZD_comb L0_14 (.in_bits(L0_input_int[29:28]), .out_pos(L0_wire_pos_14), .out_val(L0_wire_val_14));
+FPU_LZD_comb L0_15 (.in_bits(L0_input_int[31:30]), .out_pos(L0_wire_pos_15), .out_val(L0_wire_val_15));
+
+assign L0_output_pos_val =
+{L0_wire_val_15, L0_wire_pos_15,
+ L0_wire_val_14, L0_wire_pos_14,
+ L0_wire_val_13, L0_wire_pos_13,
+ L0_wire_val_12, L0_wire_pos_12,
+ L0_wire_val_11, L0_wire_pos_11,
+ L0_wire_val_10, L0_wire_pos_10,
+ L0_wire_val_9, L0_wire_pos_9,
+ L0_wire_val_8, L0_wire_pos_8,
+ L0_wire_val_7, L0_wire_pos_7,
+ L0_wire_val_6, L0_wire_pos_6,
+ L0_wire_val_5, L0_wire_pos_5,
+ L0_wire_val_4, L0_wire_pos_4,
+ L0_wire_val_3, L0_wire_pos_3,
+ L0_wire_val_2, L0_wire_pos_2,
+ L0_wire_val_1, L0_wire_pos_1,
+ L0_wire_val_0, L0_wire_pos_0};
+
+
+endmodule
+
diff --git a/verilog/rtl/FPU/LZD_layer1.v b/verilog/rtl/FPU/LZD_layer1.v
new file mode 100644
index 0000000..3cf47ce
--- /dev/null
+++ b/verilog/rtl/FPU/LZD_layer1.v
@@ -0,0 +1,35 @@
+module LZD_layer_1 (L1_input_pos_val, L1_output_pos_val);
+
+parameter layer = 1;
+
+//Input of layer 1, Output from layer 0
+input [31 :0]L1_input_pos_val;
+
+//Output of layer 1, this will be Input to layer 2
+output [23 : 0] L1_output_pos_val;
+
+//Wires
+wire L1_wire_output_val_0, L1_wire_output_val_1, L1_wire_output_val_2, L1_wire_output_val_3, L1_wire_output_val_4, L1_wire_output_val_5, L1_wire_output_val_6, L1_wire_output_val_7;
+wire [layer : 0] L1_wire_output_pos_0, L1_wire_output_pos_1, L1_wire_output_pos_2, L1_wire_output_pos_3, L1_wire_output_pos_4, L1_wire_output_pos_5, L1_wire_output_pos_6, L1_wire_output_pos_7;
+
+
+FPU_LZD_mux L1_0 (.in_val_2(L1_input_pos_val[3]), .in_pos_2(L1_input_pos_val[2]), .in_val_1(L1_input_pos_val[1]), .in_pos_1(L1_input_pos_val[0]), .out_pos(L1_wire_output_pos_0), .out_val(L1_wire_output_val_0)); defparam L1_0.layer = 1;
+FPU_LZD_mux L1_1 (.in_val_2(L1_input_pos_val[7]), .in_pos_2(L1_input_pos_val[6]), .in_val_1(L1_input_pos_val[5]), .in_pos_1(L1_input_pos_val[4]), .out_pos(L1_wire_output_pos_1), .out_val(L1_wire_output_val_1)); defparam L1_1.layer = 1;
+FPU_LZD_mux L1_2 (.in_val_2(L1_input_pos_val[11]), .in_pos_2(L1_input_pos_val[10]), .in_val_1(L1_input_pos_val[9]), .in_pos_1(L1_input_pos_val[8]), .out_pos(L1_wire_output_pos_2), .out_val(L1_wire_output_val_2)); defparam L1_2.layer = 1;
+FPU_LZD_mux L1_3 (.in_val_2(L1_input_pos_val[15]), .in_pos_2(L1_input_pos_val[14]), .in_val_1(L1_input_pos_val[13]), .in_pos_1(L1_input_pos_val[12]), .out_pos(L1_wire_output_pos_3), .out_val(L1_wire_output_val_3)); defparam L1_3.layer = 1;
+FPU_LZD_mux L1_4 (.in_val_2(L1_input_pos_val[19]), .in_pos_2(L1_input_pos_val[18]), .in_val_1(L1_input_pos_val[17]), .in_pos_1(L1_input_pos_val[16]), .out_pos(L1_wire_output_pos_4), .out_val(L1_wire_output_val_4)); defparam L1_4.layer = 1;
+FPU_LZD_mux L1_5 (.in_val_2(L1_input_pos_val[23]), .in_pos_2(L1_input_pos_val[22]), .in_val_1(L1_input_pos_val[21]), .in_pos_1(L1_input_pos_val[20]), .out_pos(L1_wire_output_pos_5), .out_val(L1_wire_output_val_5)); defparam L1_5.layer = 1;
+FPU_LZD_mux L1_6 (.in_val_2(L1_input_pos_val[27]), .in_pos_2(L1_input_pos_val[26]), .in_val_1(L1_input_pos_val[25]), .in_pos_1(L1_input_pos_val[24]), .out_pos(L1_wire_output_pos_6), .out_val(L1_wire_output_val_6)); defparam L1_6.layer = 1;
+FPU_LZD_mux L1_7 (.in_val_2(L1_input_pos_val[31]), .in_pos_2(L1_input_pos_val[30]), .in_val_1(L1_input_pos_val[29]), .in_pos_1(L1_input_pos_val[28]), .out_pos(L1_wire_output_pos_7), .out_val(L1_wire_output_val_7)); defparam L1_7.layer = 1;
+
+assign L1_output_pos_val =
+{
+ L1_wire_output_val_7, L1_wire_output_pos_7,
+ L1_wire_output_val_6, L1_wire_output_pos_6,
+ L1_wire_output_val_5, L1_wire_output_pos_5,
+ L1_wire_output_val_4, L1_wire_output_pos_4,
+ L1_wire_output_val_3, L1_wire_output_pos_3,
+ L1_wire_output_val_2, L1_wire_output_pos_2,
+ L1_wire_output_val_1, L1_wire_output_pos_1,
+ L1_wire_output_val_0, L1_wire_output_pos_0};
+endmodule
diff --git a/verilog/rtl/FPU/LZD_layer2.v b/verilog/rtl/FPU/LZD_layer2.v
new file mode 100644
index 0000000..5cd2c08
--- /dev/null
+++ b/verilog/rtl/FPU/LZD_layer2.v
@@ -0,0 +1,28 @@
+//`include "LZD_mux.v"
+
+module LZD_layer_2 (L2_input_pos_val, L2_output_pos_val);
+
+parameter layer = 2;
+
+//Input of layer 2, Output from layer 1
+input [23 :0]L2_input_pos_val;
+
+//Output of layer 2, this will be Input to layer 3
+output [15 : 0] L2_output_pos_val;
+
+//Wires
+wire L2_wire_output_val_0, L2_wire_output_val_1, L2_wire_output_val_2, L2_wire_output_val_3;
+wire [layer : 0] L2_wire_output_pos_0, L2_wire_output_pos_1, L2_wire_output_pos_2, L2_wire_output_pos_3;
+
+
+FPU_LZD_mux L2_0 (.in_val_2(L2_input_pos_val[5]), .in_pos_2(L2_input_pos_val[4:3]), .in_val_1(L2_input_pos_val[2]), .in_pos_1(L2_input_pos_val[1:0]), .out_pos(L2_wire_output_pos_0), .out_val(L2_wire_output_val_0)); defparam L2_0.layer = 2;
+FPU_LZD_mux L2_1 (.in_val_2(L2_input_pos_val[11]), .in_pos_2(L2_input_pos_val[10:9]), .in_val_1(L2_input_pos_val[8]), .in_pos_1(L2_input_pos_val[7:6]), .out_pos(L2_wire_output_pos_1), .out_val(L2_wire_output_val_1)); defparam L2_1.layer = 2;
+FPU_LZD_mux L2_2 (.in_val_2(L2_input_pos_val[17]), .in_pos_2(L2_input_pos_val[16:15]), .in_val_1(L2_input_pos_val[14]), .in_pos_1(L2_input_pos_val[13:12]), .out_pos(L2_wire_output_pos_2), .out_val(L2_wire_output_val_2)); defparam L2_2.layer = 2;
+FPU_LZD_mux L2_3 (.in_val_2(L2_input_pos_val[23]), .in_pos_2(L2_input_pos_val[22:21]), .in_val_1(L2_input_pos_val[20]), .in_pos_1(L2_input_pos_val[19:18]), .out_pos(L2_wire_output_pos_3), .out_val(L2_wire_output_val_3)); defparam L2_3.layer = 2;
+
+assign L2_output_pos_val =
+{L2_wire_output_val_3, L2_wire_output_pos_3,
+ L2_wire_output_val_2, L2_wire_output_pos_2,
+ L2_wire_output_val_1, L2_wire_output_pos_1,
+ L2_wire_output_val_0, L2_wire_output_pos_0};
+endmodule
diff --git a/verilog/rtl/FPU/LZD_layer3.v b/verilog/rtl/FPU/LZD_layer3.v
new file mode 100644
index 0000000..32bf5e5
--- /dev/null
+++ b/verilog/rtl/FPU/LZD_layer3.v
@@ -0,0 +1,24 @@
+//`include "LZD_mux.v"
+
+module LZD_layer_3 (L3_input_pos_val, L3_output_pos_val);
+
+parameter layer = 3;
+
+//Input of layer 3, Output from layer 2
+input [15 :0]L3_input_pos_val;
+
+//Output of layer 3, this will be Input to layer 4
+output [9 : 0] L3_output_pos_val;
+
+//Wires
+wire L3_wire_output_val_0, L3_wire_output_val_1;
+wire [layer : 0] L3_wire_output_pos_0, L3_wire_output_pos_1;
+
+
+FPU_LZD_mux L3_0 (.in_val_2(L3_input_pos_val[7]), .in_pos_2(L3_input_pos_val[6:4]), .in_val_1(L3_input_pos_val[3]), .in_pos_1(L3_input_pos_val[2:0]), .out_pos(L3_wire_output_pos_0), .out_val(L3_wire_output_val_0)); defparam L3_0.layer = 3;
+FPU_LZD_mux L3_1 (.in_val_2(L3_input_pos_val[15]), .in_pos_2(L3_input_pos_val[14:12]), .in_val_1(L3_input_pos_val[11]), .in_pos_1(L3_input_pos_val[10:8]), .out_pos(L3_wire_output_pos_1), .out_val(L3_wire_output_val_1)); defparam L3_1.layer = 3;
+
+assign L3_output_pos_val =
+{L3_wire_output_val_1, L3_wire_output_pos_1,
+ L3_wire_output_val_0, L3_wire_output_pos_0};
+endmodule
diff --git a/verilog/rtl/FPU/LZD_layer4.v b/verilog/rtl/FPU/LZD_layer4.v
new file mode 100644
index 0000000..911ceac
--- /dev/null
+++ b/verilog/rtl/FPU/LZD_layer4.v
@@ -0,0 +1,23 @@
+//`include "LZD_mux.v"
+
+module LZD_layer_4 (L4_input_pos_val, L4_output_pos, L4_output_valid);
+
+parameter layer = 4;
+
+//Input of layer 4, Output from layer 3
+input [9 :0]L4_input_pos_val;
+
+//Output of layer 4, this will be position of Leading 1
+output [4 : 0] L4_output_pos;
+output L4_output_valid;
+
+//Wires
+wire L4_wire_output_val;
+wire [layer : 0] L4_wire_output_pos;
+
+
+FPU_LZD_mux L4_0 (.in_val_2(L4_input_pos_val[9]), .in_pos_2(L4_input_pos_val[8:5]), .in_val_1(L4_input_pos_val[4]), .in_pos_1(L4_input_pos_val[3:0]), .out_pos(L4_wire_output_pos), .out_val(L4_wire_output_val)); defparam L4_0.layer = 4;
+
+assign L4_output_pos = L4_wire_output_pos;
+assign L4_output_valid = L4_wire_output_val;
+endmodule
diff --git a/verilog/rtl/FPU/LZD_main.v b/verilog/rtl/FPU/LZD_main.v
new file mode 100644
index 0000000..574e976
--- /dev/null
+++ b/verilog/rtl/FPU/LZD_main.v
@@ -0,0 +1,30 @@
+module FPU_I2F_LZD (I2F_LZD_input_int, I2F_LZD_output_pos, I2F_LZD_output_val);
+
+parameter layer = 1;
+
+input [31 : 0]I2F_LZD_input_int;
+
+output [4: 0]I2F_LZD_output_pos;
+output I2F_LZD_output_val;
+
+wire [31 : 0] LZD_wire_output_L0;
+wire [23 : 0] LZD_wire_output_L1;
+wire [15 : 0] LZD_wire_output_L2;
+wire [9 : 0] LZD_wire_output_L3;
+
+//Layer 0
+LZD_layer_0 L0 (.L0_input_int(I2F_LZD_input_int), .L0_output_pos_val(LZD_wire_output_L0));
+
+//Layer 1
+LZD_layer_1 L1 (.L1_input_pos_val(LZD_wire_output_L0), .L1_output_pos_val(LZD_wire_output_L1));
+
+//Layer 2
+LZD_layer_2 L2 (.L2_input_pos_val(LZD_wire_output_L1), .L2_output_pos_val(LZD_wire_output_L2));
+
+//Layer 3
+LZD_layer_3 L3 (.L3_input_pos_val(LZD_wire_output_L2), .L3_output_pos_val(LZD_wire_output_L3));
+
+//Layer 4
+LZD_layer_4 L4 (.L4_input_pos_val(LZD_wire_output_L3), .L4_output_pos(I2F_LZD_output_pos), .L4_output_valid(I2F_LZD_output_val));
+
+endmodule
diff --git a/verilog/rtl/FPU/LZD_mux.v b/verilog/rtl/FPU/LZD_mux.v
new file mode 100644
index 0000000..8673707
--- /dev/null
+++ b/verilog/rtl/FPU/LZD_mux.v
@@ -0,0 +1,17 @@
+module FPU_LZD_mux (in_pos_1, in_val_1, in_pos_2, in_val_2, out_pos, out_val);
+
+//Position of MSB set will be termed as P2
+//Position of LSB set will be termed as P1
+
+parameter layer = 1;
+
+input [layer-1 : 0] in_pos_1, in_pos_2;
+input in_val_1, in_val_2;
+
+output [layer : 0]out_pos;
+output out_val;
+
+assign out_val = in_val_1 | in_val_2;
+assign out_pos = in_val_2 ? {!in_val_2, in_pos_2} : {!in_val_2, in_pos_1} ;
+
+endmodule
diff --git a/verilog/rtl/FPU/Main_Decode.v b/verilog/rtl/FPU/Main_Decode.v
new file mode 100644
index 0000000..5062802
--- /dev/null
+++ b/verilog/rtl/FPU/Main_Decode.v
@@ -0,0 +1,155 @@
+`include "Dec_gpr_ctl.v"
+`include "FPU_CSR.v"
+`include "FPU_decode.v"
+
+
+
+module Main_Decode(clk,rst_l,Instruction,S_flag,Flag_LI,Flag_ADDI,RS1_d,RS2_d,Activation_Signal,result,Flag_Reset,Flag_CSR,Flag_CSR_r,fpu_active,fpu_complete,sfpu_op,fpu_pre,fs1_data,fs2_data,fs3_data,valid_execution,illegal_config,float_control,halt_req,fpu_result_1,fpu_rounding,dec_i0_rs1_en_d,dec_i0_rs2_en_d,fpu_sel);
+
+
+ input clk,rst_l,Activation_Signal,fpu_active,fpu_complete;
+ input [4:0]S_flag;
+ input [31:0]Instruction,result;
+ input [15:0]fpu_result_1;
+ output Flag_ADDI,Flag_LI,Flag_Reset,Flag_CSR,CSR_Write,valid_execution,illegal_config,halt_req,dec_i0_rs1_en_d,dec_i0_rs2_en_d;
+ output [31:0]RS1_d,RS2_d;
+ output [15:0]fs1_data,fs2_data,fs3_data;
+ output reg Flag_CSR_r;
+ output [23:0]sfpu_op;
+ output [2:0]fpu_pre,fpu_rounding,fpu_sel;
+ output [3:0]float_control;
+
+
+ wire [2:0] fpu_rnd,Fpu_Frm;
+ wire [11:0]IMM_ADDI,CSR_Addr;
+ wire [31:0]IMM_LI;
+ reg [4:0]rd,rd_address;
+ wire [4:0]rs1,rs2,rs1_address,rs2_address;
+ //reg [31:0]Instruction_reg;
+ wire [31:0]gpr_rs1,gpr_rs2;
+ wire [2:0] Function_CSR;
+ wire [31:0] CSR_Read_Data,CSR_Write_Data;
+ wire rs1_en,rs2_en;
+ reg [31:0] CSR_Read_Data_r;
+ reg CSR_Read_r;
+ wire CSR_Read;
+ wire [2:0]scalar_control;
+ wire write_en;
+ wire illegal_instr;
+
+ always @(posedge clk)
+ begin
+ /* if (rst_l)
+ Instruction_reg <= Instruction;
+ else
+ Instruction_reg <= 32'h00000000;
+ */
+
+ if (rst_l)
+ begin
+ CSR_Read_Data_r <= CSR_Read_Data;
+ CSR_Read_r <= (CSR_Read & ~fpu_active);
+ Flag_CSR_r <= Flag_CSR;
+ end
+ else
+ begin
+ CSR_Read_Data_r <= 32'h00000000;
+ CSR_Read_r <= 1'b0;
+ Flag_CSR_r <= 1'b0;
+ end
+
+ rd = (~rst_l) ? 5'b00000 : (Instruction[11:7] != 5'b00000) ? Instruction[11:7] : 5'b00000;
+
+ //Flag_ADDI = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b0010011) ? 1'b1 : 1'b0;
+ //Flag_LI = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b0110111) ? 1'b1 : 1'b0;
+ //RS2_d = (~rst_l) ? 32'h00000000 : Flag_LI ? IMM_LI : (Flag_ADDI) ? {{20{IMM_ADDI[11]}},IMM_ADDI} : gpr_rs2;
+ //RS1_d = (~rst_l) ? 32'h00000000 : gpr_rs1;
+
+ end
+
+ dec_gpr_ctl Int_Reg_file(
+ .clk(clk),
+ .rst_l(rst_l),
+ .rden0(rs1_en),
+ .rden1(rs2_en),
+ .raddr0(rs1),
+ .raddr1(rs2),
+ .wen0(write_en),
+ .waddr0(rd),
+ .wd0((CSR_Read_r) ? CSR_Read_Data_r : result),
+ .rd0(gpr_rs1),
+ .rd1(gpr_rs2),
+ .scan_mode(1'b0)
+ );
+
+
+ FPU_CSR CSR(
+ .clk(clk),
+ .rst_l(rst_l),
+ .S_flag(S_flag),
+ .fpu_complete(fpu_complete),
+ .CSR_Read(CSR_Read),
+ .CSR_Write(CSR_Write),
+ .CSR_Addr(CSR_Addr),
+ .CSR_Write_Data(CSR_Write_Data),
+ .CSR_Read_Data(CSR_Read_Data),
+ .fpu_active(fpu_active),
+ .illegal_instr(illegal_instr),
+ .Fpu_Frm(Fpu_Frm)
+ );
+
+ FPU_decode FPU_Decoder(
+ .clk(clk),
+ .rst_l(rst_l),
+ .instr(Instruction),
+ .fpu_active(fpu_active),
+ .fpu_complete(fpu_complete),
+ .fpu_result_1(fpu_result_1),
+ .scalar_control(scalar_control),
+ .rs1_address(rs1_address),
+ .rs2_address(rs2_address),
+ .rd_address(rd_address),
+ .illegal_instr(illegal_instr),
+ .sfpu_op(sfpu_op),
+ .fpu_rnd(fpu_rnd),
+ .fpu_pre(fpu_pre),
+ .fs1_data(fs1_data),
+ .fs2_data(fs2_data),
+ .fs3_data(fs3_data),
+ .valid_execution(valid_execution),
+ .illegal_config(illegal_config),
+ .scan_mode(1'b0),
+ .float_control(float_control),
+ .halt_req(halt_req),
+ .fpu_sel(fpu_sel)
+ );
+
+ // ADDI & LUI instructions ASSIGNEMENTS
+ assign IMM_ADDI = (~rst_l) ? 12'h000 : Instruction[31:20];
+ assign IMM_LI = (~rst_l) ? 32'h00000000 : {Instruction[31:12],12'h000};
+ assign Flag_ADDI = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b0010011) ? 1'b1 : 1'b0;
+ assign Flag_LI = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b0110111) ? 1'b1 : 1'b0;
+ assign Flag_Reset = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b0010000) ? 1'b1 : 1'b0;
+
+
+ // INTEGER REGISTER FILE ASSIGNEMENTS
+ assign rs1_en = (~rst_l) ? 1'b0 : (Instruction[11:7] != 5'b00000) ? 1'b1 : (fpu_active & ~illegal_instr) ? scalar_control[0] : 1'b0;
+ assign rs2_en = (~rst_l) ? 1'b0 : (Instruction[11:7] != 5'b00000) ? 1'b1 : (fpu_active & ~illegal_instr) ? scalar_control[1] : 1'b0;
+ assign rs1 = (~rst_l) ? 5'b00000 : (Flag_ADDI) ? Instruction[19:15] : ((Function_CSR == 3'b001) & Flag_CSR) ? Instruction[19:15] : (fpu_active & ~illegal_instr) ? rs1_address : 5'b00000;
+ assign rs2 = (~rst_l) ? 5'b00000 : (fpu_active & ~illegal_instr) ? rs2_address : 5'b00000;
+ assign RS2_d = (~rst_l) ? 32'h00000000 : Flag_LI ? IMM_LI : (Flag_ADDI) ? {{20{IMM_ADDI[11]}},IMM_ADDI} : gpr_rs2;
+ assign RS1_d = (~rst_l) ? 32'h00000000 : /*(Flag_LI) ? 32'h00000000 :*/ gpr_rs1;
+ assign write_en = (~rst_l) ? 1'b0 : (Activation_Signal | CSR_Read_r) ? 1'b1 : 1'b0;
+
+ // CSRRW & CSRRWI instructions ASSIGNEMENTS
+ assign Flag_CSR = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b1110011) ? 1'b1 : 1'b0;
+ assign Function_CSR = (~rst_l) ? 3'b000 : (Flag_CSR) ? Instruction[14:12] : 3'b000;
+ assign CSR_Addr = (~rst_l) ? 12'h000 : (fpu_active & (~illegal_instr) & (~fpu_complete)) ? 12'h001 : Instruction[31:20];
+ assign CSR_Read = (~rst_l) ? 1'b0 : ((Instruction[11:7] != 5'b00000) & Flag_CSR) ? 1'b1 : (fpu_active & (~illegal_instr) & (~fpu_complete)) ? 1'b1 : 1'b0;
+ assign CSR_Write = (~rst_l) ? 1'b0 : (Flag_CSR) ? 1'b1 : (fpu_active & (~illegal_instr) & fpu_complete) ? 1'b1 : 1'b0;
+ assign CSR_Write_Data = (~rst_l) ? 32'h00000000 : (Flag_CSR & (Function_CSR == 3'b101)) ? {27'h0000000,Instruction[19:15]} : RS1_d;
+ assign fpu_rounding = (~rst_l) ? 3'b000 : (fpu_active & (~illegal_instr) & (fpu_rnd==3'b111)) ? Fpu_Frm : (fpu_active & (~illegal_instr) & (fpu_rnd!=3'b111)) ? fpu_rnd : 3'b000;
+ assign dec_i0_rs1_en_d = (~rst_l) ? 1'b0 : rs1_en;
+ assign dec_i0_rs2_en_d = (~rst_l) ? 1'b0 : rs2_en;
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/Sky130_SRAM_1kbyte_Memory.v b/verilog/rtl/FPU/Sky130_SRAM_1kbyte_Memory.v
new file mode 100644
index 0000000..e4c4aa0
--- /dev/null
+++ b/verilog/rtl/FPU/Sky130_SRAM_1kbyte_Memory.v
@@ -0,0 +1,114 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sky130_sram_1kbyte_1rw1r_32x256_8(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+ clk1,csb1,addr1,dout1
+ );
+
+ parameter NUM_WMASKS = 4 ;
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 8 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 0 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 0 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [NUM_WMASKS-1:0] wmask0; // write mask
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+ input clk1; // clock
+ input csb1; // active low chip select
+ input [ADDR_WIDTH-1:0] addr1;
+ output [DATA_WIDTH-1:0] dout1;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [NUM_WMASKS-1:0] wmask0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ wmask0_reg = wmask0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ //#(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+ end
+
+ reg csb1_reg;
+ reg [ADDR_WIDTH-1:0] addr1_reg;
+ reg [DATA_WIDTH-1:0] dout1;
+
+ // All inputs are registers
+ always @(posedge clk1)
+ begin
+ csb1_reg = csb1;
+ addr1_reg = addr1;
+ if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+ $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+ // #(T_HOLD) dout1 = 32'bx;
+ if ( !csb1_reg && VERBOSE )
+ $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ if (wmask0_reg[0])
+ mem[addr0_reg][7:0] = din0_reg[7:0];
+ if (wmask0_reg[1])
+ mem[addr0_reg][15:8] = din0_reg[15:8];
+ if (wmask0_reg[2])
+ mem[addr0_reg][23:16] = din0_reg[23:16];
+ if (wmask0_reg[3])
+ mem[addr0_reg][31:24] = din0_reg[31:24];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+ // Memory Read Block Port 1
+ // Read Operation : When web1 = 1, csb1 = 0
+ always @ (negedge clk1)
+ begin : MEM_READ1
+ if (!csb1_reg)
+ dout1 <= #(DELAY) mem[addr1_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/FPU/beh_lib.v b/verilog/rtl/FPU/beh_lib.v
new file mode 100644
index 0000000..32a2894
--- /dev/null
+++ b/verilog/rtl/FPU/beh_lib.v
@@ -0,0 +1,710 @@
+module rvdff (
+ din,
+ clk,
+ rst_l,
+ dout
+);
+ parameter WIDTH = 1;
+ parameter SHORT = 0;
+ input wire [WIDTH - 1:0] din;
+ input wire clk;
+ input wire rst_l;
+ output reg [WIDTH - 1:0] dout;
+ generate
+ if (SHORT == 1) begin
+ wire [WIDTH:1] sv2v_tmp_70387;
+ assign sv2v_tmp_70387 = din;
+ always @(*) dout = sv2v_tmp_70387;
+ end
+ else always @(posedge clk or negedge rst_l)
+ if (rst_l == 0)
+ dout[WIDTH - 1:0] <= 0;
+ else
+ dout[WIDTH - 1:0] <= din[WIDTH - 1:0];
+ endgenerate
+endmodule
+module rvdffs (
+ din,
+ en,
+ clk,
+ rst_l,
+ dout
+);
+ parameter WIDTH = 1;
+ parameter SHORT = 0;
+ input wire [WIDTH - 1:0] din;
+ input wire en;
+ input wire clk;
+ input wire rst_l;
+ output wire [WIDTH - 1:0] dout;
+ generate
+ if (SHORT == 1) begin : genblock
+ assign dout = din;
+ end
+ else begin : genblock
+ rvdff #(WIDTH) dffs(
+ .din((en ? din[WIDTH - 1:0] : dout[WIDTH - 1:0])),
+ .clk(clk),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ end
+ endgenerate
+endmodule
+module rvdffsc (
+ din,
+ en,
+ clear,
+ clk,
+ rst_l,
+ dout
+);
+ parameter WIDTH = 1;
+ parameter SHORT = 0;
+ input wire [WIDTH - 1:0] din;
+ input wire en;
+ input wire clear;
+ input wire clk;
+ input wire rst_l;
+ output wire [WIDTH - 1:0] dout;
+ wire [WIDTH - 1:0] din_new;
+ generate
+ if (SHORT == 1) begin
+ assign dout = din;
+ end
+ else begin
+ assign din_new = {WIDTH {~clear}} & (en ? din[WIDTH - 1:0] : dout[WIDTH - 1:0]);
+ rvdff #(WIDTH) dffsc(
+ .din(din_new[WIDTH - 1:0]),
+ .clk(clk),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ end
+ endgenerate
+endmodule
+module rvdff_fpga (
+ din,
+ clk,
+ clken,
+ rawclk,
+ rst_l,
+ dout
+);
+ parameter WIDTH = 1;
+ parameter SHORT = 0;
+ input wire [WIDTH - 1:0] din;
+ input wire clk;
+ input wire clken;
+ input wire rawclk;
+ input wire rst_l;
+ output wire [WIDTH - 1:0] dout;
+ generate
+ if (SHORT == 1) begin
+ assign dout = din;
+ end
+ else rvdffs #(WIDTH) dffs(
+ .clk(rawclk),
+ .en(clken),
+ .din(din),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ endgenerate
+endmodule
+module rvdffs_fpga (
+ din,
+ en,
+ clk,
+ clken,
+ rawclk,
+ rst_l,
+ dout
+);
+ parameter WIDTH = 1;
+ parameter SHORT = 0;
+ input wire [WIDTH - 1:0] din;
+ input wire en;
+ input wire clk;
+ input wire clken;
+ input wire rawclk;
+ input wire rst_l;
+ output wire [WIDTH - 1:0] dout;
+ generate
+ if (SHORT == 1) begin : genblock
+ assign dout = din;
+ end
+ else begin : genblock
+ rvdffs #(WIDTH) dffs(
+ .clk(rawclk),
+ .en(clken & en),
+ .din(din),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ end
+ endgenerate
+endmodule
+module rvdffsc_fpga (
+ din,
+ en,
+ clear,
+ clk,
+ clken,
+ rawclk,
+ rst_l,
+ dout
+);
+ parameter WIDTH = 1;
+ parameter SHORT = 0;
+ input wire [WIDTH - 1:0] din;
+ input wire en;
+ input wire clear;
+ input wire clk;
+ input wire clken;
+ input wire rawclk;
+ input wire rst_l;
+ output wire [WIDTH - 1:0] dout;
+ wire [WIDTH - 1:0] din_new;
+ generate
+ if (SHORT == 1) begin
+ assign dout = din;
+ end
+ else rvdffs #(WIDTH) dffs(
+ .clk(rawclk),
+ .din(din[WIDTH - 1:0] & {WIDTH {~clear}}),
+ .en((en | clear) & clken),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ endgenerate
+endmodule
+module rvdffe (
+ din,
+ en,
+ clk,
+ rst_l,
+ scan_mode,
+ dout
+);
+ parameter WIDTH = 1;
+ parameter SHORT = 0;
+ parameter OVERRIDE = 0;
+ input wire [WIDTH - 1:0] din;
+ input wire en;
+ input wire clk;
+ input wire rst_l;
+ input wire scan_mode;
+ output wire [WIDTH - 1:0] dout;
+ wire l1clk;
+ generate
+ if (SHORT == 1) begin
+ assign dout = din;
+ end
+ else begin
+ if ((WIDTH >= 8) || (OVERRIDE == 1)) begin
+ rvdffs #(WIDTH) dff(
+ .din(din),
+ .en(en),
+ .clk(clk),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ end
+ end
+ endgenerate
+endmodule
+module rvdffpcie (
+ din,
+ clk,
+ rst_l,
+ en,
+ scan_mode,
+ dout
+);
+ parameter WIDTH = 31;
+ input wire [WIDTH - 1:0] din;
+ input wire clk;
+ input wire rst_l;
+ input wire en;
+ input wire scan_mode;
+ output wire [WIDTH - 1:0] dout;
+ generate
+ if (WIDTH == 31) begin : genblock
+ rvdffs #(WIDTH) dff(
+ .din(din),
+ .en(en),
+ .clk(clk),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ end
+ endgenerate
+endmodule
+module rvdfflie (
+ din,
+ clk,
+ rst_l,
+ en,
+ scan_mode,
+ dout
+);
+ parameter WIDTH = 16;
+ parameter LEFT = 8;
+ input wire [WIDTH - 1:0] din;
+ input wire clk;
+ input wire rst_l;
+ input wire en;
+ input wire scan_mode;
+ output wire [WIDTH - 1:0] dout;
+ localparam EXTRA = WIDTH - LEFT;
+ localparam LMSB = WIDTH - 1;
+ localparam LLSB = (LMSB - LEFT) + 1;
+ localparam XMSB = LLSB - 1;
+ localparam XLSB = LLSB - EXTRA;
+ generate
+ if (((WIDTH >= 16) && (LEFT >= 8)) && (EXTRA >= 8)) begin : genblock
+ rvdffs #(WIDTH) dff(
+ .din(din),
+ .en(en),
+ .clk(clk),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ end
+ endgenerate
+endmodule
+module rvdffppe (
+ din,
+ clk,
+ rst_l,
+ en,
+ scan_mode,
+ dout
+);
+ parameter WIDTH = 32;
+ input wire [WIDTH - 1:0] din;
+ input wire clk;
+ input wire rst_l;
+ input wire en;
+ input wire scan_mode;
+ output wire [WIDTH - 1:0] dout;
+ localparam RIGHT = 31;
+ localparam LEFT = WIDTH - RIGHT;
+ localparam LMSB = WIDTH - 1;
+ localparam LLSB = (LMSB - LEFT) + 1;
+ localparam RMSB = LLSB - 1;
+ localparam RLSB = LLSB - RIGHT;
+ generate
+ if (((WIDTH >= 32) && (LEFT >= 8)) && 1'd1) begin : genblock
+ rvdffs #(WIDTH) dff(
+ .din(din),
+ .en(en),
+ .clk(clk),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ end
+ endgenerate
+endmodule
+module rvdffie (
+ din,
+ clk,
+ rst_l,
+ scan_mode,
+ dout
+);
+ parameter WIDTH = 1;
+ parameter OVERRIDE = 0;
+ input wire [WIDTH - 1:0] din;
+ input wire clk;
+ input wire rst_l;
+ input wire scan_mode;
+ output wire [WIDTH - 1:0] dout;
+ wire l1clk;
+ wire en;
+ generate
+ if ((WIDTH >= 8) || (OVERRIDE == 1)) begin : genblock
+ assign en = |(din ^ dout);
+ rvdffs #(WIDTH) dff(
+ .din(din),
+ .en(en),
+ .clk(clk),
+ .rst_l(rst_l),
+ .dout(dout)
+ );
+ end
+ endgenerate
+endmodule
+module rvdffiee (
+ din,
+ clk,
+ rst_l,
+ scan_mode,
+ en,
+ dout
+);
+ parameter WIDTH = 1;
+ parameter OVERRIDE = 0;
+ input wire [WIDTH - 1:0] din;
+ input wire clk;
+ input wire rst_l;
+ input wire scan_mode;
+ input wire en;
+ output wire [WIDTH - 1:0] dout;
+ wire l1clk;
+ wire final_en;
+ generate
+ if ((WIDTH >= 8) || (OVERRIDE == 1)) begin : genblock
+ assign final_en = |(din ^ dout) & en;
+ rvdffs #(WIDTH) dff(
+ .din(din),
+ .clk(clk),
+ .rst_l(rst_l),
+ .dout(dout),
+ .en(final_en)
+ );
+ end
+ endgenerate
+endmodule
+module rvsyncss (
+ clk,
+ rst_l,
+ din,
+ dout
+);
+ parameter WIDTH = 251;
+ input wire clk;
+ input wire rst_l;
+ input wire [WIDTH - 1:0] din;
+ output wire [WIDTH - 1:0] dout;
+ wire [WIDTH - 1:0] din_ff1;
+ rvdff #(WIDTH) sync_ff1(
+ .clk(clk),
+ .rst_l(rst_l),
+ .din(din[WIDTH - 1:0]),
+ .dout(din_ff1[WIDTH - 1:0])
+ );
+ rvdff #(WIDTH) sync_ff2(
+ .clk(clk),
+ .rst_l(rst_l),
+ .din(din_ff1[WIDTH - 1:0]),
+ .dout(dout[WIDTH - 1:0])
+ );
+endmodule
+module rvsyncss_fpga (
+ gw_clk,
+ rawclk,
+ clken,
+ rst_l,
+ din,
+ dout
+);
+ parameter WIDTH = 251;
+ input wire gw_clk;
+ input wire rawclk;
+ input wire clken;
+ input wire rst_l;
+ input wire [WIDTH - 1:0] din;
+ output wire [WIDTH - 1:0] dout;
+ wire [WIDTH - 1:0] din_ff1;
+ rvdff_fpga #(WIDTH) sync_ff1(
+ .rst_l(rst_l),
+ .clk(gw_clk),
+ .rawclk(rawclk),
+ .clken(clken),
+ .din(din[WIDTH - 1:0]),
+ .dout(din_ff1[WIDTH - 1:0])
+ );
+ rvdff_fpga #(WIDTH) sync_ff2(
+ .rst_l(rst_l),
+ .clk(gw_clk),
+ .rawclk(rawclk),
+ .clken(clken),
+ .din(din_ff1[WIDTH - 1:0]),
+ .dout(dout[WIDTH - 1:0])
+ );
+endmodule
+module rvlsadder (
+ rs1,
+ offset,
+ dout
+);
+ input wire [31:0] rs1;
+ input wire [11:0] offset;
+ output wire [31:0] dout;
+ wire cout;
+ wire sign;
+ wire [31:12] rs1_inc;
+ wire [31:12] rs1_dec;
+ assign {cout, dout[11:0]} = {1'b0, rs1[11:0]} + {1'b0, offset[11:0]};
+ assign rs1_inc[31:12] = rs1[31:12] + 1;
+ assign rs1_dec[31:12] = rs1[31:12] - 1;
+ assign sign = offset[11];
+ assign dout[31:12] = (({20 {sign ~^ cout}} & rs1[31:12]) | ({20 {~sign & cout}} & rs1_inc[31:12])) | ({20 {sign & ~cout}} & rs1_dec[31:12]);
+endmodule
+module rvbradder (
+ pc,
+ offset,
+ dout
+);
+ input [31:1] pc;
+ input [12:1] offset;
+ output [31:1] dout;
+ wire cout;
+ wire sign;
+ wire [31:13] pc_inc;
+ wire [31:13] pc_dec;
+ assign {cout, dout[12:1]} = {1'b0, pc[12:1]} + {1'b0, offset[12:1]};
+ assign pc_inc[31:13] = pc[31:13] + 1;
+ assign pc_dec[31:13] = pc[31:13] - 1;
+ assign sign = offset[12];
+ assign dout[31:13] = (({19 {sign ~^ cout}} & pc[31:13]) | ({19 {~sign & cout}} & pc_inc[31:13])) | ({19 {sign & ~cout}} & pc_dec[31:13]);
+endmodule
+module rvtwoscomp (
+ din,
+ dout
+);
+ parameter WIDTH = 32;
+ input wire [WIDTH - 1:0] din;
+ output wire [WIDTH - 1:0] dout;
+ wire [WIDTH - 1:1] dout_temp;
+ genvar i;
+ generate
+ for (i = 1; i < WIDTH; i = i + 1) begin : flip_after_first_one
+ assign dout_temp[i] = (|din[i - 1:0] ? ~din[i] : din[i]);
+ end
+ endgenerate
+ assign dout[WIDTH - 1:0] = {dout_temp[WIDTH - 1:1], din[0]};
+endmodule
+module rvfindfirst1 (
+ din,
+ dout
+);
+ parameter WIDTH = 32;
+ parameter SHIFT = $clog2(WIDTH);
+ input wire [WIDTH - 1:0] din;
+ output reg [SHIFT - 1:0] dout;
+ reg done;
+ always @(*) begin
+ dout[SHIFT - 1:0] = {SHIFT {1'b0}};
+ done = 1'b0;
+ begin : sv2v_autoblock_2
+ reg signed [31:0] i;
+ for (i = WIDTH - 1; i > 0; i = i - 1)
+ begin : find_first_one
+ done = done | din[i];
+ dout[SHIFT - 1:0] = dout[SHIFT - 1:0] + (done ? 1'b0 : 1'b1);
+ end
+ end
+ end
+endmodule
+module rvfindfirst1hot (
+ din,
+ dout
+);
+ parameter WIDTH = 32;
+ input wire [WIDTH - 1:0] din;
+ output reg [WIDTH - 1:0] dout;
+ reg done;
+ always @(*) begin
+ dout[WIDTH - 1:0] = {WIDTH {1'b0}};
+ done = 1'b0;
+ begin : sv2v_autoblock_3
+ reg signed [31:0] i;
+ for (i = 0; i < WIDTH; i = i + 1)
+ begin : find_first_one
+ dout[i] = ~done & din[i];
+ done = done | din[i];
+ end
+ end
+ end
+endmodule
+module rvmaskandmatch (
+ mask,
+ data,
+ masken,
+ match
+);
+ parameter WIDTH = 32;
+ input wire [WIDTH - 1:0] mask;
+ input wire [WIDTH - 1:0] data;
+ input wire masken;
+ output wire match;
+ wire [WIDTH - 1:0] matchvec;
+ wire masken_or_fullmask;
+ assign masken_or_fullmask = masken & ~(&mask[WIDTH - 1:0]);
+ assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);
+ genvar i;
+ generate
+ for (i = 1; i < WIDTH; i = i + 1) begin : match_after_first_zero
+ assign matchvec[i] = (&mask[i - 1:0] & masken_or_fullmask ? 1'b1 : mask[i] == data[i]);
+ end
+ endgenerate
+ assign match = &matchvec[WIDTH - 1:0];
+endmodule
+module rvrangecheck (
+ addr,
+ in_range,
+ in_region
+);
+ parameter CCM_SADR = 32'h00000000;
+ parameter CCM_SIZE = 128;
+ input wire [31:0] addr;
+ output wire in_range;
+ output wire in_region;
+ localparam REGION_BITS = 4;
+ localparam MASK_BITS = 10 + $clog2(CCM_SIZE);
+ wire [31:0] start_addr;
+ wire [3:0] region;
+ assign start_addr[31:0] = CCM_SADR;
+ assign region[3:0] = start_addr[31:28];
+ assign in_region = addr[31:28] == region[3:0];
+ generate
+ if (CCM_SIZE == 48) begin
+ assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS - 1:MASK_BITS - 2]);
+ end
+ else assign in_range = addr[31:MASK_BITS] == start_addr[31:MASK_BITS];
+ endgenerate
+endmodule
+module rveven_paritygen (
+ data_in,
+ parity_out
+);
+ parameter WIDTH = 16;
+ input wire [WIDTH - 1:0] data_in;
+ output wire parity_out;
+ assign parity_out = ^data_in[WIDTH - 1:0];
+endmodule
+module rveven_paritycheck (
+ data_in,
+ parity_in,
+ parity_err
+);
+ parameter WIDTH = 16;
+ input wire [WIDTH - 1:0] data_in;
+ input wire parity_in;
+ output wire parity_err;
+ assign parity_err = ^data_in[WIDTH - 1:0] ^ parity_in;
+endmodule
+module rvecc_encode (
+ din,
+ ecc_out
+);
+ input [31:0] din;
+ output [6:0] ecc_out;
+ wire [5:0] ecc_out_temp;
+ assign ecc_out_temp[0] = ((((((((((((((((din[0] ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30];
+ assign ecc_out_temp[1] = ((((((((((((((((din[0] ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31];
+ assign ecc_out_temp[2] = ((((((((((((((((din[1] ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31];
+ assign ecc_out_temp[3] = (((((((((((((din[4] ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
+ assign ecc_out_temp[4] = (((((((((((((din[11] ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
+ assign ecc_out_temp[5] = ((((din[26] ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31];
+ assign ecc_out[6:0] = {^din[31:0] ^ ^ecc_out_temp[5:0], ecc_out_temp[5:0]};
+endmodule
+module rvecc_decode (
+ en,
+ din,
+ ecc_in,
+ sed_ded,
+ dout,
+ ecc_out,
+ single_ecc_error,
+ double_ecc_error
+);
+ input en;
+ input [31:0] din;
+ input [6:0] ecc_in;
+ input sed_ded;
+ output [31:0] dout;
+ output [6:0] ecc_out;
+ output single_ecc_error;
+ output double_ecc_error;
+ wire [6:0] ecc_check;
+ wire [38:0] error_mask;
+ wire [38:0] din_plus_parity;
+ wire [38:0] dout_plus_parity;
+ assign ecc_check[0] = (((((((((((((((((ecc_in[0] ^ din[0]) ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30];
+ assign ecc_check[1] = (((((((((((((((((ecc_in[1] ^ din[0]) ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31];
+ assign ecc_check[2] = (((((((((((((((((ecc_in[2] ^ din[1]) ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31];
+ assign ecc_check[3] = ((((((((((((((ecc_in[3] ^ din[4]) ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
+ assign ecc_check[4] = ((((((((((((((ecc_in[4] ^ din[11]) ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
+ assign ecc_check[5] = (((((ecc_in[5] ^ din[26]) ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31];
+ assign ecc_check[6] = (^din[31:0] ^ ^ecc_in[6:0]) & ~sed_ded;
+ assign single_ecc_error = (en & (ecc_check[6:0] != 0)) & ecc_check[6];
+ assign double_ecc_error = (en & (ecc_check[6:0] != 0)) & ~ecc_check[6];
+ generate
+ genvar i;
+ for (i = 1; i < 40; i = i + 1) assign error_mask[i - 1] = ecc_check[5:0] == i;
+ endgenerate
+ assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]};
+ assign dout_plus_parity[38:0] = (single_ecc_error ? error_mask[38:0] ^ din_plus_parity[38:0] : din_plus_parity[38:0]);
+ assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]};
+ assign ecc_out[6:0] = {dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]};
+endmodule
+module rvecc_encode_64 (
+ din,
+ ecc_out
+);
+ input [63:0] din;
+ output [6:0] ecc_out;
+ assign ecc_out[0] = (((((((((((((((((((((((((((((((((din[0] ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30]) ^ din[32]) ^ din[34]) ^ din[36]) ^ din[38]) ^ din[40]) ^ din[42]) ^ din[44]) ^ din[46]) ^ din[48]) ^ din[50]) ^ din[52]) ^ din[54]) ^ din[56]) ^ din[57]) ^ din[59]) ^ din[61]) ^ din[63];
+ assign ecc_out[1] = (((((((((((((((((((((((((((((((((din[0] ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31]) ^ din[32]) ^ din[35]) ^ din[36]) ^ din[39]) ^ din[40]) ^ din[43]) ^ din[44]) ^ din[47]) ^ din[48]) ^ din[51]) ^ din[52]) ^ din[55]) ^ din[56]) ^ din[58]) ^ din[59]) ^ din[62]) ^ din[63];
+ assign ecc_out[2] = (((((((((((((((((((((((((((((((((din[1] ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
+ assign ecc_out[3] = (((((((((((((((((((((((((((((din[4] ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+ assign ecc_out[4] = (((((((((((((((((((((((((((((din[11] ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+ assign ecc_out[5] = (((((((((((((((((((((((((((((din[26] ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+ assign ecc_out[6] = (((((din[57] ^ din[58]) ^ din[59]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
+endmodule
+module rvecc_decode_64 (
+ en,
+ din,
+ ecc_in,
+ ecc_error
+);
+ input en;
+ input [63:0] din;
+ input [6:0] ecc_in;
+ output ecc_error;
+ wire [6:0] ecc_check;
+ assign ecc_check[0] = ((((((((((((((((((((((((((((((((((ecc_in[0] ^ din[0]) ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30]) ^ din[32]) ^ din[34]) ^ din[36]) ^ din[38]) ^ din[40]) ^ din[42]) ^ din[44]) ^ din[46]) ^ din[48]) ^ din[50]) ^ din[52]) ^ din[54]) ^ din[56]) ^ din[57]) ^ din[59]) ^ din[61]) ^ din[63];
+ assign ecc_check[1] = ((((((((((((((((((((((((((((((((((ecc_in[1] ^ din[0]) ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31]) ^ din[32]) ^ din[35]) ^ din[36]) ^ din[39]) ^ din[40]) ^ din[43]) ^ din[44]) ^ din[47]) ^ din[48]) ^ din[51]) ^ din[52]) ^ din[55]) ^ din[56]) ^ din[58]) ^ din[59]) ^ din[62]) ^ din[63];
+ assign ecc_check[2] = ((((((((((((((((((((((((((((((((((ecc_in[2] ^ din[1]) ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
+ assign ecc_check[3] = ((((((((((((((((((((((((((((((ecc_in[3] ^ din[4]) ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+ assign ecc_check[4] = ((((((((((((((((((((((((((((((ecc_in[4] ^ din[11]) ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+ assign ecc_check[5] = ((((((((((((((((((((((((((((((ecc_in[5] ^ din[26]) ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
+ assign ecc_check[6] = ((((((ecc_in[6] ^ din[57]) ^ din[58]) ^ din[59]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
+ assign ecc_error = en & (ecc_check[6:0] != 0);
+endmodule
+module clockhdr (
+ SE,
+ EN,
+ CK,
+ Q
+);
+ input wire SE;
+ input wire EN;
+ input wire CK;
+ output Q;
+ reg en_ff;
+ wire enable;
+ assign enable = EN | SE;
+ always @(CK or enable)
+ if (!CK)
+ en_ff = enable;
+ assign Q = CK & en_ff;
+endmodule
+module rvoclkhdr (
+ en,
+ clk,
+ scan_mode,
+ l1clk
+);
+ input wire en;
+ input wire clk;
+ input wire scan_mode;
+ output wire l1clk;
+ wire SE;
+ assign SE = 0;
+ assign l1clk = clk;
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/FPU/iccm_controller.v b/verilog/rtl/FPU/iccm_controller.v
new file mode 100644
index 0000000..611396f
--- /dev/null
+++ b/verilog/rtl/FPU/iccm_controller.v
@@ -0,0 +1,120 @@
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module eb1_iccm_controller (
+ clk_i,
+ rst_ni,
+ rx_dv_i,
+ rx_byte_i,
+ we_o,
+ addr_o,
+ wdata_o,
+ reset_o
+);
+ input wire clk_i;
+ input wire rst_ni;
+ input wire rx_dv_i;
+ input wire [7:0] rx_byte_i;
+ output wire we_o;
+ output wire [13:0] addr_o;
+ output wire [31:0] wdata_o;
+ output wire reset_o;
+ reg [1:0] ctrl_fsm_cs;
+ reg [1:0] ctrl_fsm_ns;
+ wire [7:0] rx_byte_d;
+ reg [7:0] rx_byte_q0;
+ reg [7:0] rx_byte_q1;
+ reg [7:0] rx_byte_q2;
+ reg [7:0] rx_byte_q3;
+ reg we_q;
+ reg we_d;
+ reg [13:0] addr_q;
+ reg [13:0] addr_d;
+ reg reset_q;
+ reg reset_d;
+ reg [1:0] byte_count;
+ localparam [1:0] DONE = 3;
+ localparam [1:0] LOAD = 1;
+ localparam [1:0] PROG = 2;
+ localparam [1:0] RESET = 0;
+ always @(*) begin
+ we_d = we_q;
+ addr_d = addr_q;
+ reset_d = reset_q;
+ ctrl_fsm_ns = ctrl_fsm_cs;
+ case (ctrl_fsm_cs)
+ RESET: begin
+ we_d = 1'b0;
+ reset_d = 1'b0;
+ if (rx_dv_i)
+ ctrl_fsm_ns = LOAD;
+ else
+ ctrl_fsm_ns = RESET;
+ end
+ LOAD:
+ if (((byte_count == 2'b11) && (rx_byte_q2 != 8'h0f)) && (rx_byte_d != 8'hff)) begin
+ we_d = 1'b1;
+ ctrl_fsm_ns = PROG;
+ end
+ else
+ ctrl_fsm_ns = DONE;
+ PROG: begin
+ we_d = 1'b0;
+ ctrl_fsm_ns = DONE;
+ end
+ DONE:
+ if (wdata_o == 32'h00000fff) begin
+ ctrl_fsm_ns = DONE;
+ reset_d = 1'b1;
+ end
+ else if (rx_dv_i)
+ ctrl_fsm_ns = LOAD;
+ else
+ ctrl_fsm_ns = DONE;
+ default: ctrl_fsm_ns = RESET;
+ endcase
+ end
+ assign rx_byte_d = rx_byte_i;
+ assign we_o = we_q;
+ assign addr_o = addr_q;
+ assign wdata_o = {rx_byte_q0, rx_byte_q1, rx_byte_q2, rx_byte_q3};
+ assign reset_o = reset_q;
+ always @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ we_q <= 1'b0;
+ addr_q <= 13'b0000000000000;
+ rx_byte_q0 <= 8'b00000000;
+ rx_byte_q1 <= 8'b00000000;
+ rx_byte_q2 <= 8'b00000000;
+ rx_byte_q3 <= 8'b00000000;
+ reset_q <= 1'b0;
+ byte_count <= 2'b00;
+ ctrl_fsm_cs <= RESET;
+ end
+ else begin
+ we_q <= we_d;
+ if (ctrl_fsm_cs == LOAD) begin
+ if (byte_count == 2'b00) begin
+ rx_byte_q0 <= rx_byte_d;
+ byte_count <= 2'b01;
+ end
+ else if (byte_count == 2'b01) begin
+ rx_byte_q1 <= rx_byte_d;
+ byte_count <= 2'b10;
+ end
+ else if (byte_count == 2'b10) begin
+ rx_byte_q2 <= rx_byte_d;
+ byte_count <= 2'b11;
+ end
+ else begin
+ rx_byte_q3 <= rx_byte_d;
+ byte_count <= 2'b00;
+ end
+ addr_q <= addr_d;
+ end
+ if (ctrl_fsm_cs == PROG)
+ addr_q <= addr_d + 2'h2;
+ reset_q <= reset_d;
+ ctrl_fsm_cs <= ctrl_fsm_ns;
+ end
+endmodule
diff --git a/verilog/rtl/FPU/inst_checker.v b/verilog/rtl/FPU/inst_checker.v
new file mode 100644
index 0000000..788c9a5
--- /dev/null
+++ b/verilog/rtl/FPU/inst_checker.v
@@ -0,0 +1,37 @@
+module Inst_check(
+ input clk,
+ input rst_l,
+ input [6:0] inst_opcode,
+ input fpu_complete,
+ input halt_req,
+ output stall_scalar,
+ output fpu_active
+);
+
+ localparam FPU_X_RANDOM = 7'h53;
+ localparam FPU_X_FADD = 7'h43;
+ localparam FPU_X_FSUB = 7'h47;
+ localparam FPU_X_FNADD = 7'h4F;
+ localparam FPU_X_FNSUB = 7'h4B;
+ reg halt;
+
+assign stall_scalar = (rst_l == 1'b0) ? 1'b0 : (halt_req | halt) ? stall_scalar : 1'b0;
+
+assign fpu_active = (rst_l == 1'b0) ? 1'b0 : ((inst_opcode == FPU_X_RANDOM | inst_opcode == FPU_X_FADD | inst_opcode == FPU_X_FSUB | inst_opcode == FPU_X_FNADD | inst_opcode == FPU_X_FNSUB)) ? 1'b1 : (halt) ? fpu_active : 1'b0;
+
+always @(posedge clk) begin
+ if(rst_l == 1'b0) begin
+ halt <= 1'b0;
+ end
+ else if(halt_req) begin
+ halt <= 1'b1;
+ end
+ else if(fpu_complete) begin
+ halt <= 1'b0;
+ end
+ else begin
+ halt <= halt;
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/FPU/uart_rx_prog.v b/verilog/rtl/FPU/uart_rx_prog.v
new file mode 100644
index 0000000..7af5031
--- /dev/null
+++ b/verilog/rtl/FPU/uart_rx_prog.v
@@ -0,0 +1,151 @@
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module eb1_uart_rx_prog (
+ input i_Clock,
+ input rst_ni,
+ input i_Rx_Serial,
+ input [15:0] CLKS_PER_BIT,
+ output o_Rx_DV,
+ output [7:0] o_Rx_Byte
+ );
+
+ parameter s_IDLE = 3'b000;
+ parameter s_RX_START_BIT = 3'b001;
+ parameter s_RX_DATA_BITS = 3'b010;
+ parameter s_RX_STOP_BIT = 3'b011;
+ parameter s_CLEANUP = 3'b100;
+
+ reg r_Rx_Data_R;
+ reg r_Rx_Data;
+
+ reg [15:0] r_Clock_Count;
+ reg [2:0] r_Bit_Index; //8 bits total
+ reg [7:0] r_Rx_Byte;
+ reg r_Rx_DV;
+ reg [2:0] r_SM_Main;
+
+ // Purpose: Double-register the incoming data.
+ // This allows it to be used in the UART RX Clock Domain.
+ // (It removes problems caused by metastability)
+ always @(posedge i_Clock)
+ if(rst_ni == 1'b0) begin
+ r_Rx_Data_R <= 1'b1;
+ r_Rx_Data <= 1'b1;
+ end
+ else begin
+ r_Rx_Data_R <= i_Rx_Serial;
+ r_Rx_Data <= r_Rx_Data_R;
+ end
+
+
+ // Purpose: Control RX state machine
+ always @(posedge i_Clock or negedge rst_ni)
+ begin
+ if (rst_ni == 1'b0) begin
+ r_SM_Main <= s_IDLE;
+ r_Rx_DV <= 1'b0;
+ r_Clock_Count <= 16'h0000;
+ r_Bit_Index <= 3'b000;
+ r_Rx_Byte <= 8'h00;
+ end else begin
+ case (r_SM_Main)
+ s_IDLE :
+ begin
+ r_Rx_DV <= 1'b0;
+ r_Clock_Count <= 0;
+ r_Bit_Index <= 0;
+
+ if (r_Rx_Data == 1'b0) // Start bit detected
+ r_SM_Main <= s_RX_START_BIT;
+ else
+ r_SM_Main <= s_IDLE;
+ end
+
+ // Check middle of start bit to make sure it's still low
+ s_RX_START_BIT :
+ begin
+ if (r_Clock_Count == ((CLKS_PER_BIT-1)>>1))
+ begin
+ if (r_Rx_Data == 1'b0)
+ begin
+ r_Clock_Count <= 0; // reset counter, found the middle
+ r_SM_Main <= s_RX_DATA_BITS;
+ end
+ else
+ r_SM_Main <= s_IDLE;
+ end
+ else
+ begin
+ r_Clock_Count <= r_Clock_Count + 1;
+ r_SM_Main <= s_RX_START_BIT;
+ end
+ end // case: s_RX_START_BIT
+
+
+ // Wait CLKS_PER_BIT-1 clock cycles to sample serial data
+ s_RX_DATA_BITS :
+ begin
+ if (r_Clock_Count < CLKS_PER_BIT-1)
+ begin
+ r_Clock_Count <= r_Clock_Count + 1;
+ r_SM_Main <= s_RX_DATA_BITS;
+ end
+ else
+ begin
+ r_Clock_Count <= 0;
+ r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
+
+ // Check if we have received all bits
+ if (r_Bit_Index < 7)
+ begin
+ r_Bit_Index <= r_Bit_Index + 1;
+ r_SM_Main <= s_RX_DATA_BITS;
+ end
+ else
+ begin
+ r_Bit_Index <= 0;
+ r_SM_Main <= s_RX_STOP_BIT;
+ end
+ end
+ end // case: s_RX_DATA_BITS
+
+
+ // Receive Stop bit. Stop bit = 1
+ s_RX_STOP_BIT :
+ begin
+ // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
+ if (r_Clock_Count < CLKS_PER_BIT-1)
+ begin
+ r_Clock_Count <= r_Clock_Count + 1;
+ r_SM_Main <= s_RX_STOP_BIT;
+ end
+ else
+ begin
+ r_Rx_DV <= 1'b1;
+ r_Clock_Count <= 0;
+ r_SM_Main <= s_CLEANUP;
+ end
+ end // case: s_RX_STOP_BIT
+
+
+ // Stay here 1 clock
+ s_CLEANUP :
+ begin
+ r_SM_Main <= s_IDLE;
+ r_Rx_DV <= 1'b0;
+ end
+
+
+ default :
+ r_SM_Main <= s_IDLE;
+
+ endcase
+ end
+ end
+
+ assign o_Rx_DV = r_Rx_DV;
+ assign o_Rx_Byte = r_Rx_Byte;
+
+endmodule // uart_rx
+
