commit f7bc070147a1bd18c9984a2ad32176ec8358dbe2
author hamzashabbir517 <shabbirhamza517@gmail.com> Mon May 30 02:38:28 2022 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Mon May 30 02:38:28 2022 +0500
tree f29c1c685641cd637c993db499b46c029735cd85
parent ee8f304480aa80b5904b09811c0b4b3820cb2708

Testbench

verilog/dv/FPU_Half/FPU_Half_tb.v

diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v
index fc60c6e..5de42be 100644
--- a/verilog/dv/FPU_Half/FPU_Half_tb.v
+++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -133,7 +133,7 @@
             wait(mprj_io_0 == 16'h7C00);
             wait(mprj_io_0 == 16'h5124);
             wait(mprj_io_0 == 16'h6058);
-            wait(mprj_io_0 == 16'h0000);
+            wait(mprj_io_0 == 16'h8000);
             */
             // Observe Output pins [23:8] for FADD/FSUB
             /*