Pushing the updated files
diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v index 2262050..9a01a9b 100644 --- a/verilog/dv/FPU_Half/FPU_Half_tb.v +++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -17,9 +17,9 @@ `timescale 1 ns / 1 ps -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" +//`include "uprj_netlists.v" +//`include "caravel_netlists.v" +//`include "spiflash.v" `include "tb_prog.v" module FPU_Half_tb(); @@ -48,7 +48,7 @@ initial begin $dumpfile("FPU_Half.vcd"); - $dumpvars(0, FPU_Half); + $dumpvars(0, FPU_Half_tb); // Repeat cycles of 1000 clock edges as needed to complete testbench //repeat (300) begin
diff --git a/verilog/dv/FPU_Half/Makefile b/verilog/dv/FPU_Half/Makefile index fdf48e7..3fd0b56 100644 --- a/verilog/dv/FPU_Half/Makefile +++ b/verilog/dv/FPU_Half/Makefile
@@ -14,66 +14,19 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_RTL_PATH_FPU = $(UPRJ_VERILOG_PATH)/rtl/FPU/ -UPRJ_BEHAVIOURAL_MODELS = ../ + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) -## RISCV GCC -#GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -#PDK_PATH?=/ef/tech/SW/sky130A +# ---- Include Partitioned Makefiles ---- -## Simulation mode: RTL/GL -SIM?=RTL +CONFIG = caravel_user_project -.SUFFIXES: -PATTERN = FPU_Half +include $(MCW_ROOT)/verilog/dv/make/env.makefile +include $(MCW_ROOT)/verilog/dv/make/var.makefile +include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +include $(MCW_ROOT)/verilog/dv/make/sim.makefile -all: ${PATTERN:=.vcd} -hex: ${PATTERN:=.hex} - -%.vvp: %_tb.v %.hex -ifeq ($(SIM),RTL) - iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH_FPU) -I $(UPRJ_RTL_PATH) \ - $< -o $@ -else - iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH_FPU) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log - -.PHONY: clean hex all
diff --git a/verilog/dv/FPU_Half/tb_prog.v b/verilog/dv/FPU_Half/tb_prog.v new file mode 100644 index 0000000..88e1944 --- /dev/null +++ b/verilog/dv/FPU_Half/tb_prog.v
@@ -0,0 +1,105 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ns / 1ps + +module uartprog #( + parameter FILENAME="program.hex" +)( + input mprj_ready, + output reg r_Rx_Serial // used by task UART_WRITE_BYTE +); + +reg r_Clock = 0; +parameter c_BIT_PERIOD = 8681; // used by task UART_WRITE_BYTE +parameter c_CLOCK_PERIOD_NS = 100; + +reg [7:0] INSTR [16384-1:0]; +integer instr_count = 0; +reg ready; +reg test; + +always @ ( posedge r_Clock ) begin + if (mprj_ready) begin + ready <= 1'b1; + end else begin + ready <= 1'b0; + end +end + +initial begin + $readmemh(FILENAME,INSTR); +end + +task UART_WRITE_BYTE; + input [7:0] i_Data; + integer ii; + begin + // Send Start Bit + r_Rx_Serial <= 1'b0; + #(c_BIT_PERIOD); + #1000; + + // Send Data Byte + for (ii=0; ii<8; ii=ii+1) begin + r_Rx_Serial <= i_Data[ii]; + #(c_BIT_PERIOD); + end + + // Send Stop Bit + r_Rx_Serial <= 1'b1; + #(c_BIT_PERIOD); + end +endtask // UART_WRITE_BYTE + +initial begin + test = 1'b0; + #1000 test = 1'b1; +end + +always + #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock; + +initial begin + r_Rx_Serial <= 1'b1; + #2000; + while (!ready && test) begin + @(posedge r_Clock) + r_Rx_Serial <= 1'b1; + end + while ((instr_count < 16384) && ({INSTR[instr_count],INSTR[instr_count+1],INSTR[instr_count+2],INSTR[instr_count+3]} != 32'h00000FFF)) begin + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count][7:0]); + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count+1][7:0]); + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count+2][7:0]); + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count+3][7:0]); + @(posedge r_Clock); + instr_count = instr_count + 32'd4; + end + @(posedge r_Clock); + UART_WRITE_BYTE(8'h00); + @(posedge r_Clock); + UART_WRITE_BYTE(8'h00); + @(posedge r_Clock); + UART_WRITE_BYTE(8'h0F); + @(posedge r_Clock); + UART_WRITE_BYTE(8'hFF); + @(posedge r_Clock); +end + +endmodule
diff --git a/verilog/rtl/FPU/Dec_gpr_ctl.v b/verilog/rtl/FPU/Dec_gpr_ctl.v index 384bde4..ad2c597 100644 --- a/verilog/rtl/FPU/Dec_gpr_ctl.v +++ b/verilog/rtl/FPU/Dec_gpr_ctl.v
@@ -31,8 +31,9 @@ // GPR Write Enables assign gpr_wr_en[31:1] = (rst_l == 1'b0) ? {31{1'b1}} : (w0v[31:1]); +genvar j; generate - for (genvar j=1; j<32; j=j+1) + for (j=1; j<32; j=j+1) rvdffe #(32) gprff (.*, .en(gpr_wr_en[j]), .din(gpr_in[j][XLEN-1:0]), .dout(gpr_out[j][XLEN-1:0])); endgenerate @@ -42,18 +43,18 @@ assign rd1 = (rst_l == 1'b0) ? {XLEN{1'b0}} : ((rden1 == 1'b1) & (raddr1 != 5'b00000)) ? gpr_out[raddr1][XLEN-1:0] : {XLEN{1'b0}}; // GPR write logic -integer j; +integer p; always @(*) begin if(rst_l == 1'b0) begin w0v = 32'h00000000; - for(j=1; j<32; j=j+1) begin - gpr_in[j] = {XLEN{1'b0}}; + for(p=1; p<32; p=p+1) begin + gpr_in[p] = {XLEN{1'b0}}; end end else begin - for (int j=1; j<32; j=j+1) begin - w0v[j] = wen0 & (waddr0[4:0] == j ); - gpr_in[j] = ({XLEN{w0v[j]}} & wd0[XLEN-1:0]); + for (p=1; p<32; p=p+1) begin + w0v[p] = wen0 & (waddr0[4:0] == p ); + gpr_in[p] = ({XLEN{w0v[p]}} & wd0[XLEN-1:0]); end end end
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v index 08d4cfa..6c200da 100644 --- a/verilog/rtl/FPU/FPU_FSM_TOP.v +++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -1,4 +1,4 @@ -`include "FPU_FSM_Control_Decode.v" +/*`include "FPU_FSM_Control_Decode.v" `include "Sky130_SRAM_1kbyte_Memory.v" `include "uart_rx_prog.v" `include "iccm_controller.v" @@ -47,7 +47,7 @@ `include "LZD_main.v" `include "LZD_mux.v" `include "LZD_comb.v" - +*/ module FPU_FSM_TOP(r_Rx_Serial,clk,rst_l); @@ -219,4 +219,4 @@ $dumpvars(0); end -endmodule \ No newline at end of file +endmodule
diff --git a/verilog/rtl/FPU/FPU_exu.v b/verilog/rtl/FPU/FPU_exu.v index 1e11800..eaa4786 100644 --- a/verilog/rtl/FPU/FPU_exu.v +++ b/verilog/rtl/FPU/FPU_exu.v
@@ -25,7 +25,7 @@ ); -reg [23:0] sfpu_op_r; +wire [23:0] sfpu_op_r; reg sfpu_alu_valid_r; wire [FPLEN-1:0] fs1_d; wire [FPLEN-1:0] fs2_d;
diff --git a/verilog/rtl/FPU/FPU_fpr_ctl.v b/verilog/rtl/FPU/FPU_fpr_ctl.v index 7b1c185..fd0ea3f 100644 --- a/verilog/rtl/FPU/FPU_fpr_ctl.v +++ b/verilog/rtl/FPU/FPU_fpr_ctl.v
@@ -47,11 +47,11 @@ // FPR Write Enables assign fpr_wr_en[31:0] = (rst_l == 1'b0) ? {32{1'b1}} : (w0v[31:0]); - + +genvar j; generate - for (genvar j=0; j<32; j++) begin : fpr + for (j=0; j<32; j=j+1) rvdffe #(16) fprff (.*, .en(fpr_wr_en[j]), .din(fpr_in[j][FPLEN-1:0]), .dout(fpr_out[j][FPLEN-1:0])); - end : fpr endgenerate @@ -61,18 +61,18 @@ assign rd2 = (rst_l == 1'b0) ? {FPLEN{1'b0}} : ((rden2 == 1'b1)) ? fpr_out[raddr2][FPLEN-1:0] : {FPLEN{1'b0}}; // FPR write logic -integer j; +integer q; always @(*) begin if(rst_l == 1'b0) begin w0v = 32'h00000000; - for(j=0; j<32; j=j+1) begin - fpr_in[j] = {FPLEN{1'b0}}; + for(q=0; q<32; q=q+1) begin + fpr_in[q] = {FPLEN{1'b0}}; end end else begin - for (int j=0; j<32; j++ ) begin - w0v[j] = wen0 & (waddr0[4:0] == j ); - fpr_in[j] = ({FPLEN{w0v[j]}} & wd0[FPLEN-1:0]); + for (q=0; q<32; q=q+1) begin + w0v[q] = wen0 & (waddr0[4:0] == q ); + fpr_in[q] = ({FPLEN{w0v[q]}} & wd0[FPLEN-1:0]); end end end
diff --git a/verilog/rtl/FPU/Main_Decode.v b/verilog/rtl/FPU/Main_Decode.v index 4bf7239..99956ec 100644 --- a/verilog/rtl/FPU/Main_Decode.v +++ b/verilog/rtl/FPU/Main_Decode.v
@@ -17,7 +17,8 @@ wire [2:0] fpu_rnd,Fpu_Frm; wire [11:0]IMM_ADDI,CSR_Addr; wire [31:0]IMM_LI; - reg [4:0]rd,rd_address; + reg [4:0]rd; + wire [4:0] rd_address; wire [4:0]rs1,rs2,rs1_address,rs2_address; //reg [31:0]Instruction_reg; wire [31:0]gpr_rs1,gpr_rs2; @@ -148,4 +149,4 @@ assign dec_i0_rs2_en_d = (~rst_l) ? 1'b0 : rs2_en; assign sfpu_op = (~rst_l) ? 24'b000000 : sfpu_op_w; -endmodule \ No newline at end of file +endmodule