Bit mismatch solve
diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v
index 23db252..e5e9efc 100644
--- a/verilog/dv/FPU_Half/FPU_Half_tb.v
+++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -125,6 +125,7 @@
wait(mprj_io_0 == 16'hBCF0);
*/
// Observe Output pins [23:8] for FMUL
+ /*
wait(mprj_io_0 == 16'h60C2);
wait(mprj_io_0 == 16'h30A7);
wait(mprj_io_0 == 16'h67FF);
@@ -133,6 +134,25 @@
wait(mprj_io_0 == 16'h5124);
wait(mprj_io_0 == 16'h6058);
wait(mprj_io_0 == 16'h0000);
+ */
+ // Observe Output pins [23:8] for FADD/FSUB
+
+ wait(mprj_io_0 == 16'h5848);
+ wait(mprj_io_0 == 16'h3CE7);
+ wait(mprj_io_0 == 16'h5A92);
+ wait(mprj_io_0 == 16'h5E40);
+ wait(mprj_io_0 == 16'hE09C);
+ wait(mprj_io_0 == 16'hDCDA);
+ wait(mprj_io_0 == 16'hDF0E);
+ wait(mprj_io_0 == 16'h0000);
+ wait(mprj_io_0 == 16'hD7FC);
+ wait(mprj_io_0 == 16'hBBAE);
+ wait(mprj_io_0 == 16'hD9EE);
+ wait(mprj_io_0 == 16'h4D20);
+ wait(mprj_io_0 == 16'hC920);
+ wait(mprj_io_0 == 16'hDCD8);
+ wait(mprj_io_0 == 16'hDF04);
+ wait(mprj_io_0 == 16'hBD78);
$display("MPRJ-IO state = %h", mprj_io[23:8]);
diff --git a/verilog/rtl/FPU/Dec_gpr_ctl.v b/verilog/rtl/FPU/Dec_gpr_ctl.v
index ad2c597..babaa54 100644
--- a/verilog/rtl/FPU/Dec_gpr_ctl.v
+++ b/verilog/rtl/FPU/Dec_gpr_ctl.v
@@ -46,7 +46,7 @@
integer p;
always @(*) begin
if(rst_l == 1'b0) begin
- w0v = 32'h00000000;
+ w0v = 31'h00000000;
for(p=1; p<32; p=p+1) begin
gpr_in[p] = {XLEN{1'b0}};
end
diff --git a/verilog/rtl/FPU/FPU_decode.v b/verilog/rtl/FPU/FPU_decode.v
index ca3d2f5..cc706fb 100644
--- a/verilog/rtl/FPU/FPU_decode.v
+++ b/verilog/rtl/FPU/FPU_decode.v
@@ -101,7 +101,7 @@
always @(posedge clk) begin
if(rst_l == 1'b0 | illegal_config)
begin
- control_signals_r <= 114'h0;
+ control_signals_r <= 115'h0;
end
else
@@ -113,7 +113,7 @@
end
else if((~valid_execution) | ((~fpu_active) & (fpu_complete)))
begin
- control_signals_r <= 114'h0;
+ control_signals_r <= 115'h0;
end
else
begin
diff --git a/verilog/rtl/FPU/beh_lib.v b/verilog/rtl/FPU/beh_lib.v
index 32a2894..67b166f 100644
--- a/verilog/rtl/FPU/beh_lib.v
+++ b/verilog/rtl/FPU/beh_lib.v
@@ -18,7 +18,7 @@
end
else always @(posedge clk or negedge rst_l)
if (rst_l == 0)
- dout[WIDTH - 1:0] <= 0;
+ dout[WIDTH - 1:0] <= {{WIDTH{0}};
else
dout[WIDTH - 1:0] <= din[WIDTH - 1:0];
endgenerate
@@ -707,4 +707,4 @@
wire SE;
assign SE = 0;
assign l1clk = clk;
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/FPU/iccm_controller.v b/verilog/rtl/FPU/iccm_controller.v
index 611396f..21544ac 100644
--- a/verilog/rtl/FPU/iccm_controller.v
+++ b/verilog/rtl/FPU/iccm_controller.v
@@ -71,7 +71,7 @@
ctrl_fsm_ns = LOAD;
else
ctrl_fsm_ns = DONE;
- default: ctrl_fsm_ns = RESET;
+ //default: ctrl_fsm_ns = RESET;
endcase
end
assign rx_byte_d = rx_byte_i;
@@ -82,7 +82,7 @@
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
we_q <= 1'b0;
- addr_q <= 13'b0000000000000;
+ addr_q <= 14'b00000000000000;
rx_byte_q0 <= 8'b00000000;
rx_byte_q1 <= 8'b00000000;
rx_byte_q2 <= 8'b00000000;
diff --git a/verilog/rtl/FPU/uart_rx_prog.v b/verilog/rtl/FPU/uart_rx_prog.v
index 7af5031..7a046df 100644
--- a/verilog/rtl/FPU/uart_rx_prog.v
+++ b/verilog/rtl/FPU/uart_rx_prog.v
@@ -53,8 +53,8 @@
s_IDLE :
begin
r_Rx_DV <= 1'b0;
- r_Clock_Count <= 0;
- r_Bit_Index <= 0;
+ r_Clock_Count <= 16'h0000;
+ r_Bit_Index <= 3'b000;
if (r_Rx_Data == 1'b0) // Start bit detected
r_SM_Main <= s_RX_START_BIT;
@@ -69,7 +69,7 @@
begin
if (r_Rx_Data == 1'b0)
begin
- r_Clock_Count <= 0; // reset counter, found the middle
+ r_Clock_Count <= 16'h0000; // reset counter, found the middle
r_SM_Main <= s_RX_DATA_BITS;
end
else
@@ -77,7 +77,7 @@
end
else
begin
- r_Clock_Count <= r_Clock_Count + 1;
+ r_Clock_Count <= r_Clock_Count + 16'd1;
r_SM_Main <= s_RX_START_BIT;
end
end // case: s_RX_START_BIT
@@ -88,23 +88,23 @@
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
- r_Clock_Count <= r_Clock_Count + 1;
+ r_Clock_Count <= r_Clock_Count + 16'd1;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
- r_Clock_Count <= 0;
+ r_Clock_Count <= 16'h0000;
r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
// Check if we have received all bits
if (r_Bit_Index < 7)
begin
- r_Bit_Index <= r_Bit_Index + 1;
+ r_Bit_Index <= r_Bit_Index + 3'b001;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
- r_Bit_Index <= 0;
+ r_Bit_Index <= 3'b000;
r_SM_Main <= s_RX_STOP_BIT;
end
end
@@ -117,13 +117,13 @@
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
- r_Clock_Count <= r_Clock_Count + 1;
+ r_Clock_Count <= r_Clock_Count + 16'd1;
r_SM_Main <= s_RX_STOP_BIT;
end
else
begin
r_Rx_DV <= 1'b1;
- r_Clock_Count <= 0;
+ r_Clock_Count <= 16'h0000;
r_SM_Main <= s_CLEANUP;
end
end // case: s_RX_STOP_BIT
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 222fde8..5ef6c51 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -94,7 +94,7 @@
// Ouptut at LA bits [31:16]
assign la_data_out[31:0] = 32'h00000000;
assign la_data_out[47:32] = (&la_oenb[47:32]) ? FPU_hp_result : 16'h0000;
- assign la_data_out[127:48] = {79{1'b0}};
+ assign la_data_out[127:48] = {80{1'b0}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = (~la_oenb[64]) ? la_data_in[64] : wb_clk_i;
